CoreSight

coresight@lists.linaro.org

9 participants
2379 discussions

Re: [PATCH v4 02/15] arm64: errata: Add detection for TRBE overwrite in FILL mode

by Suzuki K Poulose

Hi Thanks for the report. I have fixed all of them. Suzuki On 12/10/2021 16:31, Randy Dunlap wrote: > Hi, > > On 10/12/21 6:17 AM, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 077f2ec4eeb2..404f56e87e93 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -666,6 +666,47 @@ config ARM64_ERRATUM_1508412 >> If unsure, say Y. >> +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + bool >> + >> +config ARM64_ERRATUM_2119858 >> + bool "Cortex-A710: 2119858: workaround TRBE overwriting trace >> data in FILL mode" >> + default y >> + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes >> are in >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Cortex-A710 erratum >> 2119858. >> + >> + Affected Cortex-A710 cores could overwrite upto 3 cache lines >> of trace > > up to > >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL >> mode in > > pointed to by > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the >> TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first >> 256bytes of > > 256 bytes 256 bytes > >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2139208 >> + bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace >> data in FILL mode" >> + default y >> + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes >> are in >> + depends on CORESIGHT_TRBE >> + select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >> + help >> + This option adds the workaround for ARM Neoverse-N2 erratum >> 2139208. >> + >> + Affected Neoverse-N2 cores could overwrite upto 3 cache lines >> of trace > > up to > >> + data at the base of the buffer (ponited by TRBASER_EL1) in FILL >> mode in > > pointed to by > >> + the event of a WRAP event. >> + >> + Work around the issue by always making sure we move the >> TRBPTR_EL1 by >> + 256bytes before enabling the buffer and filling the first >> 256bytes of > > 256 bytes 256 bytes > >> + the buffer with ETM ignore packets upon disabling. >> + >> + If unsure, say Y. > >

3 years, 8 months

Re: [PATCH] coresight: trbe: Defer the probe on offline CPUs

by Suzuki K Poulose

On 14/10/2021 04:28, Anshuman Khandual wrote: > Hi Suzuki, > > On 10/13/21 10:03 PM, Suzuki K Poulose wrote: >> If a CPU is offline during the driver init, we could end up causing >> a kernel crash trying to register the coresight device for the TRBE >> instance. > > Which pointer deference fails here exactly ? > > static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) > { > struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); > struct coresight_device *trbe_csdev = coresight_get_percpu_sink(cpu); > struct coresight_desc desc = { 0 }; > struct device *dev; > > if (WARN_ON(trbe_csdev)) > return; > > dev = &cpudata->drvdata->pdev->dev; <---- Fails here > > cpudata->drvdata link gets established in arm_trbe_probe_cpu() which > would not have run on an offline cpu. Yes, that is correct. > >> >> e.g: > > Should probably also mention the exact point of dereference failure > before this error message here. > >> >> [ 0.149999] coresight ete0: CPU0: ete v1.1 initialized >> [ 0.149999] coresight-etm4x ete_1: ETM arch init failed >> [ 0.149999] coresight-etm4x: probe of ete_1 failed with error -22 >> [ 0.150085] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000050 >> [ 0.150085] Mem abort info: >> [ 0.150085] ESR = 0x96000005 >> [ 0.150085] EC = 0x25: DABT (current EL), IL = 32 bits >> [ 0.150085] SET = 0, FnV = 0 >> [ 0.150085] EA = 0, S1PTW = 0 >> [ 0.150085] Data abort info: >> [ 0.150085] ISV = 0, ISS = 0x00000005 >> [ 0.150085] CM = 0, WnR = 0 >> [ 0.150085] [0000000000000050] user address but active_mm is swapper >> [ 0.150085] Internal error: Oops: 96000005 [#1] PREEMPT SMP >> [ 0.150085] Modules linked in: >> [ 0.150085] Hardware name: FVP Base RevC (DT) >> [ 0.150085] pstate: 00800009 (nzcv daif -PAN +UAO -TCO BTYPE=--) >> [ 0.150155] pc : arm_trbe_register_coresight_cpu+0x74/0x144 >> [ 0.150155] lr : arm_trbe_register_coresight_cpu+0x48/0x144 >> ... >> >> [ 0.150237] Call trace: >> [ 0.150237] arm_trbe_register_coresight_cpu+0x74/0x144 >> [ 0.150237] arm_trbe_device_probe+0x1c0/0x2d8 >> [ 0.150259] platform_drv_probe+0x94/0xbc >> [ 0.150259] really_probe+0x1bc/0x4a8 >> [ 0.150266] driver_probe_device+0x7c/0xb8 >> [ 0.150266] device_driver_attach+0x6c/0xac >> [ 0.150266] __driver_attach+0xc4/0x148 >> [ 0.150266] bus_for_each_dev+0x7c/0xc8 >> [ 0.150266] driver_attach+0x24/0x30 >> [ 0.150266] bus_add_driver+0x100/0x1e0 >> [ 0.150266] driver_register+0x78/0x110 >> [ 0.150266] __platform_driver_register+0x44/0x50 >> [ 0.150266] arm_trbe_init+0x28/0x84 >> [ 0.150266] do_one_initcall+0x94/0x2bc >> [ 0.150266] do_initcall_level+0xa4/0x158 >> [ 0.150266] do_initcalls+0x54/0x94 >> [ 0.150319] do_basic_setup+0x24/0x30 >> [ 0.150319] kernel_init_freeable+0xe8/0x14c >> [ 0.150319] kernel_init+0x14/0x18c >> [ 0.150319] ret_from_fork+0x10/0x30 >> [ 0.150319] Code: f94012c8 b0004ce2 9134a442 52819801 (f9402917) >> [ 0.150319] ---[ end trace d23e0cfe5098535e ]--- >> [ 0.150346] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b >> >> Fix this by skipping the step, if we are unable to probe the CPU. >> >> Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") >> Reported-by: Bransilav Rankov <branislav.rankov(a)arm.com> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Mike Leach <mike.leach(a)linaro.org> >> Cc: Leo Yan <leo.yan(a)linaro.org> >> Tested-by: Branislav Rankov <branislav.rankov(a)arm.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >> index 5d350acef798..85ceda68af82 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -1286,7 +1286,9 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata) >> return -ENOMEM; >> >> for_each_cpu(cpu, &drvdata->supported_cpus) { >> - smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1); >> + /* If we fail to probe the CPU, let us defer it to hotplug callbacks */ >> + if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1)) >> + continue; >> if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> arm_trbe_register_coresight_cpu(drvdata, cpu); >> if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> > > Right, LGTM. Although I guess the following addition might be worthwhile > just to highlight the fact that cpudata->drvdata is not valid unless the > cpu has gone through arm_trbe_probe_cpu() first. > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -869,6 +869,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp > if (WARN_ON(trbe_csdev)) > return; > > + WARN_ON(!cpudata->drvdata); Ok, I would rather return here with the warning. I will send a revision. Thanks ! Suzuki

3 years, 8 months

[PATCH] coresight: trbe: Defer the probe on offline CPUs

by Suzuki K Poulose

If a CPU is offline during the driver init, we could end up causing a kernel crash trying to register the coresight device for the TRBE instance. e.g: [ 0.149999] coresight ete0: CPU0: ete v1.1 initialized [ 0.149999] coresight-etm4x ete_1: ETM arch init failed [ 0.149999] coresight-etm4x: probe of ete_1 failed with error -22 [ 0.150085] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000050 [ 0.150085] Mem abort info: [ 0.150085] ESR = 0x96000005 [ 0.150085] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.150085] SET = 0, FnV = 0 [ 0.150085] EA = 0, S1PTW = 0 [ 0.150085] Data abort info: [ 0.150085] ISV = 0, ISS = 0x00000005 [ 0.150085] CM = 0, WnR = 0 [ 0.150085] [0000000000000050] user address but active_mm is swapper [ 0.150085] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 0.150085] Modules linked in: [ 0.150085] Hardware name: FVP Base RevC (DT) [ 0.150085] pstate: 00800009 (nzcv daif -PAN +UAO -TCO BTYPE=--) [ 0.150155] pc : arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150155] lr : arm_trbe_register_coresight_cpu+0x48/0x144 ... [ 0.150237] Call trace: [ 0.150237] arm_trbe_register_coresight_cpu+0x74/0x144 [ 0.150237] arm_trbe_device_probe+0x1c0/0x2d8 [ 0.150259] platform_drv_probe+0x94/0xbc [ 0.150259] really_probe+0x1bc/0x4a8 [ 0.150266] driver_probe_device+0x7c/0xb8 [ 0.150266] device_driver_attach+0x6c/0xac [ 0.150266] __driver_attach+0xc4/0x148 [ 0.150266] bus_for_each_dev+0x7c/0xc8 [ 0.150266] driver_attach+0x24/0x30 [ 0.150266] bus_add_driver+0x100/0x1e0 [ 0.150266] driver_register+0x78/0x110 [ 0.150266] __platform_driver_register+0x44/0x50 [ 0.150266] arm_trbe_init+0x28/0x84 [ 0.150266] do_one_initcall+0x94/0x2bc [ 0.150266] do_initcall_level+0xa4/0x158 [ 0.150266] do_initcalls+0x54/0x94 [ 0.150319] do_basic_setup+0x24/0x30 [ 0.150319] kernel_init_freeable+0xe8/0x14c [ 0.150319] kernel_init+0x14/0x18c [ 0.150319] ret_from_fork+0x10/0x30 [ 0.150319] Code: f94012c8 b0004ce2 9134a442 52819801 (f9402917) [ 0.150319] ---[ end trace d23e0cfe5098535e ]--- [ 0.150346] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b Fix this by skipping the step, if we are unable to probe the CPU. Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") Reported-by: Bransilav Rankov <branislav.rankov(a)arm.com> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Tested-by: Branislav Rankov <branislav.rankov(a)arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-trbe.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 5d350acef798..85ceda68af82 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1286,7 +1286,9 @@ static int arm_trbe_probe_coresight(struct trbe_drvdata *drvdata) return -ENOMEM; for_each_cpu(cpu, &drvdata->supported_cpus) { - smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1); + /* If we fail to probe the CPU, let us defer it to hotplug callbacks */ + if (smp_call_function_single(cpu, arm_trbe_probe_cpu, drvdata, 1)) + continue; if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) arm_trbe_register_coresight_cpu(drvdata, cpu); if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) -- 2.25.4

3 years, 8 months

[PATCH v4 00/15] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. The Kconfig items for the TRBE errata are initially dropped in with dependency on COMPILE_TEST. These are dropped only after the driver is equipped with the work around in later patches. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v4 Changes since v3: - Fix missing Kconfig selection for TSB flush failure erratum (Will) Merged the Kconfig changes to the core patch for TSB. - Use COMPILE_TEST dependency for the TRBE work arounds instead of delaying the Kconfig entries. Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (15): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 111 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 382 +++++++++++++++++-- 7 files changed, 556 insertions(+), 36 deletions(-) -- 2.25.4

3 years, 8 months

Re: [PATCH 4/5] perf arm-spe: Implement find_snapshot callback

by James Clark

On 12/10/2021 09:19, Will Deacon wrote: > On Mon, Oct 11, 2021 at 04:55:37PM +0100, German Gomez wrote: >> Hi Leo, >> >> On 06/10/2021 10:51, Leo Yan wrote: >>> On Wed, Oct 06, 2021 at 10:35:20AM +0100, German Gomez wrote: >>> >>> [...] >>> >>>>> So simply say, I think the head pointer monotonically increasing is >>>>> the right thing to do in Arm SPE driver. >>>> I will talk to James about how we can proceed on this. >>> Thanks! >> >> I took this offline with James and, though it looks possible to patch >> the SPE driver to have a monotonically increasing head pointer in order >> to simplify the handling in the perf tool, it could be a breaking change >> for users of the perf_event_open syscall that currently rely on the way >> it works now. >> >> An alternative way we considered to simplify the patch is to change the >> logic inside the find_snapshot callback so that it records the entire >> contents of the aux buffer every time. >> >> What do you think? > > What does intel-pt do? Intel-pt has a wrapped head, which is why it has the intel_pt_find_snapshot() function in perf to try to not save any zeros from the buffer that haven't been written yet. (With a wrapped head pointer it's impossible to tell). Coresight has a monotonically increasing head pointer so it is possible to tell. Recently, Leo removed the Coresight version of find_snapshot() for this reason. It would be nice to do the same for SPE because that function has a heuristic and is also slow, but I imagine that not returning wrapped head pointers could break anything that expects them. James > > Will >

3 years, 8 months

Re: [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures

by Suzuki K Poulose

On 11/10/2021 11:18, Will Deacon wrote: > On Fri, Oct 08, 2021 at 07:29:05PM +0100, Suzuki K Poulose wrote: >> Advertise the workaround for the TSB flush failures via >> Kconfig entries. >> >> Cc: Will Deacon <will(a)kernel.org> >> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Marc Zyngier <maz(a)kernel.org> >> Reviewed-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Acked-by: Catalin Marinas <catalin.marinas(a)arm.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> Changes since previous: >> - Split the Kconfig/erratum updates to keep the conflicts >> minimal with the other Kconfig updates in TRBE errata >> I have retained the tags >> --- >> Documentation/arm64/silicon-errata.rst | 4 ++++ >> arch/arm64/Kconfig | 31 ++++++++++++++++++++++++++ >> 2 files changed, 35 insertions(+) >> >> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >> index 2f99229d993c..569a92411dcd 100644 >> --- a/Documentation/arm64/silicon-errata.rst >> +++ b/Documentation/arm64/silicon-errata.rst >> @@ -94,6 +94,8 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N1 | #1349291 | N/A | >> @@ -102,6 +104,8 @@ stable kernels. >> +----------------+-----------------+-----------------+-----------------------------+ >> | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | >> +----------------+-----------------+-----------------+-----------------------------+ >> +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | >> ++----------------+-----------------+-----------------+-----------------------------+ >> | ARM | MMU-500 | #841119,826419 | N/A | >> +----------------+-----------------+-----------------+-----------------------------+ >> +----------------+-----------------+-----------------+-----------------------------+ >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index eac4030322df..0764774e12bb 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -705,6 +705,37 @@ config ARM64_ERRATUM_2139208 >> >> If unsure, say Y. >> >> +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> + bool >> + >> +config ARM64_ERRATUM_2054223 >> + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" >> + default y >> + help >> + Enable workaround for ARM Cortex-A710 erratum 2054223 >> + >> + Affected cores may fail to flush the trace data on a TSB instruction, when >> + the PE is in trace prohibited state. This will cause losing a few bytes >> + of the trace cached. >> + >> + Workaround is to issue two TSB consecutively on affected cores. >> + >> + If unsure, say Y. >> + >> +config ARM64_ERRATUM_2067961 >> + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" >> + default y >> + help >> + Enable workaround for ARM Neoverse-N2 erratum 2067961 >> + >> + Affected cores may fail to flush the trace data on a TSB instruction, when >> + the PE is in trace prohibited state. This will cause losing a few bytes >> + of the trace cached. >> + >> + Workaround is to issue two TSB consecutively on affected cores. >> + >> + If unsure, say Y. > > Shouldn't these two be selecting the workaround? doh! I have given myself a slap for this and fixed it locally. Suzuki

3 years, 8 months

[PATCH v3 00/16] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on coresight/next. The series has been reordered to make it easier to merge the patches via arm64 tree and the coresight tree. Patches 1-4 are could be picked up via arm64 tree. The rest can go via the coresight tree. All Kconfig changes are at the end of the series and could go via the coresight tree to make sure that the work arounds are available in the final tree before they can be selected by the user. A tree is available here : git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v3 Changes since v2: * https://lkml.kernel.org/r/20210921134121.2423546-1-suzuki.poulose@arm.com - Dropped patch adding a helper to reach cpudata from perf handle - Split the TSB erratum work around patch to split the Kconfig/erratum list update changes(pushed to the end of the series). - Added wrappers to check the erratum : trbe_has_erratum(cpudata, TRBE_ERRATUM_<TITLE>) -> trbe_may_<title> - More ASCII art explanation on workaround. Changes since v1: * https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (16): for arm64 tree arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range for CoreSight tree coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Advertise workaround for TRBE overwrite in FILL mode arm64: errata: Advertise the workaround for TSB flush failures arm64: errata: Advertise TRBE erratum workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 109 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 382 +++++++++++++++++-- 7 files changed, 554 insertions(+), 36 deletions(-) -- 2.25.4

3 years, 8 months

Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

On 08/10/2021 10:52, Will Deacon wrote: > On Fri, Oct 08, 2021 at 10:25:03AM +0100, Suzuki K Poulose wrote: >> Hi Will >> >> On 08/10/2021 08:32, Will Deacon wrote: >>> Hi Suzuki, >>> >>> On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote: >>>> This series adds CPU erratum work arounds related to the self-hosted >>>> tracing. The list of affected errata handled in this series are : >>>> >>>> * TRBE may overwrite trace in FILL mode >>>> - Arm Neoverse-N2 #2139208 >>>> - Cortex-A710 #211985 >>>> >>>> * A TSB instruction may not flush the trace completely when executed >>>> in trace prohibited region. >>>> >>>> - Arm Neoverse-N2 #2067961 >>>> - Cortex-A710 #2054223 >>>> >>>> * TRBE may write to out-of-range address >>>> - Arm Neoverse-N2 #2253138 >>>> - Cortex-A710 #2224489 >>>> >>>> The series applies on the self-hosted/trbe fixes posted here [0]. >>>> A tree containing both the series is available here [1] >>> >>> Any chance you could put the arch/arm64/ bits at the start of the series, >>> please? That way, I can queue them on their own branch which can be shared >>> with the coresight tree. >> >> I could move the bits around. I have a question though. >> >> Will, Catalin, Mathieu, >> >> The workaround for these errata, at least two of them are >> in the TRBE driver patches. Are we happy with enabling the Kconfig >> entry in the kernel, without the CoreSight patches to implement the work >> around ? > > I suppose you could move all the Kconfig changes into their own patch and > stick it right at the end in the Coresight tree. Cool, I will do that then. Thanks. I will send the updated series. Suzuki

3 years, 8 months

Re: [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

Hi Will On 08/10/2021 08:32, Will Deacon wrote: > Hi Suzuki, > > On Tue, Sep 21, 2021 at 02:41:04PM +0100, Suzuki K Poulose wrote: >> This series adds CPU erratum work arounds related to the self-hosted >> tracing. The list of affected errata handled in this series are : >> >> * TRBE may overwrite trace in FILL mode >> - Arm Neoverse-N2 #2139208 >> - Cortex-A710 #211985 >> >> * A TSB instruction may not flush the trace completely when executed >> in trace prohibited region. >> >> - Arm Neoverse-N2 #2067961 >> - Cortex-A710 #2054223 >> >> * TRBE may write to out-of-range address >> - Arm Neoverse-N2 #2253138 >> - Cortex-A710 #2224489 >> >> The series applies on the self-hosted/trbe fixes posted here [0]. >> A tree containing both the series is available here [1] > > Any chance you could put the arch/arm64/ bits at the start of the series, > please? That way, I can queue them on their own branch which can be shared > with the coresight tree. I could move the bits around. I have a question though. Will, Catalin, Mathieu, The workaround for these errata, at least two of them are in the TRBE driver patches. Are we happy with enabling the Kconfig entry in the kernel, without the CoreSight patches to implement the work around ? Suzuki

3 years, 8 months

[PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds

by Suzuki K Poulose

This series adds CPU erratum work arounds related to the self-hosted tracing. The list of affected errata handled in this series are : * TRBE may overwrite trace in FILL mode - Arm Neoverse-N2 #2139208 - Cortex-A710 #211985 * A TSB instruction may not flush the trace completely when executed in trace prohibited region. - Arm Neoverse-N2 #2067961 - Cortex-A710 #2054223 * TRBE may write to out-of-range address - Arm Neoverse-N2 #2253138 - Cortex-A710 #2224489 The series applies on the self-hosted/trbe fixes posted here [0]. A tree containing both the series is available here [1] [0] https://lkml.kernel.org/r/20210914102641.1852544-1-suzuki.poulose@arm.com [1] git@git.gitlab.arm.com:linux-arm/linux-skp.git coresight/errata/trbe-tsb-n2-a710/v2 Changes since v1: https://lkml.kernel.org/r/20210728135217.591173-1-suzuki.poulose@arm.com - Added a fix to the TRBE driver handling of sink_specific data - Added more description and ASCII art for overwrite in FILL mode work around - Added another TRBE erratum to the list. "TRBE may write to out-of-range address" Patches from 12-17 - Added comment to list the expectations around TSB erratum workaround. Suzuki K Poulose (17): coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: Add erratum detection for TRBE overwrite in FILL mode coresight: trbe: Workaround TRBE errata overwrite in FILL mode arm64: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures coresight: trbe: Add a helper to fetch cpudata from perf handle coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space arm64: Add erratum detection for TRBE write to out-of-range coresight: trbe: Work around write to out of range arm64: Advertise TRBE erratum workaround for write to out-of-range address Documentation/arm64/silicon-errata.rst | 12 + arch/arm64/Kconfig | 109 ++++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 ++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 339 +++++++++++++++++-- 7 files changed, 510 insertions(+), 37 deletions(-) -- 2.24.1

3 years, 8 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

CoreSight