Hi Jay,
On Tue, Jan 25, 2022 at 10:33:45AM +0800, Jiankang Chen wrote:
> Hi Mathieu
>
> 在 2022/1/25 04:08, Mathieu Poirier 写道:
> > On Mon, 24 Jan 2022 at 04:00, Jay Chen <jkchen(a)linux.alibaba.com> wrote:
> > > Currently, there are 130 etr and etf on our machine,
> > > but the current coresight tmc driver uses misc_register
> > > to register the device, which leads to the error that
> > > the device number is not enough.
> > >
> > > coresight-tmc: probe of xxxxx failed with error -16
> > >
> > > This patch changes the device registration method
> > > to cdev's dynamic registration method to solve the
> > > problem of insufficient device numbers.
> > This patch is still not labelled properly and as such being dropped.
>
> Hello, about the label of this patch, what kind of patch should I add?
You could use "git format" command with option "-v" to add the version
number, e.g. if you are committing patch version 4, so you can generate
patch like:
$ git format-patch HEAD~1 -v4
Or if you want to generate patch for a specific commit:
$ git format-patch -1 patch_commit -v4
Every time when you generate a new version's patch, you could
increment the version number with option "-v4", "-v5", and so on.
P.s. I strongly suggest Marc Zyngier's great talk for how to upstream
kernel patch in a good way:
https://events19.linuxfoundation.org/wp-content/uploads/2017/12/Getting-You…
Thanks,
Leo
On 24/01/2022 03:15, Anshuman Khandual wrote:
> Errata ARM64_ERRATUM_[2119858|2224489] also affect some Cortex-X2 ranges as
> well. This series updates the errata definition and detection as required.
> This series applies on v5.17-rc1.
>
> Relevant identification document can be found here.
>
> https://developer.arm.com/documentation/101803/0200/AArch64-system-register…
> AArch64-identification-register-summary/MIDR-EL1--Main-ID-Register
>
> Relevant errata document can be found here.
>
> https://developer.arm.com/documentation/SDEN1775100
>
> Cc: Catalin Marinas <catalin.marinas(a)arm.com>
> Cc: Will Deacon <will(a)kernel.org>
> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org>
> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com>
> Cc: coresight(a)lists.linaro.org
> Cc: linux-arm-kernel(a)lists.infradead.org
> Cc: linux-kernel(a)vger.kernel.org
>
For the series:
Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>
The kernel uses open code to check if a process is in root PID namespace
or not in several places.
Suggested by Suzuki, this patch set is to create a helper function
task_is_in_init_pid_ns() to replace open code.
This patch set has been applied on the mainline kernel and built for
Arm64 kernel with enabling all relevant modules.
Changes from v1:
* Renamed helper function from task_is_in_root_ns() to
task_is_in_init_pid_ns(). (Leon Romanovsky)
* Improved patches' commit logs for more neat.
Leo Yan (7):
pid: Introduce helper task_is_in_init_pid_ns()
coresight: etm3x: Use task_is_in_init_pid_ns()
coresight: etm4x: Use task_is_in_init_pid_ns()
connector/cn_proc: Use task_is_in_init_pid_ns()
coda: Use task_is_in_init_pid_ns()
audit: Use task_is_in_init_pid_ns()
taskstats: Use task_is_in_init_pid_ns()
drivers/connector/cn_proc.c | 2 +-
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 8 ++++----
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 8 ++++----
fs/coda/inode.c | 2 +-
fs/coda/psdev.c | 2 +-
include/linux/pid_namespace.h | 5 +++++
kernel/audit.c | 2 +-
kernel/taskstats.c | 2 +-
8 files changed, 18 insertions(+), 13 deletions(-)
--
2.25.1
I was working on refactoring some of the magic numbers for the register
accesses and I saw this issue with programming one of the values.
I don't have any evidence that someone encountered it not working, probably
there is no hardware where QSUPP==0b10, or it just didn't get used yet.
But the issue is that this silently writes a reserved value even if the
user provided one was correct so it might ruin someones day if it ever
comes up.
It's a small change so I didn't see the harm in fixing it.
Applies to coresight/next f9809d565135
James Clark (1):
coresight: Fix TRCCONFIGR.QE sysfs interface
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.17.1
Good morning,
On Mon, Jan 10, 2022 at 07:31:00AM +0000, Miaoqian Lin wrote:
> device_register() calls device_initialize(),
> according to doc of device_initialize:
>
> Use put_device() to give up your reference instead of freeing
> * @dev directly once you have called this function.
That is _if_ device_initialize() is called manually. In this instance
@dev is registered with device_register() and unregistered with
device_unregister(). The latter conforms to the comment you pointed out and
calls put_device() as expected.
Thanks,
Mathieu
>
> To prevent potential memleak, use put_device() instead call kfree
> directly.
>
> Signed-off-by: Miaoqian Lin <linmq006(a)gmail.com>
> ---
> drivers/hwtracing/coresight/coresight-syscfg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-syscfg.c b/drivers/hwtracing/coresight/coresight-syscfg.c
> index 43054568430f..007fa1c761a7 100644
> --- a/drivers/hwtracing/coresight/coresight-syscfg.c
> +++ b/drivers/hwtracing/coresight/coresight-syscfg.c
> @@ -764,7 +764,7 @@ struct device *cscfg_device(void)
> /* Must have a release function or the kernel will complain on module unload */
> static void cscfg_dev_release(struct device *dev)
> {
> - kfree(cscfg_mgr);
> + put_device(dev);
> cscfg_mgr = NULL;
> }
>
> --
> 2.17.1
>
When enabled, all taken branch addresses are output, even if the branch
was because of a direct branch instruction. This enables reconstruction
of the program flow without having access to the memory image of the
code being executed.
Use bit 8 for the config option which would be the correct bit for
programming ETMv3. Although branch broadcast can't be enabled on ETMv3
because it's not in the define ETM3X_SUPPORTED_OPTIONS, using the
correct bit might help prevent future collisions or allow it to be
enabled if needed.
Signed-off-by: James Clark <james.clark(a)arm.com>
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++
drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++++
include/linux/coresight-pmu.h | 2 ++
3 files changed, 13 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index c039b6ae206f..43bbd5dc3d3b 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -52,6 +52,7 @@ static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
* The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config';
* now take them as general formats and apply on all ETMs.
*/
+PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST));
PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC));
/* contextid1 enables tracing CONTEXTIDR_EL1 for ETMv4 */
PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID));
@@ -97,6 +98,7 @@ static struct attribute *etm_config_formats_attr[] = {
&format_attr_sinkid.attr,
&format_attr_preset.attr,
&format_attr_configid.attr,
+ &format_attr_branch_broadcast.attr,
NULL,
};
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index bf18128cf5de..d2bafb50c66a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -692,6 +692,15 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
}
+ /* branch broadcast - enable if selected and supported */
+ if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
+ if (!drvdata->trcbb) {
+ ret = -EINVAL;
+ goto out;
+ } else
+ config->cfg |= BIT(ETM4_CFG_BIT_BB);
+ }
+
out:
return ret;
}
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 4ac5c081af93..6c2fd6cc5a98 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -18,6 +18,7 @@
* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
* directly use below macros as config bits.
*/
+#define ETM_OPT_BRANCH_BROADCAST 8
#define ETM_OPT_CYCACC 12
#define ETM_OPT_CTXTID 14
#define ETM_OPT_CTXTID2 15
@@ -25,6 +26,7 @@
#define ETM_OPT_RETSTK 29
/* ETMv4 CONFIGR programming bits for the ETM OPTs */
+#define ETM4_CFG_BIT_BB 3
#define ETM4_CFG_BIT_CYCACC 4
#define ETM4_CFG_BIT_CTXTID 6
#define ETM4_CFG_BIT_VMID 7
--
2.28.0