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2382 discussions

Re: [PATCH v1 3/3] perf auxtrace arm: Support compat_auxtrace_mmap__{read_head|write_tail}

by Leo Yan

Hi Russell, On Mon, Aug 23, 2021 at 02:39:18PM +0100, Russell King (Oracle) wrote: > On Mon, Aug 23, 2021 at 09:30:43PM +0800, Leo Yan wrote: > > On Mon, Aug 23, 2021 at 01:23:42PM +0100, James Clark wrote: [...] > > > For x86, it's possible to include tools/include/asm/atomic.h, but that doesn't > > > include arch/arm/include/asm/atomic.h and there are some other #ifdefs that might > > > make it not so easy for Arm. Just wondering if you considered trying to include the > > > existing one? Or decided that it was easier to duplicate it? > > > > Good finding! > > > > With you reminding, I recognized that the atomic operations for > > arm/arm64 should be improved for user space program. So far, perf tool > > simply uses the compiler's atomic implementations (from > > asm-generic/atomic-gcc.h) for arm/arm64; but for a more reliable > > implementation, I think we should improve the user space program with > > architecture's atomic instructions. > > No we should not. Sometimes, what's in the kernel is for the kernel's > use only, and not for userspace's use. That may be because what works > in kernel space does not work in userspace. > > For example, the ARMv6+ atomic operations can be executed in userspace > _provided_ they are only used on memory which has an exclusive monitor. > They can't be used on anything that is not "normal memory". Okay, IIUC, the requirement for "normal memory" and exclusive monitor should also apply on aarch64 for ldrex/strex, Load-Acquire and Store-Release instructions, etc. Otherwise, it's heavily dependent on the exclusive monitors outside the cache coherency domain (but this is out of the scopes for CPU). perf tool is very likely to map memory with "normal memory" but we cannot say it's always true. So I agree there have risk for exporting the aarch32/aarch64 atomic headers to user space. > Prior to > ARMv6, the atomic operations rely on disabling interrupts. That > facility is simply not available to userspace, so these must not be > made available to userspace. > > The same applies to bitops. > > We've been here before in the past, when the kernel headers were not > separated from the user ABI headers, and people would write programs > that included e.g. bitops.h on x86 because they had optimised bitops > code. This made the userspace programs very non-portable - without > re-implementing userspace versions of this stuff in every userspace > program that did this stuff. > > So no, having experienced the effects of this kind of thing in the > past, the kernel should _not_ export architecture specific code in > header files to userspace. > > Also, it should be pointed out that by doing so, you create a licensing > issue. If the code is GPLv2, and you build your program such that it > incorporates GPLv2 code, then if the userspace program is not GPLv2 > compliant, you have a licensing problem, and in effect the program > can be distributed. > > Please do not go down this route. Thanks a lot for the suggestion and quick response. Leo

3 years, 10 months

Query regarding AXI Write Burst Length in ETR driver

by Tanmay Jagdale

Hi All, The AXI write burst length is set to 0xF in TMC_AXICTL register in the TMC ETR driver. Definition in coresight-tmc.h #define TMC_AXICTL_WR_BURST_16 0xF00 Marvell CN10K chip uses Coresight SoC-600 IP. Since write burst length field is implementation defined, the maximum value supported by our chip is 0x7. We could not find a way to figure out the maximum supported value through any of the ETR registers. So can you please recommend a way to choose the value 0x7 without affecting other silicons ? With Regards, Tanmay

3 years, 10 months

[PATCH v3 0/1] perf tools: Warning fixes

by James Clark

Changes since v2: Add Leo's reviewed by tag that I missed James Clark (1): perf cs-etm: Add warnings for missing DSOs tools/perf/util/cs-etm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 2.23.0

3 years, 10 months

[RFC PATCH 0/6] perf tools: Warning fixes

by James Clark

I'm submitting this as an RFC because there are a few changes I'd like to get feedback on. The two changes I wanted to make were the last two for Coresight warnings, but I ended up making some perf-wide changes along the way. For #1 (perf tools: Add WARN_ONCE equivalent for UI warnings) * Does it make sense to add warn once equivalents at all, or should the once be re-done for each usage? * Or should there be some kind of generic 'once' wrapper? For #3 (perf tools: Add disassembly warnings for annotate --stdio) * If the output is interpreted by any other tools, then adding these warnings could be an issue, so maybe this change could be dropped, but no error output at all isn't ideal. For #4 (perf tools: Add flag for tracking warnings of missing DSOs) * In theory I could re-use 'annotate_warned', but it might make sense to rename it in that case, or just leave the new auxtrace_warned and remove any confusion. This set applies to perf/core e73f0f0ee7541 Thanks James James Clark (6): perf tools: Add WARN_ONCE equivalent for UI warnings perf tools: Re-add annotate_warned functionality perf tools: Add disassembly warnings for annotate --stdio perf tools: Add flag for tracking warnings of missing DSOs perf cs-etm: Improve Coresight zero timestamp warning perf cs-etm: Add warnings for missing DSOs tools/perf/ui/browsers/annotate.c | 1 + tools/perf/ui/gtk/annotate.c | 1 + tools/perf/util/annotate.c | 20 +++++++++++++++++-- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 +++++-- tools/perf/util/cs-etm.c | 10 +++++++++- tools/perf/util/debug.h | 14 +++++++++++++ tools/perf/util/dso.h | 1 + 7 files changed, 49 insertions(+), 5 deletions(-) -- 2.28.0

3 years, 10 months

[PATCH 0/6] Support ETE decoding

by James Clark

Decoding ETE already works because it is a superset of ETMv4, but if any new packet types are found then they will be ignored by the decoder. This patchset creates an ETE decoder which can output the new packets and saves a new register that is required. No new packet types are handled by perf yet, as this can be added in the future. This set applies on top of "perf cs-etm: Support TRBE (unformatted decoding)" on perf/core. James Clark (6): perf cs-etm: Refactor initialisation of decoder params. perf cs-etm: Initialise architecture based on TRCIDR1 perf cs-etm: Save TRCDEVARCH register perf cs-etm: Update OpenCSD decoder for ETE perf cs-etm: Create ETE decoder perf cs-etm: Print the decoder name tools/build/feature/test-libopencsd.c | 4 +- tools/perf/arch/arm/util/cs-etm.c | 13 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 151 ++++++++---------- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 8 + tools/perf/util/cs-etm.c | 54 ++++++- tools/perf/util/cs-etm.h | 6 +- 6 files changed, 147 insertions(+), 89 deletions(-) -- 2.28.0

3 years, 10 months

[PATCH v2 0/1] perf tools: Warning fixes

by James Clark

Changes since v1: * Remove first 5 patches as they have been applied to perf/core * Add Leo's kernel symbols suggestion and reviewed by tag * Add reference to debuginfod as suggested by Arnaldo Applies to perf/core f3c33cbd92 James Clark (1): perf cs-etm: Add warnings for missing DSOs tools/perf/util/cs-etm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) -- 2.23.0

3 years, 11 months

Re: [PATCH 14/38] coresight: Replace deprecated CPU-hotplug functions.

by Mathieu Poirier

On Tue, Aug 03, 2021 at 04:15:57PM +0200, Sebastian Andrzej Siewior wrote: > The functions get_online_cpus() and put_online_cpus() have been > deprecated during the CPU hotplug rework. They map directly to > cpus_read_lock() and cpus_read_unlock(). > > Replace deprecated CPU-hotplug functions with the official version. > The behavior remains unchanged. > > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Cc: Mike Leach <mike.leach(a)linaro.org> > Cc: Leo Yan <leo.yan(a)linaro.org> > Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-arm-kernel(a)lists.infradead.org > Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> > --- > drivers/hwtracing/coresight/coresight-cpu-debug.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c > index 9731d3a960735..00de46565bc40 100644 > --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c > +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c > @@ -588,11 +588,11 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id) > > drvdata->base = base; > > - get_online_cpus(); > + cpus_read_lock(); > per_cpu(debug_drvdata, drvdata->cpu) = drvdata; > ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data, > drvdata, 1); > - put_online_cpus(); > + cpus_read_unlock(); > Applied - thanks, Mathieu > if (ret) { > dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu); > -- > 2.32.0 >

3 years, 11 months

Re: [PATCH 06/10] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition

by Suzuki K Poulose

On 30/07/2021 12:26, Anshuman Khandual wrote: > > > On 7/28/21 7:22 PM, Suzuki K Poulose wrote: >> Add the CPU Partnumbers for the new Arm designs. >> >> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >> Cc: Mark Rutland <mark.rutland(a)arm.com> >> Cc: Will Deacon <will(a)kernel.org> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> arch/arm64/include/asm/cputype.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h >> index 6231e1f0abe7..b71bd6c176c2 100644 >> --- a/arch/arm64/include/asm/cputype.h >> +++ b/arch/arm64/include/asm/cputype.h >> @@ -73,6 +73,8 @@ >> #define ARM_CPU_PART_CORTEX_A76 0xD0B >> #define ARM_CPU_PART_NEOVERSE_N1 0xD0C >> #define ARM_CPU_PART_CORTEX_A77 0xD0D >> +#define ARM_CPU_PART_CORTEX_A710 0xD47 >> +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 >> >> #define APM_CPU_PART_POTENZA 0x000 >> >> @@ -112,6 +114,8 @@ >> #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) >> #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) >> #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) >> +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) >> +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) > > Should not the new ones be added after MIDR_CORTEX_A77 below to preserve the order ? > TBH. The order doesn't matter much as they are part numbers for different CPUs, without any dependencies between them. But for the sake of keeping the order, I could fix this. Thanks Suzuki

3 years, 11 months

Re: [PATCH 05/10] coresight: trbe: Allow driver to choose a different alignment

by Suzuki K Poulose

On 30/07/2021 12:02, Anshuman Khandual wrote: > > > On 7/28/21 7:22 PM, Suzuki K Poulose wrote: >> The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1, >> advertised via the TRBIDR_EL1. This is used by the driver to >> align the buffer write head. This patch allows the driver to >> choose a different alignment from that of the hardware, by >> decoupling the alignment tracking. This will be useful for >> working around errata. >> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Mike Leach <mike.leach(a)linaro.org> >> Cc: Leo Yan <leo.yan(a)linaro.org> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++---- >> 1 file changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >> index 9735d514c5e1..9ea28813182b 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -92,7 +92,8 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = { >> /* >> * struct trbe_cpudata: TRBE instance specific data >> * @trbe_flag - TRBE dirty/access flag support >> - * @tbre_align - Actual TRBE alignment required for TRBPTR_EL1. >> + * @trbe_hw_align - Actual TRBE alignment required for TRBPTR_EL1. >> + * @trbe_align - Software alignment used for the TRBPTR_EL1, >> * @cpu - CPU this TRBE belongs to. >> * @mode - Mode of current operation. (perf/disabled) >> * @drvdata - TRBE specific drvdata >> @@ -100,6 +101,7 @@ static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = { >> */ >> struct trbe_cpudata { >> bool trbe_flag; >> + u64 trbe_hw_align; >> u64 trbe_align; >> int cpu; >> enum cs_mode mode; >> @@ -906,7 +908,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha >> { >> struct trbe_cpudata *cpudata = dev_get_drvdata(dev); >> >> - return sprintf(buf, "%llx\n", cpudata->trbe_align); >> + return sprintf(buf, "%llx\n", cpudata->trbe_hw_align); >> } >> static DEVICE_ATTR_RO(align); >> >> @@ -995,11 +997,13 @@ static void arm_trbe_probe_cpu(void *info) >> } >> >> trbe_check_errata(cpudata); >> - cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr); >> - if (cpudata->trbe_align > SZ_2K) { >> + >> + cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr); >> + if (cpudata->trbe_hw_align > SZ_2K) { >> pr_err("Unsupported alignment on cpu %d\n", cpu); >> goto cpu_clear; >> } >> + cpudata->trbe_align = cpudata->trbe_hw_align; > > When it changes, it must be asserted that trbe_align would be a multiple > of trbe_hw_align before existing from arm_trbe_probe_cpu(). We only set it to PAGE_SIZE, which is one of 4K, 16K, 64K all of which are aligned to 2K or any of the smaller alignment supported by TRBE. > >> cpudata->trbe_flag = get_trbe_flag_update(trbidr); >> cpudata->cpu = cpu; >> cpudata->drvdata = drvdata; >> > > Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > Thanks Suzuki

3 years, 11 months

Re: [PATCH v2 05/10] coresight: trbe: Drop duplicate TRUNCATE flags

by Suzuki K Poulose

On 30/07/2021 05:47, Anshuman Khandual wrote: > > > On 7/23/21 6:16 PM, Suzuki K Poulose wrote: >> We mark the buffer as TRUNCATED when there is no space left >> in the buffer. But we do it at different points. >> __trbe_normal_offset() >> and also, at all the callers of the above function via >> compute_trbe_buffer_limit(), when the limit == base (i.e >> offset = 0 as returned by the __trbe_normal_offset()). >> >> So, given that the callers already mark the buffer as TRUNCATED >> drop the caller inside the __trbe_normal_offset(). >> >> This is in preparation to moving the handling of TRUNCATED >> into a central place. >> >> Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> >> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >> Cc: Mike Leach <mike.leach(a)linaro.org> >> Cc: Leo Yan <leo.yan(a)linaro.org> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 7 +------ >> 1 file changed, 1 insertion(+), 6 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >> index 446f080f8320..62e1a08f73ff 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -253,13 +253,9 @@ static unsigned long __trbe_normal_offset(struct perf_output_handle *handle) >> * trbe_base trbe_base + nr_pages >> * >> * Perf aux buffer does not have any space for the driver to write into. >> - * Just communicate trace truncation event to the user space by marking >> - * it with PERF_AUX_FLAG_TRUNCATED. >> */ >> - if (!handle->size) { >> - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); >> + if (!handle->size) >> return 0; >> - } >> >> /* Compute the tail and wakeup indices now that we've aligned head */ >> tail = PERF_IDX2OFF(handle->head + handle->size, buf); >> @@ -361,7 +357,6 @@ static unsigned long __trbe_normal_offset(struct perf_output_handle *handle) >> return limit; >> >> trbe_pad_buf(handle, handle->size); >> - perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); >> return 0; >> } > > What about in trbe_handle_spurious() path which used to set the flag via > compute_trbe_buffer_limit(), but would not any more after this change. I > guess following additional change would be required to preserve the past > behaviour. > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -685,6 +685,7 @@ static void trbe_handle_spurious(struct perf_output_handle *handle) > buf->trbe_write = buf->trbe_base + PERF_IDX2OFF(handle->head, buf); > if (buf->trbe_limit == buf->trbe_base) { > trbe_drain_and_disable_local(); > + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); > return; > } > trbe_enable_hw(buf); > Agreed, I will add this. Thanks Suzuki

3 years, 11 months

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