On 29/09/2023 09:16, Uwe Kleine-König wrote:
> etm4_platform_driver (which lives in ".data" contains a reference to
> etm4_remove_platform_dev(). So the latter must not be marked with __exit
> which results in the function being discarded for a build with
> CONFIG_CORESIGHT_SOURCE_ETM4X=y which in turn makes the remove pointer
> contain invalid data.
>
> etm4x_amba_driver referencing etm4_remove_amba() has the same issue.
>
> Drop the __exit annotations for the two affected functions and a third
> one that is called by the other two.
>
> For reasons I don't understand this isn't catched by building with
> CONFIG_DEBUG_SECTION_MISMATCH=y.
>
> Fixes: c23bc382ef0e ("coresight: etm4x: Refactor probing routine")
> Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices")
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig(a)pengutronix.de>
Thanks for the fix, I can queue them via the coresight tree.
Suzuki
Partially revert the change in commit 6148652807ba ("coresight: Enable
and disable helper devices adjacent to the path") which changed the bare
call from source_ops(csdev)->enable() to coresight_enable_source() for
Perf sessions. It was missed that coresight_enable_source() is
specifically for the sysfs interface, rather than being a generic call.
This interferes with the sysfs reference counting to cause the following
crash:
$ perf record -e cs_etm/@tmc_etr0/ -C 0 &
$ echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
$ echo 1 > /sys/bus/coresight/devices/etm0/enable_source
$ echo 0 > /sys/bus/coresight/devices/etm0/enable_source
Unable to handle kernel NULL pointer dereference at virtual
address 00000000000001d0
Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP
...
Call trace:
etm4_disable+0x54/0x150 [coresight_etm4x]
coresight_disable_source+0x6c/0x98 [coresight]
coresight_disable+0x74/0x1c0 [coresight]
enable_source_store+0x88/0xa0 [coresight]
dev_attr_store+0x20/0x40
sysfs_kf_write+0x4c/0x68
kernfs_fop_write_iter+0x120/0x1b8
vfs_write+0x2dc/0x3b0
ksys_write+0x70/0x108
__arm64_sys_write+0x24/0x38
invoke_syscall+0x50/0x128
el0_svc_common.constprop.0+0x104/0x130
do_el0_svc+0x40/0xb8
el0_svc+0x2c/0xb8
el0t_64_sync_handler+0xc0/0xc8
el0t_64_sync+0x1a4/0x1a8
Code: d53cd042 91002000 b9402a81 b8626800 (f940ead5)
---[ end trace 0000000000000000 ]---
This commit linked below also fixes the issue, but has unlocked updates
to the mode which could potentially race. So until we come up with a
more complete solution that takes all locking and interaction between
both modes into account, just revert back to the old behavior for Perf.
Reported-by: Junhao He <hejunhao3(a)huawei.com>
Closes: https://lore.kernel.org/linux-arm-kernel/20230921132904.60996-1-hejunhao3@h…
Fixes: 6148652807ba ("coresight: Enable and disable helper devices adjacent to the path")
Signed-off-by: James Clark <james.clark(a)arm.com>
---
drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 5ca6278baff4..89e8ed214ea4 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -493,7 +493,7 @@ static void etm_event_start(struct perf_event *event, int flags)
goto fail_end_stop;
/* Finally enable the tracer */
- if (coresight_enable_source(csdev, CS_MODE_PERF, event))
+ if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
goto fail_disable_path;
/*
@@ -587,7 +587,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
return;
/* stop tracer */
- coresight_disable_source(csdev, event);
+ source_ops(csdev)->disable(csdev, event);
/* tell the core */
event->hw.state = PERF_HES_STOPPED;
--
2.34.1
This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
the perf event attribute. But first, this implements an errata work around
affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.
This series applies on coresight/for-next/queue.
Cc: Catalin Marinas <catalin.marinas(a)arm.com>
Cc: Will Deacon <will(a)kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com>
Cc: Mike Leach <mike.leach(a)linaro.org>
Cc: James Clark <james.clark(a)arm.com>
Cc: Leo Yan <leo.yan(a)linaro.org>
Cc: Jonathan Corbet <corbet(a)lwn.net>
Cc: linux-doc(a)vger.kernel.org
Cc: coresight(a)lists.linaro.org
Cc: linux-arm-kernel(a)lists.infradead.org
Cc: linux-kernel(a)vger.kernel.org
Changes in V7:
- Changed commit message for the second patch adding cc_threshold
Changes in V6:
https://lore.kernel.org/all/20230920095443.1126617-1-anshuman.khandual@arm.…
- Renamed etm4_core_reads_wrong_ccitmin() as etm4_fixup_wrong_ccitmin()
- Moved drvdata->ccitmin fixup inside etm4_fixup_wrong_ccitmin()
Changes in V5:
https://lore.kernel.org/all/20230821045216.641499-1-anshuman.khandual@arm.c…https://lore.kernel.org/all/20230915093649.435163-1-anshuman.khandual@arm.c…
- Replaced 'where as' with single word 'whereas'
- Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT
Changes in V4:
https://lore.kernel.org/all/20230818112051.594986-1-anshuman.khandual@arm.c…
- Fixed a typo s/rangess/ranges,
- Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin()
- Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin()
- Moved the comment inside etm4_core_reads_wrong_ccitmin()
Changes in V3:
https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.c…
- Added errata work around affecting TRCIDR3.CCITMIN
- Split the document update into a separate patch
Changes in V2:
https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.c…
- s/treshhold/threshold
Changes in V1:
https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.…
Anshuman Khandual (3):
coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
coresight: etm: Make cycle count threshold user configurable
Documentation: coresight: Add cc_threshold tunable
Documentation/arch/arm64/silicon-errata.rst | 10 ++++
Documentation/trace/coresight/coresight.rst | 4 ++
.../hwtracing/coresight/coresight-etm-perf.c | 2 +
.../coresight/coresight-etm4x-core.c | 46 ++++++++++++++++++-
4 files changed, 60 insertions(+), 2 deletions(-)
--
2.25.1
Introduction of TPDM DSB subunit
DSB subunit is responsible for creating a dataset element, and is also
optionally responsible for packing it to fit multiple elements on a
single ATB transfer if possible in the configuration. The TPDM Core
Datapath requests timestamps be stored by the TPDA and then delivering
ATB sized data (depending on ATB width and element size, this could
be smaller or larger than a dataset element) to the ATB Mast FSM.
The DSB subunit must be configured prior to enablement. This series
adds support for TPDM to configure the configure DSB subunit.
Once this series patches are applied properly, the new tpdm nodes for
should be observed at the tpdm path /sys/bus/coresight/devices/tpdm*
which supports DSB subunit.
e.g.
root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l
drwxr-xr-x 2 root root 0 Jan 1 00:00 connections
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type
drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts
-rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type
-rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source
--w------- 1 root root 4096 Jan 1 00:00 integration_test
drwxr-xr-x 2 root root 0 Jan 1 00:00 power
--w------- 1 root root 4096 Jan 1 00:02 reset_dataset
lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight
-rw-r--r-- 1 root root 4096 Apr 5 2021 uevent
-r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier
We can use the commands are similar to the below to configure the
TPDMs which support DSB subunit. Enable coresight sink first.
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset
echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx
echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask
echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val
echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts
echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type
echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5
echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2
echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
TPDM_DSB commit tree:
https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v10https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v10
Changes in V10:
1. Use checking the number of DSB MSR instead of checking
if DSB MSR is supported in the visiblity function. Thus
only the available MSRs will be listed in the directory.
-- Suzuki K Poulose
2. Rename the attribut group "tpdm_dsb_attrs_grp" to
"tpdm_dsb_attr_grp".
Changes in V9:
1. Adjust the alignment for all the patches in this series.
-- Suzuki K Poulose
2. Initialize the variable "ret" to 0 in the patch#4.
-- Suzuki K Poulose
3. Change the kernel version to 6.7 for all the sysfs files
in the documents for this patch series.
-- Suzuki K Poulose
4. Remove the parameter "max" from the general read/write
functions in the patch#9 and patch#10.
-- Suzuki K Poulose
5. Avoid releasing the lock in two different places in the
patch#10.
-- Suzuki K Poulose
6. Rename "dsb_patt_ts" to "enable_ts", and rename "dsb_patt_type"
to "set_type" in the patch#11. Move these two sysfs files to the
folder "dsb_patt".
-- Suzuki K Poulose
7. Clear the relevant fields first in the function "set_dsb_tier".
-- Suzuki K Poulose
8. Reading/writing the TIER register in the function "set_dsb_tier".
-- Suzuki K Poulose
9. Read the property "qcom,dsb_msr_num" during probe.
-- Suzuki K Poulose
10. Move the variable "dsb_msr_num" to "drvdata".
-- Suzuki K Poulose
11. Move the msr number check to simple tpdm sysfs API.
-- Suzuki K Poulose
12. Remove the needless "msr number" check in the function
"tpdm_reset_datasets"
-- Suzuki K Poulose
Changes in V8:
1. Refine the function "tpda_set_element_size" and rename it
to "tpda_get_element_size" in the patch#4.
-- Suzuki K Poulose
2. Refine the functioin "tpda_enable_port" in the patch#4.
-- Suzuki K Poulose
3. Write a helper to check if the TPDM has DSB dataset in the
patch#5.
-- Suzuki K Poulose
4. Move the function "tpdm_reset_datasets" to "datasets_setup"
to call in the patch#5.
-- Suzuki K Poulose
5. Refine the comment of DSB in "tpdm_drvdata" in the patch#5.
-- Suzuki K Poulose
6. Refine the comments in the documents for this patch series.
-- Suzuki K Poulose
7. Adjust the code alignment in this patch series.
-- Suzuki K Poulose
8. Combine the mode related functions to one in the patch#8.
-- Suzuki K Poulose
9. Refine the R/W functions of "dsb_mode" in the patch#8.
-- Suzuki K Poulose
10. Adjust the macros of mode in the TPDM header file in the
patch#8.
-- Suzuki K Poulose
11. Remove the unused code and fix the warnings in compiling
for the patch#9.
-- kernel test robot
12. Use the following sysfs nodes to read/set edge control
related value in the patch#9.
dsb_edge/
\- ctrl_idx -> Set the index number
\- ctrl_val -> Set the edge control value
\- ctrl_mask -> Set the edge control mask
\- edcr0 ... edcr15 -> Read the edge control value
\- edcmr0 ... edcmr7 -> Read the edge control mask
-- Suzuki K Poulose
13. Use the following sysfs nodes to read/set DSB trigger
pattern value and mask in the patch#10.
dsb_trig_patt/
\- xpr0 ... xpr15 -> (RW) Set/Get the value
\- xpmr0 ... xpmr7 -> (RW) Set/Get the mask
-- Suzuki K Poulose
14. Use the following sysfs nodes to read/set DSB pattern
value and mask in the patch#11.
dsb_patt/
\- tpr0 ... tpr15 -> (RW) Set/Get the value
\- tpmr0 ... tpmr7 -> (RW) Set/Get the mask
-- Suzuki K Poulose
15. Add "Acked-by" tag to the patch#12.
-- Rob Herring
16. Use the following sysfs nodes to read/set DSB MSR in
the patch#13.
dsb_msr/
\- msr0 ... msr31 -> (RW) Set/Get the value
-- Suzuki K Poulose
17. Create the maximal number of DSB MSR sysfs nodes if the
TPDM supports DSB MSR. Write the values set by user space to
the DSB MSR according to the number of MSR supported by the
TPDM.
-- Suzuki K Poulose
Changes in V7:
1. Since the "One value" limitation on SysFs file usage, add
the nodes to read/write the index number for configuring the
DSB TPDM. The following index number nodes are added.
"dsb_edge_ctrl_idx" in the patch #9
"dsb_trig_patt_idx" in the patch #10
"dsb_patt_idx" in the patch #11
"dsb_msr_idx" in the patch #13
-- Suzuki K Poulose
Changes in V6:
1. Align the code to fix the styling issue.
-- Suzuki K Poulose
Changes in V5:
1. Correct data type for DSB element size in dt-bindings patch.
2. Refine the recursive function "tpda_set_element_size".
-- Suzuki K Poulose
3. Get return value of the function "__tpda_enable" in
"tpda_enable".
-- Suzuki K Poulose
4. Refine the comments on "dsb_esize".
-- Suzuki K Poulose
5. Split the chage that introduce the subtype
"SUBTYPE_SOURCE_TPDM" to Coresight driver.
-- Suzuki K Poulose
6. Inline the trigger type setting to "tpdm_enable_dsb" simply.
-- Suzuki K Poulose
7. Split the change that remove the needless CS_{UN,}LOCK in
the function "tpdm_datasets_setup".
-- Suzuki K Poulose
8. Remove the disablement step in the reset node.
-- Suzuki K Poulose
9. Update the kernel version to 6.5 in the sysfs document.
-- Suzuki K Poulose
10. Remove the needless check in "tpdm_dsb_is_visible".
-- Suzuki K Poulose
11. Change the macro to mask the mode of DSB TPDM.
-- Suzuki K Poulose
12. Add a check to make sure "sysfs_emit_at" calling will not
cause overflow.
-- Suzuki K Poulose
13. Change the macro to get "edge_ctrl" value.
-- Suzuki K Poulose
14. Remove the needless comments in the sysfs document.
-- Suzuki K Poulose
15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in
"dsb_msr_show".
-- Suzuki K Poulose
16. Update the check of MSR number in "dsb_msr_store".
-- Suzuki K Poulose
17. Write data to the MSR registers in the DSB TPDM enablement
function.
-- Suzuki K Poulose
Changes in V4:
1. Change the range of the property "qcom,dsb-element-size", and
change the type to enumeration.
-- Suzuki K Poulose, Krzysztof Kozlowski
2. Change dsb_esize from 32 bits to 8 bits.
-- Suzuki K Poulose
3. Update the function tpda_set_element_size since James has
updated the dependency series. Meanwhile, it will send out a
warning if it detects more than one TPDM from the same TPDA
input port.
-- Suzuki K Poulose
4. Add a source_sub_type for TPDM to distinguish TPDM from
the other coresight source.
-- Suzuki K Poulose
5. Return error if the element size is not configured on
devicetree in TPDA enablement.
-- Suzuki K Poulose
6. Move memory allocation from "tpdm_init_datasets" to
"tpdm_datasets_setup". Rename "tpdm_init_datasets" as
"tpdm_reset_datasets".
-- Suzuki K Poulose
7. Replace "coresight_disable" with "coresight_disable_source"
to disable the TPDM in resetting.
-- Suzuki K Poulose
8. Make sure "drvdata" is not NULL pointer before using it.
-- Suzuki K Poulose
9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since
cycle accurate mode is not supported on the current targets.
It is replaced by test mode.
10. Document the value of "dsb_mode".
-- Suzuki K Poulose
11. Macros are used to replace the formulas on dsb edge control
nodes.
-- Suzuki K Poulose
12. Document the values of "dsb_trig_patt_val" and
"dsb_trig_patt_mask".
-- Suzuki K Poulose
13. Combine two pattern related loops to one. And move DSB TIER
register configurations to the new function "set_dsb_tier".
-- Suzuki K Poulose
14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num".
-- Suzuki K Poulose, Krzysztof Kozlowski
Changes in V3:
1. Move the property "qcom,dsb-element-size" to TPDM
devicetree and update the TPDM yaml file for this item.
-- Suzuki K Poulose
2. Add the error message when the DSB element size is not set to
32-bit or 64-bit. -- Suzuki K Poulose
3. Add more information to the comments of patch #3
-- Suzuki K Poulose
4. Combine the value updates to the TPDM_DSB_CR for TPDM.
-- Suzuki K Poulose
5. Remove the function "tpdm_datasets_alloc", and fold its code
to a new function "tpdm_init_datasets". It will complete the
initialization of TPDM. -- Suzuki K Poulose
6. Change the method of qualifying input values.
-- Suzuki K Poulose
7. Add the documentation of the new sysfs handles.
-- Suzuki K Poulose
8. Provide the separate handles for the "mode bits".
-- Suzuki K Poulose
Changes in V2:
1. Change the name of the property "qcom,dsb-elem-size" to
"qcom,dsb-element-size" -- Suzuki K Poulose
2. Update the TPDA yaml file for the item "qcom,dsb-elem-size".
-- Krzysztof Kozlowski
3. Add the full name of DSB in the description of the item
"qcom,dsb-elem-size". -- Rob Herring
Changes in V1:
1. Change the definition of the property "qcom,dsb-elem-size" from
"uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski
2. Add the full name of DSB. -- Rob Herring
3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose
4. Divide the function "tpdm_datasets_alloc" into two functions,
"tpdm_datasets_setup" and "tpdm_datasets_alloc".
5. Detecte the input string with the conventional semantics automatically,
and constrain the size of the input value. -- Suzuki K Poulose
6. Use the hook function "is_visible()" to hide the DSB related knobs if
the data sets are missing. -- Suzuki K Poulose
7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values.
-- Suzuki K Poulose
8. Update the definition of the macros in TPDM driver.
9. Update the comments of the values for the nodes which are for DSB
element creation and onfigure pattern match output. -- Suzuki K Poulose
10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose
Tao Zhang (13):
coresight-tpdm: Remove the unnecessary lock
dt-bindings: arm: Add support for DSB element size
coresight-tpdm: Introduce TPDM subtype to TPDM driver
coresight-tpda: Add DSB dataset support
coresight-tpdm: Initialize DSB subunit configuration
coresight-tpdm: Add reset node to TPDM node
coresight-tpdm: Add nodes to set trigger timestamp and type
coresight-tpdm: Add node to set dsb programming mode
coresight-tpdm: Add nodes for dsb edge control
coresight-tpdm: Add nodes to configure pattern match output
coresight-tpdm: Add nodes for timestamp request
dt-bindings: arm: Add support for DSB MSR register
coresight-tpdm: Add nodes for dsb msr support
.../testing/sysfs-bus-coresight-devices-tpdm | 159 ++++
.../bindings/arm/qcom,coresight-tpdm.yaml | 20 +
drivers/hwtracing/coresight/coresight-core.c | 3 +
drivers/hwtracing/coresight/coresight-tpda.c | 126 ++-
drivers/hwtracing/coresight/coresight-tpda.h | 2 +
drivers/hwtracing/coresight/coresight-tpdm.c | 718 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-tpdm.h | 161 ++++
include/linux/coresight.h | 1 +
8 files changed, 1168 insertions(+), 22 deletions(-)
--
2.17.1
On Thu, Oct 12, 2023 at 10:56:41AM -0700, Ian Rogers wrote:
> Avoid setting PMU values in arm_spe_pmu_default_config, move to
> perf_pmu__arch_init.
>
> Signed-off-by: Ian Rogers <irogers(a)google.com>
> Reviewed-by: Adrian Hunter <adrian.hunter(a)intel.com>
> ---
> tools/perf/arch/arm/util/pmu.c | 2 ++
> tools/perf/arch/arm64/util/arm-spe.c | 3 ---
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c
> index d55d2b15f2e6..f25f68f84a94 100644
> --- a/tools/perf/arch/arm/util/pmu.c
> +++ b/tools/perf/arch/arm/util/pmu.c
> @@ -23,6 +23,8 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused)
> pmu->default_config = cs_etm_get_default_config(pmu);
> #if defined(__aarch64__)
> } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) {
> + pmu->selectable = true;
> + pmu->is_uncore = false;
Arm SPE is not an uncore PMU event. Arm SPE driver registers sysfs node
'cpumask', thus it misleads the pmu_is_uncore() function and it returns
'true' for Arm SPE event.
Here we need to explictly set false to correct the 'is_uncore' flag.
I did test on my machine, the changes work well for Arm SPE event.
Tested-by: Leo Yan <leo.yan(a)linaro.org>
This patch series is to improve timestamp handling in per-thread mode.
The current code doesn't validate timestamp and always return success for
per-thread mode, for a sane implementation, the first patch is to allow
validation timestamp tracing in per-thread mode.
The second patch is to respect timestamp option "--timestamp" or "-T",
when users set this option, the tool will automatically enable hardware
timestamp tracing in Arm CoreSight.
This patch set is rebased on the latest perf-tools-next branch, and
tested on Arm Juno board. And added James Clark's review tags.
Leo Yan (2):
perf cs-etm: Validate timestamp tracing in per-thread mode
perf cs-etm: Respect timestamp option
tools/perf/arch/arm/util/cs-etm.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
--
2.34.1