CoreSight

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Re: [PATCH v5 2/2] coresight: cti: Add Qualcomm extended CTI support

by Mike Leach

Hi, On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. Qualcomm CTI > implementation differs from the standard CTI in the following aspects: > > 1. The number of supported triggers is extended to 128. > 2. Several register offsets differ from the CoreSight specification. > > Signed-off-by: Jinlong Mao <jinglong.mao(a)oss.qualcomm.com> > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 86 +++++++++-- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 174 +++++++++++++++++----- > drivers/hwtracing/coresight/coresight-cti.h | 43 +++++- > drivers/hwtracing/coresight/qcom-cti.h | 29 ++++ > 4 files changed, 281 insertions(+), 51 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8c9cec832898..5330db7eecf1 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -21,6 +21,55 @@ > > #include "coresight-priv.h" > #include "coresight-cti.h" > +#include "qcom-cti.h" > + > +static const u32 cti_normal_offset[] = { > + [INDEX_CTIINTACK] = CTIINTACK, > + [INDEX_CTIAPPSET] = CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = CTIAPPPULSE, > + [INDEX_CTIINEN] = CTIINEN(0), > + [INDEX_CTIOUTEN] = CTIOUTEN(0), > + [INDEX_CTITRIGINSTATUS] = CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = CTICHOUTSTATUS, > + [INDEX_CTIGATE] = CTIGATE, > + [INDEX_ASICCTL] = ASICCTL, > + [INDEX_ITCHINACK] = ITCHINACK, > + [INDEX_ITTRIGINACK] = ITTRIGINACK, > + [INDEX_ITCHOUT] = ITCHOUT, > + [INDEX_ITTRIGOUT] = ITTRIGOUT, > + [INDEX_ITCHOUTACK] = ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = ITTRIGOUTACK, > + [INDEX_ITCHIN] = ITCHIN, > + [INDEX_ITTRIGIN] = ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > + > +static const u32 cti_extended_offset[] = { > + [INDEX_CTIINTACK] = QCOM_CTIINTACK, > + [INDEX_CTIAPPSET] = QCOM_CTIAPPSET, > + [INDEX_CTIAPPCLEAR] = QCOM_CTIAPPCLEAR, > + [INDEX_CTIAPPPULSE] = QCOM_CTIAPPPULSE, > + [INDEX_CTIINEN] = QCOM_CTIINEN, > + [INDEX_CTIOUTEN] = QCOM_CTIOUTEN, > + [INDEX_CTITRIGINSTATUS] = QCOM_CTITRIGINSTATUS, > + [INDEX_CTITRIGOUTSTATUS] = QCOM_CTITRIGOUTSTATUS, > + [INDEX_CTICHINSTATUS] = QCOM_CTICHINSTATUS, > + [INDEX_CTICHOUTSTATUS] = QCOM_CTICHOUTSTATUS, > + [INDEX_CTIGATE] = QCOM_CTIGATE, > + [INDEX_ASICCTL] = QCOM_ASICCTL, > + [INDEX_ITCHINACK] = QCOM_ITCHINACK, > + [INDEX_ITTRIGINACK] = QCOM_ITTRIGINACK, > + [INDEX_ITCHOUT] = QCOM_ITCHOUT, > + [INDEX_ITTRIGOUT] = QCOM_ITTRIGOUT, > + [INDEX_ITCHOUTACK] = QCOM_ITCHOUTACK, > + [INDEX_ITTRIGOUTACK] = QCOM_ITTRIGOUTACK, > + [INDEX_ITCHIN] = QCOM_ITCHIN, > + [INDEX_ITTRIGIN] = QCOM_ITTRIGIN, > + [INDEX_ITCTRL] = CORESIGHT_ITCTRL, > +}; > > /* > * CTI devices can be associated with a PE, or be connected to CoreSight > @@ -70,15 +119,16 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) > > /* write the CTI trigger registers */ > for (i = 0; i < config->nr_trig_max; i++) { > - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); > + writel_relaxed(config->ctiinen[i], > + drvdata->base + cti_offset(drvdata, INDEX_CTIINEN, i)); > writel_relaxed(config->ctiouten[i], > - drvdata->base + CTIOUTEN(i)); > + drvdata->base + cti_offset(drvdata, INDEX_CTIOUTEN, i)); > } > > /* other regs */ > - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); > - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); > - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); > + writel_relaxed(config->ctigate, drvdata->base + cti_offset(drvdata, INDEX_CTIGATE, 0)); > + writel_relaxed(config->asicctl, drvdata->base + cti_offset(drvdata, INDEX_ASICCTL, 0)); > + writel_relaxed(config->ctiappset, drvdata->base + cti_offset(drvdata, INDEX_CTIAPPSET, 0)); > > /* re-enable CTI */ > writel_relaxed(1, drvdata->base + CTICONTROL); > @@ -214,6 +264,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -394,8 +447,8 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > > /* update the local register values */ > chan_bitmask = BIT(channel_idx); > - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : > - CTIOUTEN(trigger_idx)); > + reg_offset = (direction == CTI_TRIG_IN ? cti_offset(drvdata, INDEX_CTIINEN, trigger_idx) : > + cti_offset(drvdata, INDEX_CTIOUTEN, trigger_idx)); > > raw_spin_lock(&drvdata->spinlock); > > @@ -479,19 +532,19 @@ int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, > case CTI_CHAN_SET: > config->ctiappset |= chan_bitmask; > reg_value = config->ctiappset; > - reg_offset = CTIAPPSET; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPSET, 0); > break; > > case CTI_CHAN_CLR: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPCLEAR; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPCLEAR, 0); > break; > > case CTI_CHAN_PULSE: > config->ctiappset &= ~chan_bitmask; > reg_value = chan_bitmask; > - reg_offset = CTIAPPPULSE; > + reg_offset = cti_offset(drvdata, INDEX_CTIAPPPULSE, 0); > break; > > default: > @@ -894,6 +947,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -980,9 +1034,19 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > drvdata->csdev_release = drvdata->csdev->dev.release; > drvdata->csdev->dev.release = cti_device_release; > > + /* qcom_cti*/ perhaps this comment could be "check architect value"? > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > + drvdata->subtype = QCOM_CTI; > + drvdata->offsets = cti_extended_offset; > + } else { > + drvdata->subtype = ARM_STD_CTI; > + drvdata->offsets = cti_normal_offset; > + } > + > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, "CTI initialized %d\n", drvdata->subtype); Here extend string to "CTI Intialized; subtype=%d\n" > return 0; > > pm_release: > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index a9df77215141..88fd1c9c0101 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -172,9 +172,8 @@ static struct attribute *coresight_cti_attrs[] = { > > /* register based attributes */ > > -/* Read registers with power check only (no enable check). */ > -static ssize_t coresight_cti_reg_show(struct device *dev, > - struct device_attribute *attr, char *buf) > +static ssize_t coresight_cti_mgmt_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > @@ -189,6 +188,39 @@ static ssize_t coresight_cti_reg_show(struct device *dev, > return sysfs_emit(buf, "0x%x\n", val); > } > > +/* Read registers with power check only (no enable check). */ > +static ssize_t coresight_cti_reg_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > + u32 val = 0, idx = drvdata->config.regs_idx; This needs to be inside the spin lock > + > + pm_runtime_get_sync(dev->parent); > + raw_spin_lock(&drvdata->spinlock); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_CTITRIGINSTATUS: > + case INDEX_CTITRIGOUTSTATUS: > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + case INDEX_ITTRIGOUTACK: > + case INDEX_ITTRIGIN: > + val = readl_relaxed(drvdata->base + > + cti_offset(drvdata, cti_attr->off, idx)); > + break; > + > + default: > + val = readl_relaxed(drvdata->base + cti_offset(drvdata, cti_attr->off, 0)); > + break; > + } > + } > + > + raw_spin_unlock(&drvdata->spinlock); > + pm_runtime_put_sync(dev->parent); > + return sysfs_emit(buf, "0x%x\n", val); > +} > + > /* Write registers with power check only (no enable check). */ > static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct device_attribute *attr, > @@ -197,19 +229,38 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > unsigned long val = 0; > + u32 idx = drvdata->config.regs_idx; > this needs to be inside the spinlock > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > > pm_runtime_get_sync(dev->parent); > raw_spin_lock(&drvdata->spinlock); > - if (drvdata->config.hw_powered) > - cti_write_single_reg(drvdata, cti_attr->off, val); > + if (drvdata->config.hw_powered) { > + switch (cti_attr->off) { > + case INDEX_ITTRIGINACK: > + case INDEX_ITTRIGOUT: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, idx), val); > + break; > + > + default: > + cti_write_single_reg(drvdata, cti_offset(drvdata, cti_attr->off, 0), val); > + break; > + } > + } > raw_spin_unlock(&drvdata->spinlock); > pm_runtime_put_sync(dev->parent); > return size; > } > > +#define coresight_cti_mgmt_reg(name, offset) \ > + (&((struct cs_off_attribute[]) { \ > + { \ > + __ATTR(name, 0444, coresight_cti_mgmt_reg_show, NULL), \ > + offset \ > + } \ > + })[0].attr.attr) > + > #define coresight_cti_reg(name, offset) \ > (&((struct cs_off_attribute[]) { \ > { \ > @@ -237,17 +288,17 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > > /* coresight management registers */ > static struct attribute *coresight_cti_mgmt_attrs[] = { > - coresight_cti_reg(devaff0, CTIDEVAFF0), > - coresight_cti_reg(devaff1, CTIDEVAFF1), > - coresight_cti_reg(authstatus, CORESIGHT_AUTHSTATUS), > - coresight_cti_reg(devarch, CORESIGHT_DEVARCH), > - coresight_cti_reg(devid, CORESIGHT_DEVID), > - coresight_cti_reg(devtype, CORESIGHT_DEVTYPE), > - coresight_cti_reg(pidr0, CORESIGHT_PERIPHIDR0), > - coresight_cti_reg(pidr1, CORESIGHT_PERIPHIDR1), > - coresight_cti_reg(pidr2, CORESIGHT_PERIPHIDR2), > - coresight_cti_reg(pidr3, CORESIGHT_PERIPHIDR3), > - coresight_cti_reg(pidr4, CORESIGHT_PERIPHIDR4), > + coresight_cti_mgmt_reg(devaff0, CTIDEVAFF0), > + coresight_cti_mgmt_reg(devaff1, CTIDEVAFF1), > + coresight_cti_mgmt_reg(authstatus, CORESIGHT_AUTHSTATUS), > + coresight_cti_mgmt_reg(devarch, CORESIGHT_DEVARCH), > + coresight_cti_mgmt_reg(devid, CORESIGHT_DEVID), > + coresight_cti_mgmt_reg(devtype, CORESIGHT_DEVTYPE), > + coresight_cti_mgmt_reg(pidr0, CORESIGHT_PERIPHIDR0), > + coresight_cti_mgmt_reg(pidr1, CORESIGHT_PERIPHIDR1), > + coresight_cti_mgmt_reg(pidr2, CORESIGHT_PERIPHIDR2), > + coresight_cti_mgmt_reg(pidr3, CORESIGHT_PERIPHIDR3), > + coresight_cti_mgmt_reg(pidr4, CORESIGHT_PERIPHIDR4), > NULL, > }; > > @@ -258,13 +309,15 @@ static struct attribute *coresight_cti_mgmt_attrs[] = { > * If inaccessible & pcached_val not NULL then show cached value. > */ > static ssize_t cti_reg32_show(struct device *dev, char *buf, > - u32 *pcached_val, int reg_offset) > + u32 *pcached_val, int index) > { > u32 val = 0; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > raw_spin_lock(&drvdata->spinlock); > + reg_offset = cti_offset(drvdata, index, 0); > if ((reg_offset >= 0) && cti_active(config)) { > CS_UNLOCK(drvdata->base); > val = readl_relaxed(drvdata->base + reg_offset); > @@ -284,11 +337,12 @@ static ssize_t cti_reg32_show(struct device *dev, char *buf, > * if reg_offset >= 0 then write through if enabled. > */ > static ssize_t cti_reg32_store(struct device *dev, const char *buf, > - size_t size, u32 *pcached_val, int reg_offset) > + size_t size, u32 *pcached_val, int index) > { > unsigned long val; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > + int reg_offset; > > if (kstrtoul(buf, 0, &val)) > return -EINVAL; > @@ -298,6 +352,7 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > if (pcached_val) > *pcached_val = (u32)val; > > + reg_offset = cti_offset(drvdata, index, 0); > /* write through if offset and enabled */ > if ((reg_offset >= 0) && cti_active(config)) > cti_write_single_reg(drvdata, reg_offset, val); > @@ -306,14 +361,14 @@ static ssize_t cti_reg32_store(struct device *dev, const char *buf, > } > > /* Standard macro for simple rw cti config registers */ > -#define cti_config_reg32_rw(name, cfgname, offset) \ > +#define cti_config_reg32_rw(name, cfgname, index) \ > static ssize_t name##_show(struct device *dev, \ > struct device_attribute *attr, \ > char *buf) \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_show(dev, buf, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > \ > static ssize_t name##_store(struct device *dev, \ > @@ -322,7 +377,7 @@ static ssize_t name##_store(struct device *dev, \ > { \ > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \ > return cti_reg32_store(dev, buf, size, \ > - &drvdata->config.cfgname, offset); \ > + &drvdata->config.cfgname, index); \ > } \ > static DEVICE_ATTR_RW(name) > > @@ -356,6 +411,46 @@ static ssize_t inout_sel_store(struct device *dev, > } > static DEVICE_ATTR_RW(inout_sel); > > +/* > + * QCOM CTI supports up to 128 triggers, there are 6 registers need to be > + * expanded to up to 4 instances, and regs_idx can be used to indicate which > + * one is in use. > + * CTITRIGINSTATUS, CTITRIGOUTSTATUS, > + * ITTRIGIN, ITTRIGOUT, > + * ITTRIGINACK, ITTRIGOUTACK. All the other selection indexes are of the form xxx_sel - this should be something along the lines of "ext_reg_sel" for consistency Additionally this information needs to appear as an entry in the documentation file Documentation/ABI/testing/sysfs-bus-coresight-devices-cti so users are aware of which registers this select relates to. > + */ > +static ssize_t regs_idx_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + u32 val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + raw_spin_lock(&drvdata->spinlock); > + val = drvdata->config.regs_idx; > + raw_spin_unlock(&drvdata->spinlock); > + return sprintf(buf, "%d\n", val); > +} > + > +static ssize_t regs_idx_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + unsigned long val; > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > + > + if (kstrtoul(buf, 0, &val)) > + return -EINVAL; > + if (val > ((drvdata->config.nr_trig_max + 31) / 32 - 1)) > + return -EINVAL; > + > + raw_spin_lock(&drvdata->spinlock); > + drvdata->config.regs_idx = val; > + raw_spin_unlock(&drvdata->spinlock); > + return size; > +} > +static DEVICE_ATTR_RW(regs_idx); see above - cheange to ..._sel > + > static ssize_t inen_show(struct device *dev, > struct device_attribute *attr, > char *buf) > @@ -389,7 +484,7 @@ static ssize_t inen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIINEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIINEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -428,7 +523,7 @@ static ssize_t outen_store(struct device *dev, > > /* write through if enabled */ > if (cti_active(config)) > - cti_write_single_reg(drvdata, CTIOUTEN(index), val); > + cti_write_single_reg(drvdata, cti_offset(drvdata, INDEX_CTIOUTEN, index), val); > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -448,9 +543,9 @@ static ssize_t intack_store(struct device *dev, > } > static DEVICE_ATTR_WO(intack); > > -cti_config_reg32_rw(gate, ctigate, CTIGATE); > -cti_config_reg32_rw(asicctl, asicctl, ASICCTL); > -cti_config_reg32_rw(appset, ctiappset, CTIAPPSET); > +cti_config_reg32_rw(gate, ctigate, INDEX_CTIGATE); > +cti_config_reg32_rw(asicctl, asicctl, INDEX_ASICCTL); > +cti_config_reg32_rw(appset, ctiappset, INDEX_CTIAPPSET); > > static ssize_t appclear_store(struct device *dev, > struct device_attribute *attr, > @@ -504,6 +599,7 @@ static DEVICE_ATTR_WO(apppulse); > */ > static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_inout_sel.attr, > + &dev_attr_regs_idx.attr, > &dev_attr_inen.attr, > &dev_attr_outen.attr, > &dev_attr_gate.attr, > @@ -512,20 +608,20 @@ static struct attribute *coresight_cti_regs_attrs[] = { > &dev_attr_appset.attr, > &dev_attr_appclear.attr, > &dev_attr_apppulse.attr, > - coresight_cti_reg(triginstatus, CTITRIGINSTATUS), > - coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), > - coresight_cti_reg(chinstatus, CTICHINSTATUS), > - coresight_cti_reg(choutstatus, CTICHOUTSTATUS), > + coresight_cti_reg(triginstatus, INDEX_CTITRIGINSTATUS), > + coresight_cti_reg(trigoutstatus, INDEX_CTITRIGOUTSTATUS), > + coresight_cti_reg(chinstatus, INDEX_CTICHINSTATUS), > + coresight_cti_reg(choutstatus, INDEX_CTICHOUTSTATUS), > #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS > - coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), > - coresight_cti_reg(ittrigin, ITTRIGIN), > - coresight_cti_reg(itchin, ITCHIN), > - coresight_cti_reg_rw(ittrigout, ITTRIGOUT), > - coresight_cti_reg_rw(itchout, ITCHOUT), > - coresight_cti_reg(itchoutack, ITCHOUTACK), > - coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), > - coresight_cti_reg_wo(ittriginack, ITTRIGINACK), > - coresight_cti_reg_wo(itchinack, ITCHINACK), > + coresight_cti_reg_rw(itctrl, INDEX_ITCTRL), > + coresight_cti_reg(ittrigin, INDEX_ITTRIGIN), > + coresight_cti_reg(itchin, INDEX_ITCHIN), > + coresight_cti_reg_rw(ittrigout, INDEX_ITTRIGOUT), > + coresight_cti_reg_rw(itchout, INDEX_ITCHOUT), > + coresight_cti_reg(itchoutack, INDEX_ITCHOUTACK), > + coresight_cti_reg(ittrigoutack, INDEX_ITTRIGOUTACK), > + coresight_cti_reg_wo(ittriginack, INDEX_ITTRIGINACK), > + coresight_cti_reg_wo(itchinack, INDEX_ITCHINACK), > #endif > NULL, > }; > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 0bd71407ef34..034d6fd1590b 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -57,7 +57,38 @@ struct fwnode_handle; > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > + > +/* Qcom CTI supports up to 128 triggers*/ > +enum cti_subtype { > + ARM_STD_CTI, > + QCOM_CTI, > +}; > + > +/* These registers are remapped in Qcom CTI*/ > +enum cti_offset_index { > + INDEX_CTIINTACK, > + INDEX_CTIAPPSET, > + INDEX_CTIAPPCLEAR, > + INDEX_CTIAPPPULSE, > + INDEX_CTIINEN, > + INDEX_CTIOUTEN, > + INDEX_CTITRIGINSTATUS, > + INDEX_CTITRIGOUTSTATUS, > + INDEX_CTICHINSTATUS, > + INDEX_CTICHOUTSTATUS, > + INDEX_CTIGATE, > + INDEX_ASICCTL, > + INDEX_ITCHINACK, > + INDEX_ITTRIGINACK, > + INDEX_ITCHOUT, > + INDEX_ITTRIGOUT, > + INDEX_ITCHOUTACK, > + INDEX_ITTRIGOUTACK, > + INDEX_ITCHIN, > + INDEX_ITTRIGIN, > + INDEX_ITCTRL, > +}; > > /** > * Group of related trigger signals > @@ -149,6 +180,9 @@ struct cti_config { > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > + /* qcom_cti regs' index */ > + u8 regs_idx; rename to ..._sel as per comments above. This value also needs to be reset in the chan_xtrigs_reset_store() function in coresight-cti-sysfs.c > + > /* cti cross trig programmable regs */ > u8 ctiinout_sel; > u32 ctiappset; > @@ -181,6 +215,8 @@ struct cti_drvdata { > struct cti_config config; > struct list_head node; > void (*csdev_release)(struct device *dev); > + enum cti_subtype subtype; > + const u32 *offsets; > }; > > /* > @@ -234,6 +270,11 @@ struct coresight_platform_data * > coresight_cti_get_platform_data(struct device *dev); > const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); > > +static inline u32 cti_offset(struct cti_drvdata *drvdata, int index, int num) > +{ > + return drvdata->offsets[index] + 4 * num; > +} > + > /* cti powered and enabled */ > static inline bool cti_active(struct cti_config *cfg) > { > diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h > new file mode 100644 > index 000000000000..eaa551ff118a > --- /dev/null > +++ b/drivers/hwtracing/coresight/qcom-cti.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0-only > + * > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#define ARCHITECT_QCOM 0x477 > + This value which is an 11 bit value, in bits 31:21 of the DEVARCH register, is co-incidentally the same as the top 12 bits 31:20 of the ARM DEVARCH register for standard ARM component. Bit 20 of DEVARCH is 1'b1 for present - the 11 bits 31:21 make the archiitect value. ARMs assigned JEDEC architect value 11h'23B which when shifted left by one and ORed with bit 20 gives a value of 12h'477 for bits 31:20. Assuming that your 11 bit JEDEC architect value is 0x477 then the top 12 bits of the qcom devarch register must be 12h'8EF I'd like to be sure that no errors have been made, please confim that bits 31:20 in your DEVARCH register are 0x8EF, and this patch has been tested as working on your system. Thanks and Regards Mike > +/* CTI programming registers */ > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08c > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > > -- > 2.43.0 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

1 month, 2 weeks

Re: [PATCH v5 1/2] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays

by Mike Leach

Hi, On Mon, 20 Oct 2025 at 08:12, Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> wrote: > > Replace the fixed-size u32 fields in the cti_config and cti_trig_grp > structure with dynamically allocated bitmaps and arrays. This allows > memory to be allocated based on the actual number of triggers during probe > time, reducing memory footprint and improving scalability for platforms > with varying trigger counts. > Additionally, repack struct cti_config to reduce its size from 80 bytes to > 72 bytes. > > Signed-off-by: Yingchao Deng <yingchao.deng(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 58 ++++++++++++++++------ > .../hwtracing/coresight/coresight-cti-platform.c | 16 +++--- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 10 ++-- > drivers/hwtracing/coresight/coresight-cti.h | 17 ++++--- > 4 files changed, 65 insertions(+), 36 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index 8fb30dd73fd2..8c9cec832898 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -214,8 +214,8 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > -static void cti_set_default_config(struct device *dev, > - struct cti_drvdata *drvdata) > +static int cti_set_default_config(struct device *dev, > + struct cti_drvdata *drvdata) > { > struct cti_config *config = &drvdata->config; > u32 devid; > @@ -234,12 +234,33 @@ static void cti_set_default_config(struct device *dev, > config->nr_trig_max = CTIINOUTEN_MAX; > } > > + config->trig_in_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_in_use) > + return -ENOMEM; > + > + config->trig_out_use = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_out_use) > + return -ENOMEM; > + > + config->trig_out_filter = devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_KERNEL); > + if (!config->trig_out_filter) > + return -ENOMEM; > + > + config->ctiinen = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); > + if (!config->ctiinen) > + return -ENOMEM; > + > + config->ctiouten = devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), GFP_KERNEL); > + if (!config->ctiouten) > + return -ENOMEM; > + > config->nr_ctm_channels = CTI_DEVID_CTMCHANNELS(devid); > > /* Most regs default to 0 as zalloc'ed except...*/ > config->trig_filter_enable = true; > config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0); > config->enable_req_count = 0; > + return 0; > } > > /* > @@ -270,8 +291,10 @@ int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, > cti_dev->nr_trig_con++; > > /* add connection usage bit info to overall info */ > - drvdata->config.trig_in_use |= tc->con_in->used_mask; > - drvdata->config.trig_out_use |= tc->con_out->used_mask; > + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, > + tc->con_in->used_mask, drvdata->config.nr_trig_max); > + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, > + tc->con_out->used_mask, drvdata->config.nr_trig_max); > > return 0; > } > @@ -293,12 +316,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, > if (!in) > return NULL; > > + in->used_mask = devm_bitmap_alloc(dev, in_sigs, GFP_KERNEL); > + if (!in->used_mask) > + return NULL; > + > out = devm_kzalloc(dev, > offsetof(struct cti_trig_grp, sig_types[out_sigs]), > GFP_KERNEL); > if (!out) > return NULL; > > + out->used_mask = devm_bitmap_alloc(dev, out_sigs, GFP_KERNEL); > + if (!out->used_mask) > + return NULL; > + > tc->con_in = in; > tc->con_out = out; > tc->con_in->nr_sigs = in_sigs; > @@ -314,7 +345,6 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > { > int ret = 0; > int n_trigs = drvdata->config.nr_trig_max; > - u32 n_trig_mask = GENMASK(n_trigs - 1, 0); > struct cti_trig_con *tc = NULL; > > /* > @@ -325,8 +355,9 @@ int cti_add_default_connection(struct device *dev, struct cti_drvdata *drvdata) > if (!tc) > return -ENOMEM; > > - tc->con_in->used_mask = n_trig_mask; > - tc->con_out->used_mask = n_trig_mask; > + bitmap_fill(tc->con_in->used_mask, n_trigs); > + bitmap_fill(tc->con_out->used_mask, n_trigs); > + > ret = cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); > return ret; > } > @@ -339,7 +370,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *config = &drvdata->config; > - u32 trig_bitmask; > u32 chan_bitmask; > u32 reg_value; > int reg_offset; > @@ -349,18 +379,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, > (trigger_idx >= config->nr_trig_max)) > return -EINVAL; > > - trig_bitmask = BIT(trigger_idx); > - > /* ensure registered triggers and not out filtered */ > if (direction == CTI_TRIG_IN) { > - if (!(trig_bitmask & config->trig_in_use)) > + if (!(test_bit(trigger_idx, config->trig_in_use))) > return -EINVAL; > } else { > - if (!(trig_bitmask & config->trig_out_use)) > + if (!(test_bit(trigger_idx, config->trig_out_use))) > return -EINVAL; > > if ((config->trig_filter_enable) && > - (config->trig_out_filter & trig_bitmask)) > + test_bit(trigger_idx, config->trig_out_filter)) > return -EINVAL; > } > > @@ -891,7 +919,9 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > raw_spin_lock_init(&drvdata->spinlock); > > /* initialise CTI driver config values */ > - cti_set_default_config(dev, drvdata); > + ret = cti_set_default_config(dev, drvdata); > + if (ret) > + return ret; > > pdata = coresight_cti_get_platform_data(dev); > if (IS_ERR(pdata)) { > diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c > index d0ae10bf6128..4bef860a0484 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-platform.c > +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c > @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct device *dev, > goto create_v8_etm_out; > > /* build connection data */ > - tc->con_in->used_mask = 0xF0; /* sigs <4,5,6,7> */ > - tc->con_out->used_mask = 0xF0; /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ > + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ > > /* > * The EXTOUT type signals from the ETM are connected to a set of input > @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* Set the v8 PE CTI connection data */ > - tc->con_in->used_mask = 0x3; /* sigs <0 1> */ > + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ > tc->con_in->sig_types[0] = PE_DBGTRIGGER; > tc->con_in->sig_types[1] = PE_PMUIRQ; > - tc->con_out->used_mask = 0x7; /* sigs <0 1 2 > */ > + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ > tc->con_out->sig_types[0] = PE_EDBGREQ; > tc->con_out->sig_types[1] = PE_DBGRESTART; > tc->con_out->sig_types[2] = PE_CTIIRQ; > @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device *dev, > goto of_create_v8_out; > > /* filter pe_edbgreq - PE trigout sig <0> */ > - drvdata->config.trig_out_filter |= 0x1; > + set_bit(0, drvdata->config.trig_out_filter); > > of_create_v8_out: > return ret; > @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp *tgrp, > if (!err) { > /* set the signal usage mask */ > for (idx = 0; idx < tgrp->nr_sigs; idx++) > - tgrp->used_mask |= BIT(values[idx]); > + set_bit(values[idx], tgrp->used_mask); > } > > kfree(values); > @@ -331,7 +331,9 @@ static int cti_plat_process_filter_sigs(struct cti_drvdata *drvdata, > > err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); > if (!err) > - drvdata->config.trig_out_filter |= tg->used_mask; > + bitmap_or(drvdata->config.trig_out_filter, > + drvdata->config.trig_out_filter, > + tg->used_mask, drvdata->config.nr_trig_max); > > kfree(tg); > return err; > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 572b80ee96fb..a9df77215141 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -711,10 +711,8 @@ static ssize_t trigout_filtered_show(struct device *dev, > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > int size = 0, nr_trig_max = cfg->nr_trig_max; > - unsigned long mask = cfg->trig_out_filter; > > - if (mask) > - size = bitmap_print_to_pagebuf(true, buf, &mask, nr_trig_max); > + size = bitmap_print_to_pagebuf(true, buf, cfg->trig_out_filter, nr_trig_max); > return size; > } > static DEVICE_ATTR_RO(trigout_filtered); > @@ -926,9 +924,8 @@ static ssize_t trigin_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_in->used_mask; > > - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); > + return bitmap_print_to_pagebuf(true, buf, con->con_in->used_mask, cfg->nr_trig_max); > } > > static ssize_t trigout_sig_show(struct device *dev, > @@ -940,9 +937,8 @@ static ssize_t trigout_sig_show(struct device *dev, > struct cti_trig_con *con = (struct cti_trig_con *)ext_attr->var; > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cti_config *cfg = &drvdata->config; > - unsigned long mask = con->con_out->used_mask; > > - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); > + return bitmap_print_to_pagebuf(true, buf, con->con_out->used_mask, cfg->nr_trig_max); > } > > /* convert a sig type id to a name */ > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index 8362a47c939c..0bd71407ef34 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -68,7 +68,7 @@ struct fwnode_handle; > */ > struct cti_trig_grp { > int nr_sigs; > - u32 used_mask; > + unsigned long *used_mask; > int sig_types[]; > }; > > @@ -146,20 +146,21 @@ struct cti_config { > bool hw_enabled; > bool hw_powered; > > - /* registered triggers and filtering */ > - u32 trig_in_use; > - u32 trig_out_use; > - u32 trig_out_filter; > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > /* cti cross trig programmable regs */ > - u32 ctiappset; > u8 ctiinout_sel; > - u32 ctiinen[CTIINOUTEN_MAX]; > - u32 ctiouten[CTIINOUTEN_MAX]; > + u32 ctiappset; > u32 ctigate; > u32 asicctl; > + u32 *ctiinen; > + u32 *ctiouten; > + > + /* registered triggers and filtering */ > + unsigned long *trig_in_use; > + unsigned long *trig_out_use; > + unsigned long *trig_out_filter; > }; > > /** > > -- > 2.43.0 > This all looks good to me. Thanks Reviewed-by: Mike Leach <mike.leach(a)linaro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

1 month, 2 weeks

Re: [PATCH 01/12] dt-bindings: arm: coresight: Add cpu cluster tmc/funnel/replicator support

by Mike Leach

Hi, On Tue, 28 Oct 2025 at 09:09, Krzysztof Kozlowski <krzk(a)kernel.org> wrote: > > On Mon, Oct 27, 2025 at 11:28:03PM -0700, Yuanfang Zhang wrote: > > Add the following compatible strings to the bindings: > > - arm,coresight-cpu-funnel > > - arm,coresight-cpu-replicator > > - arm,coresight-cpu-tmc > These are redundant - the actual hardware has not changed - what has is how the device is powered up / down on the system > We see that from the diff. Explain here the hardware instead. > > > > > Each requires 'power-domains' when used. So why is this not used to adjust the power handling in the driver? Or another attribute. Look at the CTI bindings - these can be associated with a CPU or be a system CTI - we look at the cpu attribute to differentiate, not have two separate compatibles. Regards Mike > > > > Signed-off-by: Yuanfang Zhang <yuanfang.zhang(a)oss.qualcomm.com> > > --- > > .../bindings/arm/arm,coresight-dynamic-funnel.yaml | 23 +++++++++++++++++----- > > .../arm/arm,coresight-dynamic-replicator.yaml | 22 +++++++++++++++++---- > > .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 22 +++++++++++++++++---- > > 3 files changed, 54 insertions(+), 13 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > index b74db15e5f8af2226b817f6af5f533b1bfc74736..8f32d4e3bbb750f5a6262db0032318875739cf81 100644 > > --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml > > @@ -28,19 +28,32 @@ select: > > properties: > > compatible: > > contains: > > - const: arm,coresight-dynamic-funnel > > + enum: > > + - arm,coresight-dynamic-funnel > > + - arm,coresight-cpu-funnel > > Keep alphabetical sorting. We asked this multiple times already. > > > required: > > - compatible > > > > allOf: > > - $ref: /schemas/arm/primecell.yaml# > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: arm,coresight-cpu-funnel > > + then: > > + required: > > + - power-domains > > Just move the allOf to the bottom like in example-schema. > > > + > > properties: > > compatible: > > - items: > > - - const: arm,coresight-dynamic-funnel > > - - const: arm,primecell > > - > > Why do you remove this? > > > + oneOf: > > + - items: > > + - const: arm,coresight-dynamic-funnel > > + - const: arm,primecell > > + - items: > > + - const: arm,coresight-cpu-funnel > > Hm? Why do you need custom select if this is not primecell? And nothing > in commit msg explains why this is not primecell anymore. > > You have entire commit msg to say something useful, WHY you are doing > this, WHY you are doing it DIFFERENTLY. Don't say what you did - that's > obvious, we are capable of reading diffs. > > Best regards, > Krzysztof > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

1 month, 2 weeks

[PATCH v3 00/31] CoreSight: Address CPU Power Management Issues

by Leo Yan

This series addresses CPU power management issues in the CoreSight drivers. For easier review, the patches are organized into two categories: o Patches 01 ~ 10 focus on CPU power management within the ETM drivers. These patches fix SMP-safe access to the mode, correct context synchronization, and refactor the CPU suspend/resume flows. o Patches 11 ~ 31 extend CPU power management to cover activated paths, including helpers, links, and sinks. These changes move CPU PM and hotplug notifiers from the ETMv4 driver into the CoreSight core layer. Summary: - Patches 01 ~ 03: Fix device mode access in the SMP mode. - Patch 04 : A minor fix for polling bit. - Patches 05 ~ 07: Improve the context synchronization based on the ETM specification (IHI0064H.b) and Arm ARM (ARM DDI 0487 L.a). - Patches 08 ~ 10: Refactor the context save/restore flow in the ETMv4 driver, in the end, the CPU PM callbacks reuse the normal enabling and disabling flows. - Patches 11 ~ 17: Move CPU PM code from ETMv4 driver to the core layer. - Patches 18 ~ 23: Enhance the CTI driver for preparation dynamically controlling CTI devices in PM flows. This includes device mode handling in the CTI driver and distinguishing trace modes (Perf or SysFS). Refactor the PM notifier and improve locking usage (including for syscfg). - Patches 24 ~ 31: Support save and restore context for TRBE and manages activated paths during CPU idle and CPU hotplug. Verification: This series has been verified on Juno-r0 and r2 platform. Stress test script: #!/usr/bin/bash echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink while true; do echo 0 > /sys/devices/system/cpu/cpu2/online; echo 1 > /sys/devices/system/cpu/cpu2/online; done & while true; do echo 1 > /sys/bus/coresight/devices/etm2/enable_source; echo 0 > /sys/bus/coresight/devices/etm2/enable_source; done & Test script with kernel module insmod / rmmod: #!/bin/bash modules=( "coresight" "coresight_dummy" "coresight_replicator" "coresight_tpiu" "coresight_cpu_debug" "coresight_etb10" "coresight_stm" "coresight_trbe" "coresight_tmc" "coresight_ctcu" "coresight_catu" "coresight_etm4x" "coresight_cti" "coresight_funnel" "coresight_tnoc" ) module_dir="/mnt/build/drivers/hwtracing/coresight/" if [[ "$1" == "in" ]]; then echo "Inserting modules..." for mod in "${modules[@]}"; do modprobe $mod && echo "Loaded $mod" || echo "Failed to load $mod" done elif [[ "$1" == "rm" ]]; then echo "Removing modules..." # Remove in reverse order to respect dependencies for (( idx=${#modules[@]}-1 ; idx>=0 ; idx-- )); do mod="${modules[$idx]}" echo "Removing $mod..." rmmod "$mod" && echo "Removed $mod" || echo "Failed to remove $mod" done fi --- Changes in v3: - Fixed building failure in ETMv3 driver (kernel test robot). - Refactoring ETMv3 change for checking CPU ID (Levi). - Fixed NULL pointer issue during CPU idle (James). - Fixed lockdep complaint for HARDIRQ-safe and HARDIRA-unsafe (James). - Fixed acquiring mutex in atomic context (James). - Rebased on the latest coresight-next branch. - Link to v2: https://lore.kernel.org/r/20250701-arm_cs_pm_fix_v3-v2-0-23ebb864fcc1@arm.c… Changes in v2: - Refactored ETMv4 suspend and resume for reusing the normal enabling and disabling flows (James). - Used a per-CPU structure to maintain path pointers (James). - Supported helpers in CPU PM flows (James). - Fixed the SMP-safe access to device mode. - Fixed the context synchronization in ETMv4x driver. - Link to v1: https://lore.kernel.org/linux-arm-kernel/20250516160742.1200904-1-leo.yan@a… Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (30): coresight: Change device mode to atomic type coresight: etm4x: Always set tracer's device mode on target CPU coresight: etm3x: Always set tracer's device mode on target CPU coresight: etm4x: Correct polling IDLE bit coresight: etm4x: Ensure context synchronization is not ignored coresight: etm4x: Add context synchronization before enabling trace coresight: etm4x: Properly control filter in CPU idle with FEAT_TRF coresight: etm4x: Remove the state_needs_restore flag coresight: etm4x: Add flag to control single-shot restart coresight: etm4x: Reuse normal enable and disable logic in CPU idle coresight: Populate CPU ID into the coresight_device structure coresight: sysfs: Validate CPU online status for per-CPU sources coresight: Set per CPU source pointer coresight: Register CPU PM notifier in core layer coresight: etm4x: Hook CPU PM callbacks coresight: Add callback to determine if context save/restore is needed coresight: etm4x: Remove redundant condition checks in save and restore coresight: cti: Fix race condition by using device mode coresight: cti: Introduce CS_MODE_DEBUG mode coresight: cti: Register PM notifier after data initialization coresight: cti: Properly handle modes in CPU PM notifiers coresight: cti: Make spin lock usage consistent coresight: syscfg: Use spinlock to protect active variables coresight: Add per-CPU path pointer coresight: Add 'in_idle' argument to path enable/disable functions coresight: Control path during CPU idle coresight: Add PM callbacks for percpu sink coresight: Take hotplug lock in enable_source_store() for Sysfs mode coresight: Move CPU hotplug callbacks to core layer coresight: Manage activated path during CPU hotplug Yabin Cui (1): coresight: trbe: Save and restore state across CPU low power state drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 337 ++++++++++++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 1 + drivers/hwtracing/coresight/coresight-cti-core.c | 69 ++- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-dummy.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + drivers/hwtracing/coresight/coresight-etm3x-core.c | 55 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 491 ++++++--------------- drivers/hwtracing/coresight/coresight-etm4x.h | 62 --- drivers/hwtracing/coresight/coresight-funnel.c | 1 + drivers/hwtracing/coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + drivers/hwtracing/coresight/coresight-syscfg.c | 22 +- drivers/hwtracing/coresight/coresight-syscfg.h | 2 + drivers/hwtracing/coresight/coresight-sysfs.c | 10 + drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 1 + drivers/hwtracing/coresight/coresight-tpdm.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + drivers/hwtracing/coresight/coresight-trbe.c | 85 ++++ drivers/hwtracing/coresight/ultrasoc-smb.c | 1 + include/linux/coresight.h | 55 ++- 23 files changed, 687 insertions(+), 515 deletions(-) --- base-commit: 559d6c380ea0a27e71d0269410301303515e4179 change-id: 20250909-arm_coresight_power_management_fix-139873f942e8 Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month, 2 weeks

Re: [PATCH v3 1/2] dt-bindings: arm: add CTCU device for QCS8300

by Suzuki K Poulose

On 13/10/2025 09:34, Jie Gan wrote: > The CTCU device for QCS8300 shares the same configurations as SA8775p. Add > a fallback to enable the CTCU for QCS8300 to utilize the compitable of the > SA8775p. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > index c969c16c21ef..460f38ddbd73 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml > @@ -26,8 +26,13 @@ description: | > > properties: > compatible: > - enum: > - - qcom,sa8775p-ctcu > + oneOf: > + - items: > + - enum: > + - qcom,qcs8300-ctcu > + - const: qcom,sa8775p-ctcu > + - enum: > + - qcom,sa8775p-ctcu > > reg: > maxItems: 1 > Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 month, 2 weeks

Re: [PATCH v4 05/11] coresight: etm4x: Ensure context synchronization is not ignored

by Suzuki K Poulose

On 27/10/2025 10:43, Yeoreum Yun wrote: > Hi Suzuki, >> On 24/10/2025 17:45, Leo Yan wrote: >>> As recommended in section 4.3.7 "Synchronization of register updates" of >>> ARM IHI0064H.b, a self-hosted trace analyzer should always executes an >>> ISB instruction after programming the trace unit registers. >>> >>> An ISB works as a context synchronization event; a DSB is not required. >>> Removes the redundant barrier in the enabling flow. >> >> It is required for MMIO based instances and must be retained. > > I think it seems fine. since the the etm4x device mmio is mapped as > Device-nGnRE and according to the section Leo mention: > > Synchronization when using the memory-mapped interface > .. > When disabling or enabling the trace unit, the trace analyzer must poll TRCSTATR to check the trace unit is either > idle or not idle, as described in Use of the trace unit main enable bit on page 4-169: > • When the memory is marked as Device-nGnRE or stronger. > — Write to enable or disable the trace unit. > — Poll TRCSTATR to ensure the previous write has completed. > — Execute an ISB operation. > > Therefore, we can omit the dsb in here. You are right, to be precise, as long as we quote the following, I am fine. Section 4.3.7, Synchronization when using the memory-mapped interface - When using the memory-mapped interface to program the trace unit, the trace analyzer must ensure that writes have completed, to ensure that the trace unit is fully programmed and either enabled or disabled. • If the memory marked is as Device-nGnRE or stronger, read back the value of any register in the trace unit. This relies on peripheral coherence order defined in the Arm architecture. Suzuki > > [...] > > Thanks. > > -- > Sincerely, > Yeoreum Yun

1 month, 2 weeks

Re: [PATCH v3 0/3] add sysfs nodes to configure TPDA's registers

by Suzuki K Poulose

On 27/10/2025 01:14, Jie Gan wrote: > > > On 8/27/2025 6:55 PM, Jie Gan wrote: >> Patchset 1 introduces configuration of the cross-trigger registers with >> appropriate values to enable proper generation of cross-trigger packets. >> >> Patchset 2 introduces a logic to configure the TPDA_SYNCR register, >> which determines the frequency of ASYNC packet generation. These packets >> assist userspace tools in accurately identifying each valid packet. >> >> Patchset 3 introduces a sysfs node to initiate a flush request for the >> specific port, forcing the data to synchronize and be transmitted to the >> sink device. >> > > Gentle reminder. Please could you fix the dates and version to v6.19 ? Suzuki > > Thanks, > Jie > >> Changes in V3: >> 1. Optimizing codes according to James's comment. >> Link to V2 - https://lore.kernel.org/all/20250827042042.6786-1- >> jie.gan(a)oss.qualcomm.com/ >> >> Changes in V2: >> 1. Refactoring the code based on James's comment for optimization. >> Link to V1 - https://lore.kernel.org/all/20250826070150.5603-1- >> jie.gan(a)oss.qualcomm.com/ >> >> Tao Zhang (3): >> coresight: tpda: add sysfs nodes for tpda cross-trigger configuration >> coresight: tpda: add logic to configure TPDA_SYNCR register >> coresight: tpda: add sysfs node to flush specific port >> >> .../testing/sysfs-bus-coresight-devices-tpda | 50 ++++ >> drivers/hwtracing/coresight/coresight-tpda.c | 278 ++++++++++++++++++ >> drivers/hwtracing/coresight/coresight-tpda.h | 33 ++- >> 3 files changed, 360 insertions(+), 1 deletion(-) >> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight- >> devices-tpda >> >

1 month, 2 weeks

Re: [PATCH v3 2/3] coresight: tpdm: add static tpdm support

by Suzuki K Poulose

On 13/10/2025 07:11, Jie Gan wrote: > The static TPDM function as a dummy source, however, it is essential > to enable the port connected to the TPDA and configure the element size. > Without this, the TPDA cannot correctly receive trace data from the > static TPDM. Since the static TPDM does not require MMIO mapping to > access its registers, a clock controller is not mandatory for its > operation. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 9 ++ > drivers/hwtracing/coresight/coresight-tpdm.c | 148 +++++++++++++++++++++------ > drivers/hwtracing/coresight/coresight-tpdm.h | 8 ++ > 3 files changed, 131 insertions(+), 34 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 333b3cb23685..4e93fa5bace4 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -68,6 +68,15 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > int rc = -EINVAL; > struct tpdm_drvdata *tpdm_data = dev_get_drvdata(csdev->dev.parent); > > + if (coresight_is_static_tpdm(csdev)) { > + rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > + "qcom,dsb-element-bits", &drvdata->dsb_esize); > + rc &= fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > + "qcom,cmb-element-bits", &drvdata->cmb_esize); > + This doesn't match the "dynamic" tpdm case ? We mandate that static TPDMs have DSB and CMB. I would rather set the appropriate flags in tpdm_drvdata->dsb/cmb in the TPDM driver for static tpdms and not let the "static" vs "dynamic" creep into the TPDA and other users. e.g., in TPDM driver: if (static_tpdm()) { tpdm_data->dsb = has_dsb_element_bits_property; tpdm_data->cmb = has_cmb_element_bits_property; } > + goto out; > + } > + > if (tpdm_data->dsb) { > rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > "qcom,dsb-element-bits", &drvdata->dsb_esize); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 7214e65097ec..1766b0182819 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -495,7 +495,9 @@ static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event, > return -EBUSY; > } > > - __tpdm_enable(drvdata); > + if (!coresight_is_static_tpdm(csdev)) > + __tpdm_enable(drvdata); > + > drvdata->enable = true; > spin_unlock(&drvdata->spinlock); > > @@ -551,7 +553,9 @@ static void tpdm_disable(struct coresight_device *csdev, > return; > } > > - __tpdm_disable(drvdata); > + if (!coresight_is_static_tpdm(csdev)) > + __tpdm_disable(drvdata); minor nit: It is much safer to do this check in __tpdm_xxable() and return early. > + > coresight_set_mode(csdev, CS_MODE_DISABLED); > drvdata->enable = false; > spin_unlock(&drvdata->spinlock); > @@ -1342,10 +1346,9 @@ static const struct attribute_group *tpdm_attr_grps[] = { > NULL, > }; > > -static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > +static int tpdm_probe(struct device *dev, struct resource *res) > { > void __iomem *base; > - struct device *dev = &adev->dev; > struct coresight_platform_data *pdata; > struct tpdm_drvdata *drvdata; > struct coresight_desc desc = { 0 }; > @@ -1354,32 +1357,33 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > pdata = coresight_get_platform_data(dev); > if (IS_ERR(pdata)) > return PTR_ERR(pdata); > - adev->dev.platform_data = pdata; > + dev->platform_data = pdata; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > return -ENOMEM; > - drvdata->dev = &adev->dev; > + drvdata->dev = dev; > dev_set_drvdata(dev, drvdata); > > - base = devm_ioremap_resource(dev, &adev->res); > - if (IS_ERR(base)) > - return PTR_ERR(base); > + if (res) { > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > > - drvdata->base = base; > + drvdata->base = base; > + ret = tpdm_datasets_setup(drvdata); > + if (ret) > + return ret; > > - ret = tpdm_datasets_setup(drvdata); > - if (ret) > - return ret; > + if (drvdata && tpdm_has_dsb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > > - if (drvdata && tpdm_has_dsb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,dsb-msrs-num", &drvdata->dsb_msr_num); > - > - if (drvdata && tpdm_has_cmb_dataset(drvdata)) > - of_property_read_u32(drvdata->dev->of_node, > - "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > + if (drvdata && tpdm_has_cmb_dataset(drvdata)) > + of_property_read_u32(drvdata->dev->of_node, > + "qcom,cmb-msrs-num", &drvdata->cmb_msr_num); > + } > > /* Set up coresight component description */ > desc.name = coresight_alloc_device_name(&tpdm_devs, dev); > @@ -1388,34 +1392,51 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > desc.type = CORESIGHT_DEV_TYPE_SOURCE; > desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM; > desc.ops = &tpdm_cs_ops; > - desc.pdata = adev->dev.platform_data; > - desc.dev = &adev->dev; > + desc.pdata = dev->platform_data; > + desc.dev = dev; > desc.access = CSDEV_ACCESS_IOMEM(base); > - desc.groups = tpdm_attr_grps; > + if (res) > + desc.groups = tpdm_attr_grps; > drvdata->csdev = coresight_register(&desc); > if (IS_ERR(drvdata->csdev)) > return PTR_ERR(drvdata->csdev); > > spin_lock_init(&drvdata->spinlock); > > - /* Decrease pm refcount when probe is done.*/ > - pm_runtime_put(&adev->dev); > - > return 0; > } > > -static void tpdm_remove(struct amba_device *adev) > +static int tpdm_remove(struct device *dev) > { > - struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev); > > coresight_unregister(drvdata->csdev); > + > + return 0; > +} > + > +static int dynamic_tpdm_probe(struct amba_device *adev, > + const struct amba_id *id) > +{ > + int ret; > + > + ret = tpdm_probe(&adev->dev, &adev->res); > + if (!ret) > + pm_runtime_put(&adev->dev); > + > + return ret; > +} > + > +static void dynamic_tpdm_remove(struct amba_device *adev) > +{ > + tpdm_remove(&adev->dev); > } > > /* > * Different TPDM has different periph id. > * The difference is 0-7 bits' value. So ignore 0-7 bits. > */ > -static const struct amba_id tpdm_ids[] = { > +static const struct amba_id dynamic_tpdm_ids[] = { > { > .id = 0x001f0e00, > .mask = 0x00ffff00, > @@ -1423,17 +1444,76 @@ static const struct amba_id tpdm_ids[] = { > { 0, 0, NULL }, > }; > > -static struct amba_driver tpdm_driver = { > +MODULE_DEVICE_TABLE(amba, dynamic_tpdm_ids); > + > +static struct amba_driver dynamic_tpdm_driver = { > .drv = { > .name = "coresight-tpdm", > .suppress_bind_attrs = true, > }, > - .probe = tpdm_probe, > - .id_table = tpdm_ids, > - .remove = tpdm_remove, > + .probe = dynamic_tpdm_probe, > + .id_table = dynamic_tpdm_ids, > + .remove = dynamic_tpdm_remove, > }; > > -module_amba_driver(tpdm_driver); > +static int tpdm_platform_probe(struct platform_device *pdev) > +{ > + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + int ret; > + > + pm_runtime_get_noresume(&pdev->dev); > + pm_runtime_set_active(&pdev->dev); > + pm_runtime_enable(&pdev->dev); > + > + ret = tpdm_probe(&pdev->dev, res); > + pm_runtime_put(&pdev->dev); > + if (ret) > + pm_runtime_disable(&pdev->dev); > + > + return ret; > +} > + > +static void tpdm_platform_remove(struct platform_device *pdev) > +{ > + struct tpdm_drvdata *drvdata = dev_get_drvdata(&pdev->dev); > + > + if (WARN_ON(!drvdata)) > + return; > + > + tpdm_remove(&pdev->dev); > + pm_runtime_disable(&pdev->dev); > +} > + > +static const struct of_device_id static_tpdm_match[] = { > + {.compatible = "qcom,coresight-static-tpdm"}, > + {} > +}; > + > +MODULE_DEVICE_TABLE(of, static_tpdm_match); > + > +static struct platform_driver static_tpdm_driver = { > + .probe = tpdm_platform_probe, > + .remove = tpdm_platform_remove, > + .driver = { > + .name = "coresight-static-tpdm", > + .of_match_table = static_tpdm_match, > + .suppress_bind_attrs = true, > + }, > +}; > + > +static int __init tpdm_init(void) > +{ > + return coresight_init_driver("tpdm", &dynamic_tpdm_driver, &static_tpdm_driver, > + THIS_MODULE); > +} > + > +static void __exit tpdm_exit(void) > +{ > + coresight_remove_driver(&dynamic_tpdm_driver, &static_tpdm_driver); > +} > + > +module_init(tpdm_init); > +module_exit(tpdm_exit); > > MODULE_LICENSE("GPL"); > MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h > index b11754389734..9f52c88ce5c1 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.h > +++ b/drivers/hwtracing/coresight/coresight-tpdm.h > @@ -343,4 +343,12 @@ struct tpdm_dataset_attribute { > enum dataset_mem mem; > u32 idx; > }; > + > +static inline bool coresight_is_static_tpdm(struct coresight_device *csdev) > +{ > + struct device_node *node = csdev->dev.parent->of_node; > + > + return (csdev && > + of_device_is_compatible(node, "qcom,coresight-static-tpdm")); Why do we have to go check the firmware table all the time ? Could we not cache this in drvdata ? Or even better, we can use the csdev->access by using : coresight_device_is_tpdm() return (coresight_device_is_tpdm(csdev) && !csdev->access->base); Suzuki

1 month, 2 weeks

[PATCH 0/1] coresight: fix issue with insufficient claim tags

by Mike Leach

All CoreSight compliant components have an implementation defined number of 0 to 8 claim tag bits in the claim tag registers. These are used to claim the CoreSight resources by system agents. ARM recommends implementions have 4 claim tag registers. The CoreSight drivers implement a 2 claim tag bit protocol to allow self hosted and external debug agents to manage access to the hardware. However, if there are less than 2 claim tags available the protocol incorrectly returns an error on device claim, as no checks are made. If insufficient claim tags are present in a component then the protocol must return success on claim / disclaim to allow components to be used normally. Changes read the CLAIMSET bits to establish the number of available tags, and adjust the claim returns accordingly. Applies to coresignt/next Mike Leach (1): coresight: fix issue where coresight component has no claimtags drivers/hwtracing/coresight/coresight-core.c | 26 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-priv.h | 8 ++++++ 2 files changed, 34 insertions(+) -- 2.32.0

1 month, 3 weeks

[PATCH] perf cs-etm: Mute enumeration value warning

by Leo Yan

When the OpenCSD library introduces a new enumeration value (for example, in the v1.7.1 release), the perf build fails with an error: util/cs-etm-decoder/cs-etm-decoder.c:600:10: error: enumeration value 'OCSD_GEN_TRC_ELEM_ITMTRACE' not explicitly handled in switch [-Werror, -Wswitch-enum] 600 | switch (elem->elem_type) { | ^~~~~~~~~~~~~~~ 1 error generated. Convert to if-else sentences to mute the enumeration value warning, which can avoid build failures whenever the lib is updated. No functional change. Suggested-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 44 +++++-------------- 1 file changed, 11 insertions(+), 33 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index b85a8837bddc..3050fe212666 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -588,6 +588,7 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( const ocsd_generic_trace_elem *elem) { ocsd_datapath_resp_t resp = OCSD_RESP_CONT; + ocsd_gen_trc_elem_t type; struct cs_etm_decoder *decoder = (struct cs_etm_decoder *) context; struct cs_etm_queue *etmq = decoder->data; struct cs_etm_packet_queue *packet_queue; @@ -597,52 +598,29 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( if (!packet_queue) return OCSD_RESP_FATAL_SYS_ERR; - switch (elem->elem_type) { - case OCSD_GEN_TRC_ELEM_UNKNOWN: - break; - case OCSD_GEN_TRC_ELEM_EO_TRACE: - case OCSD_GEN_TRC_ELEM_NO_SYNC: - case OCSD_GEN_TRC_ELEM_TRACE_ON: + type = elem->elem_type; + + if (type == OCSD_GEN_TRC_ELEM_EO_TRACE || + type == OCSD_GEN_TRC_ELEM_NO_SYNC || + type == OCSD_GEN_TRC_ELEM_TRACE_ON) resp = cs_etm_decoder__buffer_discontinuity(etmq, packet_queue, trace_chan_id); - break; - case OCSD_GEN_TRC_ELEM_INSTR_RANGE: + else if (type == OCSD_GEN_TRC_ELEM_INSTR_RANGE) resp = cs_etm_decoder__buffer_range(etmq, packet_queue, elem, trace_chan_id); - break; - case OCSD_GEN_TRC_ELEM_EXCEPTION: + else if (type == OCSD_GEN_TRC_ELEM_EXCEPTION) resp = cs_etm_decoder__buffer_exception(etmq, packet_queue, elem, trace_chan_id); - break; - case OCSD_GEN_TRC_ELEM_EXCEPTION_RET: + else if (type == OCSD_GEN_TRC_ELEM_EXCEPTION_RET) resp = cs_etm_decoder__buffer_exception_ret(etmq, packet_queue, trace_chan_id); - break; - case OCSD_GEN_TRC_ELEM_TIMESTAMP: + else if (type == OCSD_GEN_TRC_ELEM_TIMESTAMP) resp = cs_etm_decoder__do_hard_timestamp(etmq, elem, trace_chan_id, indx); - break; - case OCSD_GEN_TRC_ELEM_PE_CONTEXT: + else if (type == OCSD_GEN_TRC_ELEM_PE_CONTEXT) resp = cs_etm_decoder__set_tid(etmq, packet_queue, elem, trace_chan_id); - break; - /* Unused packet types */ - case OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH: - case OCSD_GEN_TRC_ELEM_ADDR_NACC: - case OCSD_GEN_TRC_ELEM_CYCLE_COUNT: - case OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN: - case OCSD_GEN_TRC_ELEM_EVENT: - case OCSD_GEN_TRC_ELEM_SWTRACE: - case OCSD_GEN_TRC_ELEM_CUSTOM: - case OCSD_GEN_TRC_ELEM_SYNC_MARKER: - case OCSD_GEN_TRC_ELEM_MEMTRANS: -#if (OCSD_VER_NUM >= 0x010400) - case OCSD_GEN_TRC_ELEM_INSTRUMENTATION: -#endif - default: - break; - } return resp; } -- 2.34.1

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