CoreSight

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2097 discussions

Re: [PATCH 1/9] dt-bindings: arm: Add support for DSB element

by Tao Zhang

在 9/8/2022 6:54 PM, Krzysztof Kozlowski 写道: > On 08/09/2022 10:44, Tao Zhang wrote: >> Add property "qcom,dsb-elem-size" to support DSB element for TPDA. >> Specifies the DSB element size supported by each monitor connected >> to the aggregator on each port. Should be specified in pairs (port, >> dsb element size). >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> index eb9bfc5..1bb3fdf 100644 >> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml >> @@ -40,6 +40,13 @@ properties: >> minItems: 1 >> maxItems: 2 >> >> + qcom,dsb-elem-size: >> + description: | >> + Specifies the DSB element size supported by each monitor >> + connected to the aggregator on each port. Should be specified >> + in pairs (port, dsb element size). >> + $ref: /schemas/types.yaml#/definitions/uint32-array > So it is rather uint32-matrix (need to describe the items subschema). > What about maxItems? > > Best regards, > Krzysztof Yes, indeed it should be uint32-matrix here. I will update in the next release. The "maxItems" cannot be known explicitly because it depends on how many DSB subunit TPDMs are connected to the TPDA input ports. Usually the number of the items is 1 to several, but there is no limit to its maximum value. Best regards, Tao

2 years, 1 month

Re: [PATCH] coresight: docs: Fix a broken reference

by Suzuki K Poulose

Cc: acme On 22/08/2022 17:02, Mathieu Poirier wrote: > On Sun, Jul 31, 2022 at 09:06:48AM +0200, Christophe JAILLET wrote: >> Since the commit in Fixes: tag, "coresight-cpu-debug.txt" has been turned >> into "arm,coresight-cpu-debug.yaml". >> >> Update the doc accordingly to avoid a 'make htmldocs' warning >> >> Fixes: 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") >> Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> >> --- >> Documentation/trace/coresight/coresight-cpu-debug.rst | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> > > Applied. fyi, there is another patch fixing the same here. https://lkml.kernel.org/r/20815dbff3d27f5d3e6876363f052d2a08ad2e72.16608294… We may have to decide which one goes in. Cheers Suzuki > > Thanks, > Mathieu > >> diff --git a/Documentation/trace/coresight/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst >> index 993dd294b81b..836b35532667 100644 >> --- a/Documentation/trace/coresight/coresight-cpu-debug.rst >> +++ b/Documentation/trace/coresight/coresight-cpu-debug.rst >> @@ -117,7 +117,8 @@ divide into below cases: >> Device Tree Bindings >> -------------------- >> >> -See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. >> +See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for >> +details. >> >> >> How to use the module >> -- >> 2.34.1 >>

2 years, 1 month

Re: [PATCH 06/13] Documentation: coresight: fix a documentation build warning

by Suzuki K Poulose

On 18/08/2022 14:38, Mauro Carvalho Chehab wrote: > Using wildcards for cross-reference doesn't work, as the Sphinx > automarkup plugin is not smart enough. So, changeset > c06475910b52 ("Documentation: coresight: Escape coresight bindings file wildcard") > tried to fix it, but at the wrong way, as it the building system > will keep producing warnings about that: > > Warning: Documentation/trace/coresight/coresight.rst references a file that doesn't exist: Documentation/devicetree/bindings/arm/arm,coresight- > > As automarkup will still try (and fail) to create a cross reference. > So, instead, change the markup to ensure that the warning won't be > reported. > > Fixes: c06475910b52 ("Documentation: coresight: Escape coresight bindings file wildcard") > Cc: Bagas Sanjaya <bagasdotme(a)gmail.com> > Signed-off-by: Mauro Carvalho Chehab <mchehab(a)kernel.org> Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > > See [PATCH 00/13] at: https://lore.kernel.org/all/cover.1660829433.git.mchehab@kernel.org/ > > Documentation/trace/coresight/coresight.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst > index 4a71ea6cb390..826e59a698da 100644 > --- a/Documentation/trace/coresight/coresight.rst > +++ b/Documentation/trace/coresight/coresight.rst > @@ -130,7 +130,7 @@ Misc: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/arm,coresight-\*.yaml for details. > +See ``Documentation/devicetree/bindings/arm/arm,coresight-*.yaml`` for details. > > As of this writing drivers for ITM, STMs and CTIs are not provided but are > expected to be added as the solution matures.

2 years, 1 month

Re: [PATCH 05/13] dt-bindings: arm: update arm,coresight-cpu-debug.yaml reference

by Suzuki K Poulose

On 18/08/2022 14:38, Mauro Carvalho Chehab wrote: > Changeset 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") > renamed: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > to: Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml. > > Update its cross-reference accordingly. > > Fixes: 66d052047ca8 ("dt-bindings: arm: Convert CoreSight CPU debug to DT schema") > Signed-off-by: Mauro Carvalho Chehab <mchehab(a)kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > --- > > See [PATCH 00/13] at: https://lore.kernel.org/all/cover.1660829433.git.mchehab@kernel.org/ > > Documentation/trace/coresight/coresight-cpu-debug.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/trace/coresight/coresight-cpu-debug.rst b/Documentation/trace/coresight/coresight-cpu-debug.rst > index 993dd294b81b..79bbe587e5e8 100644 > --- a/Documentation/trace/coresight/coresight-cpu-debug.rst > +++ b/Documentation/trace/coresight/coresight-cpu-debug.rst > @@ -117,7 +117,7 @@ divide into below cases: > Device Tree Bindings > -------------------- > > -See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details. > +See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for details. > > > How to use the module

2 years, 1 month

[PATCH v8 00/13] perf: test: Add trace data quality tests for CoreSight

by carsten.haitzler＠foss.arm.com

From: Carsten Haitzler <carsten.haitzler(a)arm.com> This series adds more test cases to perf test as well as new infrastructure for testing coresight data quality to ensure the data coming out of the kernel via perf actually contains useful information. Signed-off-by: Carsten Haitzler <carsten.haitzler(a)arm.com> Carsten Haitzler (13): perf test: Add CoreSight shell lib shared code for future tests perf test: Add build infra for perf test tools for CoreSight tests perf test: Add asm pureloop test tool perf test: Add asm pureloop test shell script perf test: Add git ignore for perf data generated by the CoreSight tests perf test: Add memcpy thread test tool perf test: Add memcpy thread test shell script perf test: Add thread loop test tool perf test: Add thread loop test shell scripts perf test: Add unroll thread test tool perf test: Add unroll thread test shell script perf test: Add git ignore for tmp and output files of CoreSight tests perf test: Add relevant documentation about CoreSight testing .../trace/coresight/coresight-perf.rst | 158 ++++++++++++++++++ MAINTAINERS | 1 + tools/perf/.gitignore | 6 +- .../perf/Documentation/perf-arm-coresight.txt | 5 + tools/perf/Makefile.config | 2 + tools/perf/Makefile.perf | 15 +- tools/perf/tests/shell/coresight/Makefile | 30 ++++ .../tests/shell/coresight/Makefile.miniconfig | 14 ++ .../tests/shell/coresight/asm_pure_loop.sh | 18 ++ .../shell/coresight/asm_pure_loop/.gitignore | 1 + .../shell/coresight/asm_pure_loop/Makefile | 34 ++++ .../coresight/asm_pure_loop/asm_pure_loop.S | 28 ++++ .../shell/coresight/memcpy_thread/.gitignore | 1 + .../shell/coresight/memcpy_thread/Makefile | 33 ++++ .../coresight/memcpy_thread/memcpy_thread.c | 79 +++++++++ .../shell/coresight/memcpy_thread_16k_10.sh | 18 ++ .../shell/coresight/thread_loop/.gitignore | 1 + .../shell/coresight/thread_loop/Makefile | 33 ++++ .../shell/coresight/thread_loop/thread_loop.c | 86 ++++++++++ .../coresight/thread_loop_check_tid_10.sh | 19 +++ .../coresight/thread_loop_check_tid_2.sh | 19 +++ .../coresight/unroll_loop_thread/.gitignore | 1 + .../coresight/unroll_loop_thread/Makefile | 33 ++++ .../unroll_loop_thread/unroll_loop_thread.c | 74 ++++++++ .../shell/coresight/unroll_loop_thread_10.sh | 18 ++ tools/perf/tests/shell/lib/coresight.sh | 132 +++++++++++++++ 26 files changed, 855 insertions(+), 4 deletions(-) create mode 100644 Documentation/trace/coresight/coresight-perf.rst create mode 100644 tools/perf/Documentation/perf-arm-coresight.txt create mode 100644 tools/perf/tests/shell/coresight/Makefile create mode 100644 tools/perf/tests/shell/coresight/Makefile.miniconfig create mode 100755 tools/perf/tests/shell/coresight/asm_pure_loop.sh create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/asm_pure_loop/asm_pure_loop.S create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/memcpy_thread/memcpy_thread.c create mode 100755 tools/perf/tests/shell/coresight/memcpy_thread_16k_10.sh create mode 100644 tools/perf/tests/shell/coresight/thread_loop/.gitignore create mode 100644 tools/perf/tests/shell/coresight/thread_loop/Makefile create mode 100644 tools/perf/tests/shell/coresight/thread_loop/thread_loop.c create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_10.sh create mode 100755 tools/perf/tests/shell/coresight/thread_loop_check_tid_2.sh create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/.gitignore create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/Makefile create mode 100644 tools/perf/tests/shell/coresight/unroll_loop_thread/unroll_loop_thread.c create mode 100755 tools/perf/tests/shell/coresight/unroll_loop_thread_10.sh create mode 100644 tools/perf/tests/shell/lib/coresight.sh -- 2.32.0

2 years, 2 months

Re: [PATCH v8 13/13] perf test: Add relevant documentation about CoreSight testing

by Leo Yan

On Wed, Sep 07, 2022 at 10:59:55AM +0800, kernel test robot wrote: [...] > All warnings (new ones prefixed by >>): Thanks for reporting! > >> Documentation/trace/coresight/coresight-perf.rst:102: WARNING: Inline emphasis start-string without end-string. > > vim +102 Documentation/trace/coresight/coresight-perf.rst > > 96 > 97 CoreSight / ASM Pure Loop > 98 CoreSight / Memcpy 16k 10 Threads > 99 CoreSight / Thread Loop 10 Threads - Check TID > 100 etc. > 101 > > 102 These perf record tests will not run if the tool binaries do not exist > 103 in tests/shell/coresight/*/ and will be skipped. If you do not have > 104 CoreSight support in hardware then either do not build perf with > 105 CoreSight support or remove these binaries in order to not have these > 106 tests fail and have them skip instead. > 107 Hi Carsten, Just note that I reproduced the warning at my side; after I used the escape for '*' like below, the warning can be dismissed. tests/shell/coresight/\*/ Thanks, Leo

2 years, 2 months

[PATCH v4 00/13] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Applies to coresight/next [4d45bc82df66] Tested on DB410c Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (13): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: perf: traceid: Add perf notifiers for Trace ID perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 49 +-- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 92 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 79 ++++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 266 ++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 78 +++++ include/linux/coresight-pmu.h | 35 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 331 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 933 insertions(+), 225 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 2 months

[PATCH v13 0/9] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support docs: sysfs: coresight: Add sysfs ABI documentation for TPDM TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add coresight components for SM8250 ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series: "[v4,00/13] coresight: Add new API to allocate trace source ID values" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220823091009.… Changes from V12: 1. Fix the conflicts when apply patches to the latest base line. Mao Jinlong (9): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add coresight components arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 111 +++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 671 ++++++++++++++++++ drivers/hwtracing/coresight/Kconfig | 23 + drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 +- drivers/hwtracing/coresight/coresight-tpda.c | 208 ++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 + drivers/hwtracing/coresight/coresight-tpdm.c | 259 +++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 ++ include/linux/coresight.h | 1 + 13 files changed, 1509 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.17.1

2 years, 2 months

Re: [PATCH] coresight: cti-sysfs: Mark coresight_cti_reg_store() as __maybe_unused

by James Clark

On 01/09/2022 20:50, Nathan Chancellor wrote: > When building without CONFIG_CORESIGHT_CTI_INTEGRATION_REGS, there is a > warning about coresight_cti_reg_store() being unused in the file: > > drivers/hwtracing/coresight/coresight-cti-sysfs.c:184:16: warning: 'coresight_cti_reg_store' defined but not used [-Wunused-function] > 184 | static ssize_t coresight_cti_reg_store(struct device *dev, > | ^~~~~~~~~~~~~~~~~~~~~~~ > > This is expected as coresight_cti_reg_store() is only used in the > coresight_cti_reg_rw macro, which is only used in a block guarded by > CONFIG_CORESIGHT_CTI_INTEGRATION_REGS. Mark coresight_cti_reg_store() as > __maybe_unused to clearly indicate that the function may be unused > depending on the configuration. It would also be possible to fix this by wrapping the definitions in #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS. That way the maybe_unused isn't needed and it's a bit cleaner. Either way, thanks for the fix. Reviewed-by: James Clark <james.clark(a)arm.com> > > Fixes: fbca79e55429 ("coresight: cti-sysfs: Re-use same functions for similar sysfs register accessors") > Signed-off-by: Nathan Chancellor <nathan(a)kernel.org> > --- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > index 478b8d38b744..6d59c815ecf5 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c > @@ -181,9 +181,9 @@ static ssize_t coresight_cti_reg_show(struct device *dev, > } > > /* Write registers with power check only (no enable check). */ > -static ssize_t coresight_cti_reg_store(struct device *dev, > - struct device_attribute *attr, > - const char *buf, size_t size) > +static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, > + struct device_attribute *attr, > + const char *buf, size_t size) > { > struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr); > > base-commit: 0a98181f805058773961c5ab3172ecf1bf1ed0e1

2 years, 2 months

[PATCH v9 0/2] Add support for UltraSoc System Memory Buffer

by Junhao He

Add support for UltraSoc System Memory Buffer. Change since v8: - Insert a blank line at the end of the config tag in Kconfig. - Fix the "llseek" initialization. - Link: https://lore.kernel.org/linux-arm-kernel/20220816131634.38195-1-hejunhao3@h… Change since v7: - Use the macros for register bit flags and numbers of resource. - Fix punctuation. - Update the Date tag and the KernelVersion tag in the document. - Link: https://lore.kernel.org/lkml/20220712091353.34540-1-hejunhao3@huawei.com/ Change since v6: - Modify the code style and driver description according to Suzuki's comment. - Modify configuration of "drvdata->reading", to void problems in open/read concurrency scenario. - Rename the macro of "SMB_FLOW_MASK". - Use the "handle->head" to determine the page number and offset. - Link: https://lore.kernel.org/linux-arm-kernel/20220606130223.57354-1-liuqi115@hu… Change since v5: - Address the comments from Suzuki, add some comments in SMB document, and modify configuration of "drvdata->reading", to void problems in multi-core concurrency scenario - Link: https://lore.kernel.org/linux-arm-kernel/20220416083953.52610-1-liuqi115@hu… Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - Link: https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link: https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi115@hu… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link: https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB drivers .../sysfs-bus-coresight-devices-ultra_smb | 31 + .../trace/coresight/ultrasoc-smb.rst | 80 +++ drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 636 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 115 ++++ 6 files changed, 874 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.33.0

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