CoreSight

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2506 discussions

RE: [EXT] Re: [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property

by Linu Cherian

Hi Conor, > -----Original Message----- > From: Conor Dooley <conor(a)kernel.org> > Sent: Saturday, October 14, 2023 6:56 PM > To: Linu Cherian <lcherian(a)marvell.com> > Cc: Mike Leach <mike.leach(a)linaro.org>; suzuki.poulose(a)arm.com; > james.clark(a)arm.com; leo.yan(a)linaro.org; linux-arm- > kernel(a)lists.infradead.org; coresight(a)lists.linaro.org; linux- > kernel(a)vger.kernel.org; robh+dt(a)kernel.org; > krzysztof.kozlowski+dt(a)linaro.org; conor+dt(a)kernel.org; > devicetree(a)vger.kernel.org; Sunil Kovvuri Goutham > <sgoutham(a)marvell.com>; George Cherian <gcherian(a)marvell.com> > Subject: Re: [EXT] Re: [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add > "memory-region" property > > On Sat, Oct 14, 2023 at 11:36:37AM +0000, Linu Cherian wrote: > > > > + - description: Reserved meta data memory. Used for ETR and ETF > sinks. > > > > + > > > > + memory-region-names: > > > > + items: > > > > + - const: trace-mem > > > > + - const: metadata-mem > > > > + > > > > > > Is there a constraint required here? If we are using the memory area > > > for trace in a panic situation, then we must have the meta data > > > memory area defined? > > > Perhaps a set of names such as "etr-trace-mem", "panic-trace-mem" , > > > "panic-metadata-mem", were the first is for general ETR trace in > > > non-panic situation and then constrain the "panic-" areas to appear > together. > > > The "etr-trace-mem", "panic-trace-mem" could easily point to the > > > same area. > > > > > As noted above, we do not have other generic use case for these reserved > regions now. > > Hence two regions/names, panic-trace-mem and panic-metadata-mem > with > > constraints kept as > > minItems: 2 and maxItems: 2 would suffice ? > > Whatever you do, please delete the -mem suffix. Ack.

2 years

Re: [PATCH] Documentation: ABI: coresight-tpdm: Fix Bit[3] description indentation

by Suzuki K Poulose

On 17/10/2023 10:56, Bagas Sanjaya wrote: > Stephen Rothwell reported htmldocs warnings when merging coresight tree: > > Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm:48: ERROR: Unexpected indentation. > Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm:48: WARNING: Block quote ends without a blank line; unexpected unindent. > > Fix indentation alignment for Bit[3] list entry in dsb_mode description to > silence above warnings. > > Fixes: 535d80d3c10fff ("coresight-tpdm: Add node to set dsb programming mode") > Reported-by: Stephen Rothwell <sfr(a)canb.auug.org.au> > Closes: https://lore.kernel.org/linux-next/20231017143324.75387a21@canb.auug.org.au/ > Signed-off-by: Bagas Sanjaya <bagasdotme(a)gmail.com> > --- > Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > index f07218e788439d..4dd49b159543b6 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > @@ -54,8 +54,8 @@ Description: > Accepts the value needs to be greater than 0. What data > bits do is listed below. > Bit[0:1] : Test mode control bit for choosing the inputs. > - Bit[3] : Set to 0 for low performance mode. > - Set to 1 for high performance mode. > + Bit[3] : Set to 0 for low performance mode. Set to 1 for high > + performance mode. > Bit[4:8] : Select byte lane for high performance mode. > > What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx > > base-commit: 90a7371cb08d7e542fa4f283c881973bba09f23b Thanks, confirmed the patch to fix the issue. I have queued this to next. https://git.kernel.org/coresight/c/845333e5f0f3 Thanks Suzuki

2 years

Re: [PATCH] coresight: etm4x: Remove bogous __exit annotation for some functions

by Suzuki K Poulose

On 29/09/2023 09:16, Uwe Kleine-König wrote: > etm4_platform_driver (which lives in ".data" contains a reference to > etm4_remove_platform_dev(). So the latter must not be marked with __exit > which results in the function being discarded for a build with > CONFIG_CORESIGHT_SOURCE_ETM4X=y which in turn makes the remove pointer > contain invalid data. > > etm4x_amba_driver referencing etm4_remove_amba() has the same issue. > > Drop the __exit annotations for the two affected functions and a third > one that is called by the other two. > > For reasons I don't understand this isn't catched by building with > CONFIG_DEBUG_SECTION_MISMATCH=y. > > Fixes: c23bc382ef0e ("coresight: etm4x: Refactor probing routine") > Fixes: 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") > Signed-off-by: Uwe Kleine-König <u.kleine-koenig(a)pengutronix.de> Thanks for the fix, I can queue them via the coresight tree. Suzuki

2 years

[PATCH] coresight: Fix crash when Perf and sysfs modes are used concurrently

by James Clark

Partially revert the change in commit 6148652807ba ("coresight: Enable and disable helper devices adjacent to the path") which changed the bare call from source_ops(csdev)->enable() to coresight_enable_source() for Perf sessions. It was missed that coresight_enable_source() is specifically for the sysfs interface, rather than being a generic call. This interferes with the sysfs reference counting to cause the following crash: $ perf record -e cs_etm/@tmc_etr0/ -C 0 & $ echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink $ echo 1 > /sys/bus/coresight/devices/etm0/enable_source $ echo 0 > /sys/bus/coresight/devices/etm0/enable_source Unable to handle kernel NULL pointer dereference at virtual address 00000000000001d0 Internal error: Oops: 0000000096000004 [#1] PREEMPT SMP ... Call trace: etm4_disable+0x54/0x150 [coresight_etm4x] coresight_disable_source+0x6c/0x98 [coresight] coresight_disable+0x74/0x1c0 [coresight] enable_source_store+0x88/0xa0 [coresight] dev_attr_store+0x20/0x40 sysfs_kf_write+0x4c/0x68 kernfs_fop_write_iter+0x120/0x1b8 vfs_write+0x2dc/0x3b0 ksys_write+0x70/0x108 __arm64_sys_write+0x24/0x38 invoke_syscall+0x50/0x128 el0_svc_common.constprop.0+0x104/0x130 do_el0_svc+0x40/0xb8 el0_svc+0x2c/0xb8 el0t_64_sync_handler+0xc0/0xc8 el0t_64_sync+0x1a4/0x1a8 Code: d53cd042 91002000 b9402a81 b8626800 (f940ead5) ---[ end trace 0000000000000000 ]--- This commit linked below also fixes the issue, but has unlocked updates to the mode which could potentially race. So until we come up with a more complete solution that takes all locking and interaction between both modes into account, just revert back to the old behavior for Perf. Reported-by: Junhao He <hejunhao3(a)huawei.com> Closes: https://lore.kernel.org/linux-arm-kernel/20230921132904.60996-1-hejunhao3@h… Fixes: 6148652807ba ("coresight: Enable and disable helper devices adjacent to the path") Signed-off-by: James Clark <james.clark(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5ca6278baff4..89e8ed214ea4 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -493,7 +493,7 @@ static void etm_event_start(struct perf_event *event, int flags) goto fail_end_stop; /* Finally enable the tracer */ - if (coresight_enable_source(csdev, CS_MODE_PERF, event)) + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; /* @@ -587,7 +587,7 @@ static void etm_event_stop(struct perf_event *event, int mode) return; /* stop tracer */ - coresight_disable_source(csdev, event); + source_ops(csdev)->disable(csdev, event); /* tell the core */ event->hw.state = PERF_HES_STOPPED; -- 2.34.1

2 years

[PATCH V7 0/3] coresight: etm: Make cycle count threshold user configurable

by Anshuman Khandual

This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via the perf event attribute. But first, this implements an errata work around affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field. This series applies on coresight/for-next/queue. Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Jonathan Corbet <corbet(a)lwn.net> Cc: linux-doc(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Changes in V7: - Changed commit message for the second patch adding cc_threshold Changes in V6: https://lore.kernel.org/all/20230920095443.1126617-1-anshuman.khandual@arm.… - Renamed etm4_core_reads_wrong_ccitmin() as etm4_fixup_wrong_ccitmin() - Moved drvdata->ccitmin fixup inside etm4_fixup_wrong_ccitmin() Changes in V5: https://lore.kernel.org/all/20230821045216.641499-1-anshuman.khandual@arm.c… https://lore.kernel.org/all/20230915093649.435163-1-anshuman.khandual@arm.c… - Replaced 'where as' with single word 'whereas' - Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT Changes in V4: https://lore.kernel.org/all/20230818112051.594986-1-anshuman.khandual@arm.c… - Fixed a typo s/rangess/ranges, - Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin() - Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin() - Moved the comment inside etm4_core_reads_wrong_ccitmin() Changes in V3: https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.c… - Added errata work around affecting TRCIDR3.CCITMIN - Split the document update into a separate patch Changes in V2: https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.c… - s/treshhold/threshold Changes in V1: https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.… Anshuman Khandual (3): coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus coresight: etm: Make cycle count threshold user configurable Documentation: coresight: Add cc_threshold tunable Documentation/arch/arm64/silicon-errata.rst | 10 ++++ Documentation/trace/coresight/coresight.rst | 4 ++ .../hwtracing/coresight/coresight-etm-perf.c | 2 + .../coresight/coresight-etm4x-core.c | 46 ++++++++++++++++++- 4 files changed, 60 insertions(+), 2 deletions(-) -- 2.25.1

2 years

[PATCH V2] coresight: tmc: Make etr buffer mode user configurable from sysfs

by Anshuman Khandual

Currently TMC-ETR automatically selects the buffer mode from all available methods in the following sequentially fallback manner - also in that order. 1. FLAT mode with or without IOMMU 2. TMC-ETR-SG (scatter gather) mode when available 3. CATU mode when available But this order might not be ideal for all situations. For example if there is a CATU connected to ETR, it may be better to use TMC-ETR scatter gather method, rather than CATU. But hard coding such order changes will prevent us from testing or using a particular mode. This change provides following new sysfs tunables for the user to control TMC-ETR buffer mode explicitly, if required. This adds following new sysfs files for buffer mode selection purpose explicitly in the user space. /sys/bus/coresight/devices/tmc_etr<N>/buf_modes_available /sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred $ cat buf_modes_available auto flat tmc-sg catu ------------------> Supported TMC-ETR buffer modes $ echo catu > buf_mode_preferred -------> Explicit buffer mode request But explicit user request has to be within supported ETR buffer modes only. These sysfs interface files are exclussive to ETR, and hence these are not available for other TMC devices such as ETB or ETF etc. A new auto' mode (i.e ETR_MODE_AUTO) has been added to help fallback to the existing default behaviour, when user provided preferred buffer mode fails. ETR_MODE_FLAT and ETR_MODE_AUTO are always available as preferred modes. Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> --- This applies on v6.5-rc6 Changes in V2: - Renamed sysfs file etr_buf_modes_available as buf_modes_available - Renamed sysfs file buf_mode_current as buf_mode_preferred - Renamed etr_supports_flat_mode() as etr_can_use_flat_mode() - Renamed coresight_tmc_groups[] as coresight_etf_groups[] - Reused coresight_tmc_group[] for trigger_cntr and buffer_size - Fallback trying ETR_MODE_AUTO when user preferred mode fails - Moved ETR sysfs details into coresight-tmc-etr.c - Dropped etr_can_use_flat_mode() check while offering ETR_MODE_FLAT in sysfs - Moved struct etr_buf_hw inside coresight-tmc-etr.c - Moved get_etr_buf_hw() and etr_can_use_flat_mode() inside coresight-tmc-etr.c - Updated month in Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc Changes in V1: https://lore.kernel.org/all/20230728084837.276551-1-anshuman.khandual@arm.c… .../testing/sysfs-bus-coresight-devices-tmc | 16 +++ .../hwtracing/coresight/coresight-tmc-core.c | 15 ++- .../hwtracing/coresight/coresight-tmc-etr.c | 111 ++++++++++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 + 4 files changed, 131 insertions(+), 14 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc index 6aa527296c71..50833ce97300 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc @@ -91,3 +91,19 @@ Contact: Mathieu Poirier <mathieu.poirier(a)linaro.org> Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS mode. Writable only for TMC-ETR configurations. The value should be aligned to the kernel pagesize. + +What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available +Date: August 2023 +KernelVersion: 6.6 +Contact: Anshuman Khandual <anshuman.khandual(a)arm.com> +Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available + for the users to configure explicitly. This file is avaialble only + for TMC ETR devices. + +What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred +Date: August 2023 +KernelVersion: 6.6 +Contact: Anshuman Khandual <anshuman.khandual(a)arm.com> +Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could + only provide a mode which is supported for a given ETR device. This + file is available only for TMC ETR devices. diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index c106d142e632..7ec5365e2b64 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -10,6 +10,7 @@ #include <linux/device.h> #include <linux/idr.h> #include <linux/io.h> +#include <linux/iommu.h> #include <linux/err.h> #include <linux/fs.h> #include <linux/miscdevice.h> @@ -344,7 +345,14 @@ static const struct attribute_group coresight_tmc_mgmt_group = { .name = "mgmt", }; -static const struct attribute_group *coresight_tmc_groups[] = { +static const struct attribute_group *coresight_etf_groups[] = { + &coresight_tmc_group, + &coresight_tmc_mgmt_group, + NULL, +}; + +static const struct attribute_group *coresight_etr_groups[] = { + &coresight_etr_group, &coresight_tmc_group, &coresight_tmc_mgmt_group, NULL, @@ -465,6 +473,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) drvdata->memwidth = tmc_get_memwidth(devid); /* This device is not associated with a session */ drvdata->pid = -1; + drvdata->etr_mode = ETR_MODE_AUTO; if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { drvdata->size = tmc_etr_get_default_buffer_size(dev); @@ -474,16 +483,17 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) } desc.dev = dev; - desc.groups = coresight_tmc_groups; switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: + desc.groups = coresight_etf_groups; desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops = &tmc_etb_cs_ops; dev_list = &etb_devs; break; case TMC_CONFIG_TYPE_ETR: + desc.groups = coresight_etr_groups; desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM; desc.ops = &tmc_etr_cs_ops; @@ -496,6 +506,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) dev_list = &etr_devs; break; case TMC_CONFIG_TYPE_ETF: + desc.groups = coresight_etf_groups; desc.type = CORESIGHT_DEV_TYPE_LINKSINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 766325de0e29..52ce24afa323 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -26,6 +26,12 @@ struct etr_flat_buf { size_t size; }; +struct etr_buf_hw { + bool has_iommu; + bool has_etr_sg; + bool has_catu; +}; + /* * etr_perf_buffer - Perf buffer used for ETR * @drvdata - The ETR drvdaga this buffer has been allocated for. @@ -828,6 +834,22 @@ static inline int tmc_etr_mode_alloc_buf(int mode, } } +static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent); + buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); + buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata); +} + +static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size) +{ + bool has_sg = buf_hw->has_catu || buf_hw->has_etr_sg; + + return !has_sg || buf_hw->has_iommu || etr_buf_size < SZ_1M; +} + /* * tmc_alloc_etr_buf: Allocate a buffer use by ETR. * @drvdata : ETR device details. @@ -841,23 +863,22 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, int node, void **pages) { int rc = -ENOMEM; - bool has_etr_sg, has_iommu; - bool has_sg, has_catu; struct etr_buf *etr_buf; + struct etr_buf_hw buf_hw; struct device *dev = &drvdata->csdev->dev; - has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); - has_iommu = iommu_get_domain_for_dev(dev->parent); - has_catu = !!tmc_etr_get_catu_device(drvdata); - - has_sg = has_catu || has_etr_sg; - + get_etr_buf_hw(dev, &buf_hw); etr_buf = kzalloc(sizeof(*etr_buf), GFP_KERNEL); if (!etr_buf) return ERR_PTR(-ENOMEM); etr_buf->size = size; + /* If there is user directive for buffer mode, try that first */ + if (drvdata->etr_mode != ETR_MODE_AUTO) + rc = tmc_etr_mode_alloc_buf(drvdata->etr_mode, drvdata, + etr_buf, node, pages); + /* * If we have to use an existing list of pages, we cannot reliably * use a contiguous DMA memory (even if we have an IOMMU). Otherwise, @@ -870,14 +891,13 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, * Fallback to available mechanisms. * */ - if (!pages && - (!has_sg || has_iommu || size < SZ_1M)) + if (rc && !pages && etr_can_use_flat_mode(&buf_hw, size)) rc = tmc_etr_mode_alloc_buf(ETR_MODE_FLAT, drvdata, etr_buf, node, pages); - if (rc && has_etr_sg) + if (rc && buf_hw.has_etr_sg) rc = tmc_etr_mode_alloc_buf(ETR_MODE_ETR_SG, drvdata, etr_buf, node, pages); - if (rc && has_catu) + if (rc && buf_hw.has_catu) rc = tmc_etr_mode_alloc_buf(ETR_MODE_CATU, drvdata, etr_buf, node, pages); if (rc) { @@ -1800,3 +1820,70 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) return 0; } + +static const char *const buf_modes_str[] = { + [ETR_MODE_FLAT] = "flat", + [ETR_MODE_ETR_SG] = "tmc-sg", + [ETR_MODE_CATU] = "catu", + [ETR_MODE_AUTO] = "auto", +}; + +static ssize_t buf_modes_available_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct etr_buf_hw buf_hw; + ssize_t size = 0; + + get_etr_buf_hw(dev, &buf_hw); + size += sysfs_emit(buf, "%s ", buf_modes_str[ETR_MODE_AUTO]); + size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_FLAT]); + if (buf_hw.has_etr_sg) + size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_ETR_SG]); + + if (buf_hw.has_catu) + size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]); + + size += sysfs_emit_at(buf, size, "\n"); + return size; +} +static DEVICE_ATTR_RO(buf_modes_available); + +static ssize_t buf_mode_preferred_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%s\n", buf_modes_str[drvdata->etr_mode]); +} + +static ssize_t buf_mode_preferred_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct etr_buf_hw buf_hw; + + get_etr_buf_hw(dev, &buf_hw); + if (sysfs_streq(buf, buf_modes_str[ETR_MODE_FLAT])) + drvdata->etr_mode = ETR_MODE_FLAT; + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_ETR_SG]) && buf_hw.has_etr_sg) + drvdata->etr_mode = ETR_MODE_ETR_SG; + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_catu) + drvdata->etr_mode = ETR_MODE_CATU; + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO])) + drvdata->etr_mode = ETR_MODE_AUTO; + else + return -EINVAL; + return size; +} +static DEVICE_ATTR_RW(buf_mode_preferred); + +static struct attribute *coresight_etr_attrs[] = { + &dev_attr_buf_modes_available.attr, + &dev_attr_buf_mode_preferred.attr, + NULL, +}; + +const struct attribute_group coresight_etr_group = { + .attrs = coresight_etr_attrs, +}; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index b97da39652d2..e59d423a9749 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -135,6 +135,7 @@ enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ ETR_MODE_CATU, /* Use SG mechanism in CATU */ + ETR_MODE_AUTO, /* Use the default mechanism */ }; struct etr_buf_operations; @@ -207,6 +208,7 @@ struct tmc_drvdata { enum tmc_mem_intf_width memwidth; u32 trigger_cntr; u32 etr_caps; + enum etr_mode etr_mode; struct idr idr; struct mutex idr_mutex; struct etr_buf *sysfs_buf; @@ -334,5 +336,6 @@ void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); void tmc_etr_remove_catu_ops(void); struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, enum cs_mode mode, void *data); +extern const struct attribute_group coresight_etr_group; #endif -- 2.25.1

2 years

[PATCH v10 00/13] Add support to configure TPDM DSB subunit

by Tao Zhang

Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. root@qemuarm64:/sys/devices/platform/soc@0/6c08000.tpdm/tpdm1# ls -l drwxr-xr-x 2 root root 0 Jan 1 00:00 connections drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_edge -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_mode drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_msr drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_patt_type drwxr-xr-x 2 root root 0 Jan 1 00:00 dsb_trig_patt -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:00 dsb_trig_type -rw-r--r-- 1 root root 4096 Jan 1 00:02 enable_source --w------- 1 root root 4096 Jan 1 00:00 integration_test drwxr-xr-x 2 root root 0 Jan 1 00:00 power --w------- 1 root root 4096 Jan 1 00:02 reset_dataset lrwxrwxrwx 1 root root 0 Apr 5 2021 subsystem -> ../../../../../bus/coresight -rw-r--r-- 1 root root 4096 Apr 5 2021 uevent -r--r--r-- 1 root root 4096 Jan 1 00:00 waiting_for_supplier We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm1/reset_dataset echo 0x3 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_idx echo 0x1 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_mask echo 0x0 > /sys/bus/coresight/devices/tpdm1/dsb_edge/ctrl_val echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/enable_ts echo 1 > /sys/bus/coresight/devices/tpdm1/dsb_patt/set_type echo 0 > /sys/bus/coresight/devices/tpdm1/dsb_trig_ts echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_patt/tpmr5 echo 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm1/dsb_trig_patt/xpr2 echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v10 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v10 Changes in V10: 1. Use checking the number of DSB MSR instead of checking if DSB MSR is supported in the visiblity function. Thus only the available MSRs will be listed in the directory. -- Suzuki K Poulose 2. Rename the attribut group "tpdm_dsb_attrs_grp" to "tpdm_dsb_attr_grp". Changes in V9: 1. Adjust the alignment for all the patches in this series. -- Suzuki K Poulose 2. Initialize the variable "ret" to 0 in the patch#4. -- Suzuki K Poulose 3. Change the kernel version to 6.7 for all the sysfs files in the documents for this patch series. -- Suzuki K Poulose 4. Remove the parameter "max" from the general read/write functions in the patch#9 and patch#10. -- Suzuki K Poulose 5. Avoid releasing the lock in two different places in the patch#10. -- Suzuki K Poulose 6. Rename "dsb_patt_ts" to "enable_ts", and rename "dsb_patt_type" to "set_type" in the patch#11. Move these two sysfs files to the folder "dsb_patt". -- Suzuki K Poulose 7. Clear the relevant fields first in the function "set_dsb_tier". -- Suzuki K Poulose 8. Reading/writing the TIER register in the function "set_dsb_tier". -- Suzuki K Poulose 9. Read the property "qcom,dsb_msr_num" during probe. -- Suzuki K Poulose 10. Move the variable "dsb_msr_num" to "drvdata". -- Suzuki K Poulose 11. Move the msr number check to simple tpdm sysfs API. -- Suzuki K Poulose 12. Remove the needless "msr number" check in the function "tpdm_reset_datasets" -- Suzuki K Poulose Changes in V8: 1. Refine the function "tpda_set_element_size" and rename it to "tpda_get_element_size" in the patch#4. -- Suzuki K Poulose 2. Refine the functioin "tpda_enable_port" in the patch#4. -- Suzuki K Poulose 3. Write a helper to check if the TPDM has DSB dataset in the patch#5. -- Suzuki K Poulose 4. Move the function "tpdm_reset_datasets" to "datasets_setup" to call in the patch#5. -- Suzuki K Poulose 5. Refine the comment of DSB in "tpdm_drvdata" in the patch#5. -- Suzuki K Poulose 6. Refine the comments in the documents for this patch series. -- Suzuki K Poulose 7. Adjust the code alignment in this patch series. -- Suzuki K Poulose 8. Combine the mode related functions to one in the patch#8. -- Suzuki K Poulose 9. Refine the R/W functions of "dsb_mode" in the patch#8. -- Suzuki K Poulose 10. Adjust the macros of mode in the TPDM header file in the patch#8. -- Suzuki K Poulose 11. Remove the unused code and fix the warnings in compiling for the patch#9. -- kernel test robot 12. Use the following sysfs nodes to read/set edge control related value in the patch#9. dsb_edge/ \- ctrl_idx -> Set the index number \- ctrl_val -> Set the edge control value \- ctrl_mask -> Set the edge control mask \- edcr0 ... edcr15 -> Read the edge control value \- edcmr0 ... edcmr7 -> Read the edge control mask -- Suzuki K Poulose 13. Use the following sysfs nodes to read/set DSB trigger pattern value and mask in the patch#10. dsb_trig_patt/ \- xpr0 ... xpr15 -> (RW) Set/Get the value \- xpmr0 ... xpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 14. Use the following sysfs nodes to read/set DSB pattern value and mask in the patch#11. dsb_patt/ \- tpr0 ... tpr15 -> (RW) Set/Get the value \- tpmr0 ... tpmr7 -> (RW) Set/Get the mask -- Suzuki K Poulose 15. Add "Acked-by" tag to the patch#12. -- Rob Herring 16. Use the following sysfs nodes to read/set DSB MSR in the patch#13. dsb_msr/ \- msr0 ... msr31 -> (RW) Set/Get the value -- Suzuki K Poulose 17. Create the maximal number of DSB MSR sysfs nodes if the TPDM supports DSB MSR. Write the values set by user space to the DSB MSR according to the number of MSR supported by the TPDM. -- Suzuki K Poulose Changes in V7: 1. Since the "One value" limitation on SysFs file usage, add the nodes to read/write the index number for configuring the DSB TPDM. The following index number nodes are added. "dsb_edge_ctrl_idx" in the patch #9 "dsb_trig_patt_idx" in the patch #10 "dsb_patt_idx" in the patch #11 "dsb_msr_idx" in the patch #13 -- Suzuki K Poulose Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode coresight-tpdm: Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../testing/sysfs-bus-coresight-devices-tpdm | 159 ++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 3 + drivers/hwtracing/coresight/coresight-tpda.c | 126 ++- drivers/hwtracing/coresight/coresight-tpda.h | 2 + drivers/hwtracing/coresight/coresight-tpdm.c | 718 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 161 ++++ include/linux/coresight.h | 1 + 8 files changed, 1168 insertions(+), 22 deletions(-) -- 2.17.1

2 years

Re: [PATCH v2 7/7] perf pmu: Lazily compute default config

by Leo Yan

On Thu, Oct 12, 2023 at 10:56:45AM -0700, Ian Rogers wrote: > The default config is computed during creation of the PMU and may do > things like scanning sysfs, when the PMU may just be used as part of > scanning. Change default_config to perf_event_attr_init_default, a > callback that is used when a default config needs initializing. This > avoids holding onto the memory for a perf_event_attr and copying. > > On a tigerlake laptop running the pmu-scan benchmark: > > Before: > Running 'internals/pmu-scan' benchmark: > Computing performance of sysfs PMU event scan for 100 times > Average core PMU scanning took: 28.780 usec (+- 0.503 usec) > Average PMU scanning took: 283.480 usec (+- 18.471 usec) > Number of openat syscalls: 30,227 > > After: > Running 'internals/pmu-scan' benchmark: > Computing performance of sysfs PMU event scan for 100 times > Average core PMU scanning took: 27.880 usec (+- 0.169 usec) > Average PMU scanning took: 245.260 usec (+- 15.758 usec) > Number of openat syscalls: 28,914 > > Over 3 runs it is a nearly 12% reduction in execution time and a 4.3% > of openat calls. > > Signed-off-by: Ian Rogers <irogers(a)google.com> > Reviewed-by: Adrian Hunter <adrian.hunter(a)intel.com> > --- > tools/perf/arch/arm/util/cs-etm.c | 13 ++------ > tools/perf/arch/arm/util/pmu.c | 4 +-- > tools/perf/arch/arm64/util/arm-spe.c | 45 ++++++++++++++-------------- > tools/perf/arch/x86/util/intel-pt.c | 25 ++++++++-------- > tools/perf/arch/x86/util/pmu.c | 2 +- > tools/perf/util/arm-spe.h | 4 ++- > tools/perf/util/cs-etm.h | 2 +- > tools/perf/util/intel-pt.h | 3 +- > tools/perf/util/parse-events.c | 12 ++++---- > tools/perf/util/pmu.c | 3 +- > tools/perf/util/pmu.h | 7 +++-- > 11 files changed, 58 insertions(+), 62 deletions(-) > > diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c > index b8d6a953fd74..16bba74f048b 100644 > --- a/tools/perf/arch/arm/util/cs-etm.c > +++ b/tools/perf/arch/arm/util/cs-etm.c > @@ -917,16 +917,9 @@ struct auxtrace_record *cs_etm_record_init(int *err) > * (CFG_CHG and evsel__set_config_if_unset()). If no default is set then user > * changes aren't tracked. > */ > -struct perf_event_attr * > -cs_etm_get_default_config(struct perf_pmu *pmu __maybe_unused) > +void > +cs_etm_get_default_config(const struct perf_pmu *pmu __maybe_unused, > + struct perf_event_attr *attr) > { > - struct perf_event_attr *attr; > - > - attr = zalloc(sizeof(struct perf_event_attr)); > - if (!attr) > - return NULL; > - > attr->sample_period = 1; > - > - return attr; > } > diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c > index f25f68f84a94..7f3af3b97f3b 100644 > --- a/tools/perf/arch/arm/util/pmu.c > +++ b/tools/perf/arch/arm/util/pmu.c > @@ -20,12 +20,12 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) > if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { > /* add ETM default config here */ > pmu->selectable = true; > - pmu->default_config = cs_etm_get_default_config(pmu); > + pmu->perf_event_attr_init_default = cs_etm_get_default_config; > #if defined(__aarch64__) > } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { > pmu->selectable = true; > pmu->is_uncore = false; > - pmu->default_config = arm_spe_pmu_default_config(pmu); > + pmu->perf_event_attr_init_default = arm_spe_pmu_default_config; > } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { > pmu->selectable = true; > #endif > diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c > index 08a76734ccd2..e3acc739bd00 100644 > --- a/tools/perf/arch/arm64/util/arm-spe.c > +++ b/tools/perf/arch/arm64/util/arm-spe.c > @@ -113,6 +113,25 @@ arm_spe_snapshot_resolve_auxtrace_defaults(struct record_opts *opts, > } > } > > +static __u64 arm_spe_pmu__sample_period(const struct perf_pmu *arm_spe_pmu) > +{ > + static __u64 sample_period; > + > + if (sample_period) > + return sample_period; I would like to drop the static 'sample_period' optimization. IIUC, it's possible for some platforms to create more than one arm_spe events (e.g. Arm big.LITTLE system), in that case, it's incorrect to use the single sample period for all of arm_spe events. Otherwise, Arm SPE changes are good for me. Thanks, Leo > + > + /* > + * If kernel driver doesn't advertise a minimum, > + * use max allowable by PMSIDR_EL1.INTERVAL > + */ > + if (perf_pmu__scan_file(arm_spe_pmu, "caps/min_interval", "%llu", > + &sample_period) != 1) { > + pr_debug("arm_spe driver doesn't advertise a min. interval. Using 4096\n"); > + sample_period = 4096; > + } > + return sample_period; > +} > + > static int arm_spe_recording_options(struct auxtrace_record *itr, > struct evlist *evlist, > struct record_opts *opts) > @@ -136,7 +155,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, > return -EINVAL; > } > evsel->core.attr.freq = 0; > - evsel->core.attr.sample_period = arm_spe_pmu->default_config->sample_period; > + evsel->core.attr.sample_period = arm_spe_pmu__sample_period(arm_spe_pmu); > evsel->needs_auxtrace_mmap = true; > arm_spe_evsel = evsel; > opts->full_auxtrace = true; > @@ -495,26 +514,8 @@ struct auxtrace_record *arm_spe_recording_init(int *err, > return &sper->itr; > } > > -struct perf_event_attr > -*arm_spe_pmu_default_config(struct perf_pmu *arm_spe_pmu) > +void > +arm_spe_pmu_default_config(const struct perf_pmu *arm_spe_pmu, struct perf_event_attr *attr) > { > - struct perf_event_attr *attr; > - > - attr = zalloc(sizeof(struct perf_event_attr)); > - if (!attr) { > - pr_err("arm_spe default config cannot allocate a perf_event_attr\n"); > - return NULL; > - } > - > - /* > - * If kernel driver doesn't advertise a minimum, > - * use max allowable by PMSIDR_EL1.INTERVAL > - */ > - if (perf_pmu__scan_file(arm_spe_pmu, "caps/min_interval", "%llu", > - &attr->sample_period) != 1) { > - pr_debug("arm_spe driver doesn't advertise a min. interval. Using 4096\n"); > - attr->sample_period = 4096; > - } > - > - return attr; > + attr->sample_period = arm_spe_pmu__sample_period(arm_spe_pmu); > } > diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c > index 6d6cd8f9133c..fa0c718b9e72 100644 > --- a/tools/perf/arch/x86/util/intel-pt.c > +++ b/tools/perf/arch/x86/util/intel-pt.c > @@ -60,7 +60,7 @@ struct intel_pt_recording { > size_t priv_size; > }; > > -static int intel_pt_parse_terms_with_default(struct perf_pmu *pmu, > +static int intel_pt_parse_terms_with_default(const struct perf_pmu *pmu, > const char *str, > u64 *config) > { > @@ -84,7 +84,7 @@ static int intel_pt_parse_terms_with_default(struct perf_pmu *pmu, > return err; > } > > -static int intel_pt_parse_terms(struct perf_pmu *pmu, const char *str, u64 *config) > +static int intel_pt_parse_terms(const struct perf_pmu *pmu, const char *str, u64 *config) > { > *config = 0; > return intel_pt_parse_terms_with_default(pmu, str, config); > @@ -177,7 +177,7 @@ static int intel_pt_pick_bit(int bits, int target) > return pick; > } > > -static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu) > +static u64 intel_pt_default_config(const struct perf_pmu *intel_pt_pmu) > { > char buf[256]; > int mtc, mtc_periods = 0, mtc_period; > @@ -256,18 +256,17 @@ static int intel_pt_parse_snapshot_options(struct auxtrace_record *itr, > return 0; > } > > -struct perf_event_attr * > -intel_pt_pmu_default_config(struct perf_pmu *intel_pt_pmu) > +void intel_pt_pmu_default_config(const struct perf_pmu *intel_pt_pmu, > + struct perf_event_attr *attr) > { > - struct perf_event_attr *attr; > + static u64 config; > + static bool initialized; > > - attr = zalloc(sizeof(struct perf_event_attr)); > - if (!attr) > - return NULL; > - > - attr->config = intel_pt_default_config(intel_pt_pmu); > - > - return attr; > + if (!initialized) { > + config = intel_pt_default_config(intel_pt_pmu); > + initialized = true; > + } > + attr->config = config; > } > > static const char *intel_pt_find_filter(struct evlist *evlist, > diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c > index 949b3e2c67bd..469555ae9b3c 100644 > --- a/tools/perf/arch/x86/util/pmu.c > +++ b/tools/perf/arch/x86/util/pmu.c > @@ -23,7 +23,7 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) > if (!strcmp(pmu->name, INTEL_PT_PMU_NAME)) { > pmu->auxtrace = true; > pmu->selectable = true; > - pmu->default_config = intel_pt_pmu_default_config(pmu); > + pmu->perf_event_attr_init_default = intel_pt_pmu_default_config; > } > if (!strcmp(pmu->name, INTEL_BTS_PMU_NAME)) { > pmu->auxtrace = true; > diff --git a/tools/perf/util/arm-spe.h b/tools/perf/util/arm-spe.h > index 98d3235781c3..4f4900c18f3e 100644 > --- a/tools/perf/util/arm-spe.h > +++ b/tools/perf/util/arm-spe.h > @@ -27,5 +27,7 @@ struct auxtrace_record *arm_spe_recording_init(int *err, > int arm_spe_process_auxtrace_info(union perf_event *event, > struct perf_session *session); > > -struct perf_event_attr *arm_spe_pmu_default_config(struct perf_pmu *arm_spe_pmu); > +void arm_spe_pmu_default_config(const struct perf_pmu *arm_spe_pmu, > + struct perf_event_attr *attr); > + > #endif > diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h > index 7cca37887917..4696267a32f0 100644 > --- a/tools/perf/util/cs-etm.h > +++ b/tools/perf/util/cs-etm.h > @@ -242,7 +242,7 @@ struct cs_etm_packet_queue { > > int cs_etm__process_auxtrace_info(union perf_event *event, > struct perf_session *session); > -struct perf_event_attr *cs_etm_get_default_config(struct perf_pmu *pmu); > +void cs_etm_get_default_config(const struct perf_pmu *pmu, struct perf_event_attr *attr); > > enum cs_etm_pid_fmt { > CS_ETM_PIDFMT_NONE, > diff --git a/tools/perf/util/intel-pt.h b/tools/perf/util/intel-pt.h > index c7d6068e3a6b..18fd0be52e6c 100644 > --- a/tools/perf/util/intel-pt.h > +++ b/tools/perf/util/intel-pt.h > @@ -42,6 +42,7 @@ struct auxtrace_record *intel_pt_recording_init(int *err); > int intel_pt_process_auxtrace_info(union perf_event *event, > struct perf_session *session); > > -struct perf_event_attr *intel_pt_pmu_default_config(struct perf_pmu *pmu); > +void intel_pt_pmu_default_config(const struct perf_pmu *intel_pt_pmu, > + struct perf_event_attr *attr); > > #endif > diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c > index c56e07bd7dd6..ea5579510b97 100644 > --- a/tools/perf/util/parse-events.c > +++ b/tools/perf/util/parse-events.c > @@ -1418,11 +1418,10 @@ int parse_events_add_pmu(struct parse_events_state *parse_state, > } > fix_raw(&parsed_terms, pmu); > > - if (pmu->default_config) { > - memcpy(&attr, pmu->default_config, sizeof(struct perf_event_attr)); > - } else { > - memset(&attr, 0, sizeof(attr)); > - } > + memset(&attr, 0, sizeof(attr)); > + if (pmu->perf_event_attr_init_default) > + pmu->perf_event_attr_init_default(pmu, &attr); > + > attr.type = pmu->type; > > if (list_empty(&parsed_terms.terms)) { > @@ -1466,7 +1465,8 @@ int parse_events_add_pmu(struct parse_events_state *parse_state, > * When using default config, record which bits of attr->config were > * changed by the user. > */ > - if (pmu->default_config && get_config_chgs(pmu, &parsed_terms, &config_terms)) { > + if (pmu->perf_event_attr_init_default && > + get_config_chgs(pmu, &parsed_terms, &config_terms)) { > parse_events_terms__exit(&parsed_terms); > return -ENOMEM; > } > diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c > index 8ef675ea7bdd..a967d25e899b 100644 > --- a/tools/perf/util/pmu.c > +++ b/tools/perf/util/pmu.c > @@ -1402,7 +1402,7 @@ int perf_pmu__config(struct perf_pmu *pmu, struct perf_event_attr *attr, > struct parse_events_terms *head_terms, > struct parse_events_error *err) > { > - bool zero = !!pmu->default_config; > + bool zero = !!pmu->perf_event_attr_init_default; > > return perf_pmu__config_terms(pmu, attr, head_terms, zero, err); > } > @@ -2064,7 +2064,6 @@ void perf_pmu__delete(struct perf_pmu *pmu) > > perf_cpu_map__put(pmu->cpus); > > - zfree(&pmu->default_config); > zfree(&pmu->name); > zfree(&pmu->alias_name); > zfree(&pmu->id); > diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h > index 5a05131aa4ce..d2895d415f08 100644 > --- a/tools/perf/util/pmu.h > +++ b/tools/perf/util/pmu.h > @@ -92,10 +92,11 @@ struct perf_pmu { > */ > int max_precise; > /** > - * @default_config: Optional default perf_event_attr determined in > - * architecture specific code. > + * @perf_event_attr_init_default: Optional function to default > + * initialize PMU specific parts of the perf_event_attr. > */ > - struct perf_event_attr *default_config; > + void (*perf_event_attr_init_default)(const struct perf_pmu *pmu, > + struct perf_event_attr *attr); > /** > * @cpus: Empty or the contents of either of: > * <sysfs>/bus/event_source/devices/<name>/cpumask. > -- > 2.42.0.655.g421f12c284-goog >

2 years

Re: [PATCH v2 3/7] perf arm-spe: Move PMU initialization from default config code

by Leo Yan

On Thu, Oct 12, 2023 at 10:56:41AM -0700, Ian Rogers wrote: > Avoid setting PMU values in arm_spe_pmu_default_config, move to > perf_pmu__arch_init. > > Signed-off-by: Ian Rogers <irogers(a)google.com> > Reviewed-by: Adrian Hunter <adrian.hunter(a)intel.com> > --- > tools/perf/arch/arm/util/pmu.c | 2 ++ > tools/perf/arch/arm64/util/arm-spe.c | 3 --- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c > index d55d2b15f2e6..f25f68f84a94 100644 > --- a/tools/perf/arch/arm/util/pmu.c > +++ b/tools/perf/arch/arm/util/pmu.c > @@ -23,6 +23,8 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) > pmu->default_config = cs_etm_get_default_config(pmu); > #if defined(__aarch64__) > } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { > + pmu->selectable = true; > + pmu->is_uncore = false; Arm SPE is not an uncore PMU event. Arm SPE driver registers sysfs node 'cpumask', thus it misleads the pmu_is_uncore() function and it returns 'true' for Arm SPE event. Here we need to explictly set false to correct the 'is_uncore' flag. I did test on my machine, the changes work well for Arm SPE event. Tested-by: Leo Yan <leo.yan(a)linaro.org>

2 years

[PATCH v1 RESEND 0/2] perf cs-etm: Improve timestamp tracing

by Leo Yan

This patch series is to improve timestamp handling in per-thread mode. The current code doesn't validate timestamp and always return success for per-thread mode, for a sane implementation, the first patch is to allow validation timestamp tracing in per-thread mode. The second patch is to respect timestamp option "--timestamp" or "-T", when users set this option, the tool will automatically enable hardware timestamp tracing in Arm CoreSight. This patch set is rebased on the latest perf-tools-next branch, and tested on Arm Juno board. And added James Clark's review tags. Leo Yan (2): perf cs-etm: Validate timestamp tracing in per-thread mode perf cs-etm: Respect timestamp option tools/perf/arch/arm/util/cs-etm.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) -- 2.34.1

2 years

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