On Tue, Sep 03, 2019 at 10:17:51AM +0100, Mike Leach wrote:
Hi Leo,
On Tue, 3 Sep 2019 at 09:06, Leo Yan leo.yan@linaro.org wrote:
Hi Mike,
On Mon, Aug 19, 2019 at 10:13:46PM +0100, Mike Leach wrote:
CTIs are defined in the device tree and associated with other CoreSight devices. The core CoreSight code has been modified to enable the registration of the CTI devices on the same bus as the other CoreSight components, but as these are not actually trace generation / capture devices, they are not part of the Coresight path when generating trace.
However, the definition of the standard CoreSight device has been extended to include a reference to an associated CTI device, and the enable / disable trace path operations will auto enable/disable any associated CTI devices at the same time.
Programming is at present via sysfs - a full API is provided to utilise the hardware capabilities. As CTI devices are unprogrammed by default, the auto enable describe above will have no effect until explicit programming takes place.
A set of device tree bindings specific to the CTI topology has been defined. The driver accesses these in a platform agnostic manner, so ACPI bindings can be added later, once they have been agreed and defined for the CTI device.
Documentation has been updated to describe both the CTI hardware, its use and programming in sysfs, and the new dts bindings required.
Tested on DB410 board, applies on coresight/next tree - 5.3-rc1 based.
I tested this patch set on my Hikey620 board with below commands (and also applied below patch for CTI DT binding); I can confirm below testing can work well on Hikey board; FWIW:
Tested-by: Leo Yan leo.yan@linaro.org
Thanks for testing this. I'll add your binding patch into the next set.
Mike
Testing commands:
.../cti_cpu0# echo 1 > enable .../cti_cpu0/channels# echo 0 4 > trigout_attach .../cti_sys0/channels# echo 0 > show_chan_sel .../cti_cpu0/channels# cat show_chan_xtrigs IN: OUT: 4 .../cti_cpu0/regs# echo 4 > inout_sel .../cti_cpu0/regs# echo 1 > outen .../cti_cpu0/channels# echo 0 > chan_set .../cti_cpu0/regs# cat trigoutstatus 0x10
---8<---
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 651771a73ed6..806f0526f18f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -213,7 +213,7 @@ }; };
etm@f659c000 {
etm0: etm@f659c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659c000 0 0x1000>;@@ -232,7 +232,7 @@ }; };
etm@f659d000 {
etm1: etm@f659d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659d000 0 0x1000>;@@ -251,7 +251,7 @@ }; };
etm@f659e000 {
etm2: etm@f659e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659e000 0 0x1000>;@@ -270,7 +270,7 @@ }; };
etm@f659f000 {
etm3: etm@f659f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659f000 0 0x1000>;@@ -289,7 +289,7 @@ }; };
etm@f65dc000 {
etm4: etm@f65dc000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dc000 0 0x1000>;@@ -308,7 +308,7 @@
}; };
etm@f65dd000 {
etm5: etm@f65dd000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dd000 0 0x1000>;@@ -327,7 +327,7 @@ }; };
etm@f65de000 {
etm6: etm@f65de000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65de000 0 0x1000>;@@ -346,7 +346,7 @@ }; };
etm@f65df000 {
etm7: etm@f65df000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65df000 0 0x1000>;@@ -364,5 +364,119 @@ }; }; };
/* System CTIs *//* CTI 0 - TMC and TPIU connections */cti@f6403000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf6403000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";};/* CTI - CPU-0 */cti@f6598000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf6598000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu0>;arm,cs-dev-assoc = <&etm0>;};/* CTI - CPU-1 */cti@f6599000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf6599000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu1>;arm,cs-dev-assoc = <&etm1>;};/* CTI - CPU-2 */cti@f659a000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf659a000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu2>;arm,cs-dev-assoc = <&etm2>;};/* CTI - CPU-3 */cti@f659b000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf659b000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu3>;arm,cs-dev-assoc = <&etm3>;};/* CTI - CPU-4 */cti@f65d8000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf65d8000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu4>;arm,cs-dev-assoc = <&etm4>;};/* CTI - CPU-5 */cti@f65d9000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf65d9000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu5>;arm,cs-dev-assoc = <&etm5>;};/* CTI - CPU-6 */cti@f65da000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf65da000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu6>;arm,cs-dev-assoc = <&etm6>;};/* CTI - CPU-7 */cti@f65db000 {compatible = "arm,coresight-cti", "arm,primecell";reg = <0 0xf65db000 0 0x1000>;clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;clock-names = "apb_pclk";arm,cti-v8-arch;cpu = <&cpu7>;arm,cs-dev-assoc = <&etm7>;};
For the hikey620 DT bindings:
Reviewed-by: Mathieu Poirier mathieu.poirier@linaro.org
};};
-- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK