This is a no-op change for style and consistency and has no effect on the binary produced by gcc-11.
Signed-off-by: James Clark james.clark@arm.com --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++------------ drivers/hwtracing/coresight/coresight-etm4x.h | 11 +++++++++++ 2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 78f01c9e45cb..afb1b39e3a38 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1183,26 +1183,20 @@ static void etm4_init_arch_data(void *info)
etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ - drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); + drvdata->nr_ext_inp = REG_VAL(etmidr5, TRCIDR5_NUMEXTIN); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ - drvdata->trcid_size = BMVAL(etmidr5, 16, 21); + drvdata->trcid_size = REG_VAL(etmidr5, TRCIDR5_TRACEIDSIZE); /* ATBTRIG, bit[22] implementation can support ATB triggers? */ - if (BMVAL(etmidr5, 22, 22)) - drvdata->atbtrig = true; - else - drvdata->atbtrig = false; + drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); /* * LPOVERRIDE, bit[23] implementation supports * low-power state override */ - if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up)) - drvdata->lpoverride = true; - else - drvdata->lpoverride = false; + drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ - drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); + drvdata->nrseqstate = REG_VAL(etmidr5, TRCIDR5_NUMSEQSTATE); /* NUMCNTR, bits[30:28] number of counters available for tracing */ - drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); + drvdata->nr_cntr = REG_VAL(etmidr5, TRCIDR5_NUMCNTR); etm4_cs_lock(drvdata, csa); cpu_detect_trace_filtering(drvdata); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 0b22c57a9da1..ca6ed39ceaf7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -183,6 +183,17 @@ #define TRCIDR4_NUMVMIDC_SHIFT 28 #define TRCIDR4_NUMVMIDC_MASK GENMASK(3, 0)
+#define TRCIDR5_NUMEXTIN_SHIFT 0 +#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) +#define TRCIDR5_TRACEIDSIZE_SHIFT 16 +#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(5, 0) +#define TRCIDR5_ATBTRIG BIT(22) +#define TRCIDR5_LPOVERRIDE BIT(23) +#define TRCIDR5_NUMSEQSTATE_SHIFT 25 +#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(2, 0) +#define TRCIDR5_NUMCNTR_SHIFT 28 +#define TRCIDR5_NUMCNTR_MASK GENMASK(2, 0) + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions