Static replicators have no programmable registers and need no APB programming clock.
The Zynq clock controller registers dbg_trc and dbg_apb and calls clk_prepare_enable() for each gate the bootloader left on. This does not depend on the CoreSight nodes' clock references, so removing the unused consumer entries leaves this protection intact.
Keep atclk optional for SoCs that need to control the trace datapath. The unchanged driver still accepts legacy firmware that supplies apb_pclk, atclk, or both by name.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- .../bindings/arm/arm,coresight-static-replicator.yaml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml index b81851b26c7495047333b0ee0b5e690c0b153a61..e5596f6d0ce0f28429630f7344507ce49db59e68 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -31,17 +31,10 @@ properties: maxItems: 1
clocks: - minItems: 1 - maxItems: 3 + maxItems: 1
clock-names: - oneOf: - - items: - - enum: [apb_pclk, atclk] - - items: # Zynq-700 - - const: apb_pclk - - const: dbg_trc - - const: dbg_apb + const: atclk
label: description: