This series documents optional atclk for static CoreSight links and removes unused clock references from several device trees. It also describes the programmable Zynq-7000 funnel as dynamic.
Signed-off-by: Leo Yan leo.yan@arm.com --- Leo Yan (5): dt-bindings: arm: coresight: Limit static replicator to atclk dt-bindings: arm: coresight: Allow atclk for static funnel arm64: dts: hisilicon: Drop PCLK from static CoreSight links ARM: dts: zynq: Use dynamic CoreSight funnel and trim clocks ARM: dts: qcom: apq8064: Drop PCLK from static replicator
.../bindings/arm/arm,coresight-static-funnel.yaml | 6 ++++++ .../arm/arm,coresight-static-replicator.yaml | 11 ++-------- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 3 --- arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 24 ++++++++++------------ .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 4 ---- .../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 -- 6 files changed, 19 insertions(+), 31 deletions(-) --- base-commit: 551c722f40809618230001baccf219193e22fc5a change-id: 20261001-arm_coresight_hi3660_remove_dynamic_funnel_clocks-d277556abe8d
Best regards,
Static replicators have no programmable registers and need no APB programming clock.
The Zynq clock controller registers dbg_trc and dbg_apb and calls clk_prepare_enable() for each gate the bootloader left on. This does not depend on the CoreSight nodes' clock references, so removing the unused consumer entries leaves this protection intact.
Keep atclk optional for SoCs that need to control the trace datapath. The unchanged driver still accepts legacy firmware that supplies apb_pclk, atclk, or both by name.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- .../bindings/arm/arm,coresight-static-replicator.yaml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml index b81851b26c7495047333b0ee0b5e690c0b153a61..e5596f6d0ce0f28429630f7344507ce49db59e68 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml @@ -31,17 +31,10 @@ properties: maxItems: 1
clocks: - minItems: 1 - maxItems: 3 + maxItems: 1
clock-names: - oneOf: - - items: - - enum: [apb_pclk, atclk] - - items: # Zynq-700 - - const: apb_pclk - - const: dbg_trc - - const: dbg_apb + const: atclk
label: description:
Static funnels have no programmable registers and need no APB programming clock. They can still require a trace clock for the ATB datapath.
Document an optional atclk input. The CoreSight funnel driver already enables it when present.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- .../devicetree/bindings/arm/arm,coresight-static-funnel.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml index 9598a3d0a95b20e6272d4d72329a081101cca524..f502dc1a462d85e9cb6dfafc603a40360fa0fb41 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml @@ -30,6 +30,12 @@ properties: power-domains: maxItems: 1
+ clocks: + maxItems: 1 + + clock-names: + const: atclk + label: description: Description of a coresight device.
The static links don't need to program registers, therefore apb_pclk reference is unnecessary, remove the pclk properties from those nodes.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 4 ---- arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 -- 2 files changed, 6 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index 4c6a075908d1f8e3b9bba7cf9f0a2220819ea188..629b412d1b9fcc060f1eff9517652d3ddb7db441 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -306,8 +306,6 @@ cluster1_etf_out: endpoint { /* An invisible combo funnel between clusters and top funnel */ funnel { compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk";
out-ports { port { @@ -397,8 +395,6 @@ top_etf_out: endpoint {
replicator { compatible = "arm,coresight-static-replicator"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk";
in-ports { port { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 3f387f4cf5e02386cd130da877a62f395173c806..df449c53fb98cbdc11454cea7deabaea6177c68e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -62,8 +62,6 @@ etf_out: endpoint {
replicator { compatible = "arm,coresight-static-replicator"; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk";
in-ports { port {
The Zynq-7000 funnel at 0xf8804000 has input-enable registers. Describe it as a dynamic funnel so the CoreSight driver programs them. Keep the existing apb_pclk reference required by AMBA probing.
The static replicator has no programming registers, so remove its clock references. CoreSight drivers do not request dbg_trc or dbg_apb for the funnel, ETB, TPIU or PTMs. Drop those references while keeping apb_pclk for the programmable AMBA devices.
The Zynq clock controller registers dbg_trc and dbg_apb and calls clk_prepare_enable() for each gate the bootloader left on (see zynq_clk_setup()). This does not depend on the CoreSight nodes' clock references, so removing the unused consumer entries leaves this protection intact.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi index 153b8d93cbee2c30b399c0770f2022b307fe0808..4280fe6da379064b6ac5bf9e9a5b891830a094b2 100644 --- a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -68,8 +68,6 @@ regulator_vccpint: fixedregulator {
replicator { compatible = "arm,coresight-static-replicator"; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
out-ports { #address-cells = <1>; @@ -464,8 +462,8 @@ watchdog0: watchdog@f8005000 { etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; in-ports { port { etb_in_port: endpoint { @@ -478,8 +476,8 @@ etb_in_port: endpoint { tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; in-ports { port { tpiu_in_port: endpoint { @@ -490,10 +488,10 @@ tpiu_in_port: endpoint { };
funnel@f8804000 { - compatible = "arm,coresight-static-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + clocks = <&clkc 27>; + clock-names = "apb_pclk";
/* funnel output ports */ out-ports { @@ -536,8 +534,8 @@ funnel0_in_port2: endpoint { ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; cpu = <&cpu0>; out-ports { port { @@ -551,8 +549,8 @@ ptm0_out_port: endpoint { ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; - clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; - clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + clocks = <&clkc 27>; + clock-names = "apb_pclk"; cpu = <&cpu1>; out-ports { port {
The APQ8064 static replicator has no registers to program, so it does not need an APB clock. Remove its RPM_QDSS_CLK reference. Other programmable CoreSight devices keep their clock references.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 09062b2ad8ba550c3c2ee5849c96fb68fa2dff4b..d3ae9b835b9f45ce0bf66c850006a6ab149a183e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -281,9 +281,6 @@ scm { replicator { compatible = "arm,coresight-static-replicator";
- clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - in-ports { port { replicator_in: endpoint {
-
Leo Yan