The static links don't need to program registers, therefore apb_pclk reference is unnecessary, remove the pclk properties from those nodes.
Assisted-by: Codex:gpt-6 Signed-off-by: Leo Yan leo.yan@arm.com --- arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 4 ---- arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 2 -- 2 files changed, 6 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi index 4c6a075908d1f8e3b9bba7cf9f0a2220819ea188..629b412d1b9fcc060f1eff9517652d3ddb7db441 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -306,8 +306,6 @@ cluster1_etf_out: endpoint { /* An invisible combo funnel between clusters and top funnel */ funnel { compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk";
out-ports { port { @@ -397,8 +395,6 @@ top_etf_out: endpoint {
replicator { compatible = "arm,coresight-static-replicator"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk";
in-ports { port { diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi index 3f387f4cf5e02386cd130da877a62f395173c806..df449c53fb98cbdc11454cea7deabaea6177c68e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi @@ -62,8 +62,6 @@ etf_out: endpoint {
replicator { compatible = "arm,coresight-static-replicator"; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk";
in-ports { port {