On Thu, Jan 29, 2015 at 09:00:11PM +0530, Sumit Semwal wrote:

So, short answer is, it is left to the exporter to decide. The dma-buf framework should not even attempt to decide or enforce any of the above.

At each dma_buf_attach(), there's a callback to the exporter, where the exporter can decide, if it intends to handle these kind of cases, on the best way forward.

The exporter might, for example, decide to migrate backing storage,

That's a decision which the exporter can not take. Think about it...

If subsystem Y has mapped the buffer, it could be accessing the buffer's backing storage at the same time that subsystem Z tries to attach to the buffer.

Once the buffer has been exported to another user, the exporter has effectively lost control over mediating accesses to that buffer.

All that it can do with the way the dma-buf API is today is to allocate a _different_ scatter list pointing at the same backing storage which satisfies the segment size and number of segments, etc.

There's also another issue which you haven't addressed. What if several attachments result in lowering max_segment_size and max_segment_count such that:

max_segment_size * max_segment_count < dmabuf->size

but individually, the attachments allow dmabuf->size to be represented as a scatterlist?

If an exporter were to take notice of the max_segment_size and max_segment_count, the resulting buffer is basically unrepresentable as a scatterlist.

...

Please consider the possible sequences of use (such as the scenario above) when creating or augmenting an API.

I tried to think of the scenarios I could think of, but If you still feel this approach doesn't help with your concerns, I'll graciously accept advice to improve it.

See the new one above :)

On Thu, Jan 29, 2015 at 10:47 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Thu, Jan 29, 2015 at 09:00:11PM +0530, Sumit Semwal wrote:

...

So, short answer is, it is left to the exporter to decide. The dma-buf framework should not even attempt to decide or enforce any of the above.

At each dma_buf_attach(), there's a callback to the exporter, where the exporter can decide, if it intends to handle these kind of cases, on the best way forward.

The exporter might, for example, decide to migrate backing storage,

That's a decision which the exporter can not take. Think about it...

If subsystem Y has mapped the buffer, it could be accessing the buffer's backing storage at the same time that subsystem Z tries to attach to the buffer.

The *theory* is that Y is map/unmap'ing the buffer around each use, so there will be some point where things could be migrated and remapped.. in practice, I am not sure that anyone is doing this yet.

Probably it would be reasonable if a more restrictive subsystem tried to attach after the buffer was already allocated and mapped in a way that don't meet the new constraints, then -EBUSY.

But from a quick look it seems like there needs to be a slight fixup to not return 0 if calc_constraints() fails..

Once the buffer has been exported to another user, the exporter has effectively lost control over mediating accesses to that buffer.

All that it can do with the way the dma-buf API is today is to allocate a _different_ scatter list pointing at the same backing storage which satisfies the segment size and number of segments, etc.

There's also another issue which you haven't addressed. What if several attachments result in lowering max_segment_size and max_segment_count such that:

    max_segment_size * max_segment_count < dmabuf->size

but individually, the attachments allow dmabuf->size to be represented as a scatterlist?

Quite possibly for some of these edge some of cases, some of the dma-buf exporters are going to need to get more clever (ie. hand off different scatterlists to different clients). Although I think by far the two common cases will be "I can support anything via an iommu/mmu" and "I need phys contig".

But that isn't an issue w/ dma-buf itself, so much as it is an issue w/ drivers. I guess there would be more interest in fixing up drivers when actual hw comes along that needs it..

BR, -R

If an exporter were to take notice of the max_segment_size and max_segment_count, the resulting buffer is basically unrepresentable as a scatterlist.

...

...

Please consider the possible sequences of use (such as the scenario above) when creating or augmenting an API.

I tried to think of the scenarios I could think of, but If you still feel this approach doesn't help with your concerns, I'll graciously accept advice to improve it.

See the new one above :)

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Thu, Jan 29, 2015 at 2:26 PM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Thu, Jan 29, 2015 at 01:52:09PM -0500, Rob Clark wrote:

...

Quite possibly for some of these edge some of cases, some of the dma-buf exporters are going to need to get more clever (ie. hand off different scatterlists to different clients). Although I think by far the two common cases will be "I can support anything via an iommu/mmu" and "I need phys contig".

But that isn't an issue w/ dma-buf itself, so much as it is an issue w/ drivers. I guess there would be more interest in fixing up drivers when actual hw comes along that needs it..

However, validating the attachments is the business of dma-buf. This is actual infrastructure, which should ensure some kind of sanity such as the issues I've raised.

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That all said, I think probably all the existing exporters cache the sg-list. And I can't think of any actual hw which would hit this problem that can be solved by multiple sg-lists for the same physical memory. (And the constraint calculation kind of assumes the end result will be a single sg-list.) So it seems reasonable to me to check that max_segment_count * max_segment_size is not smaller than the buffer.

If it was a less theoretical problem, I think I'd more inclined for a way that the exporter could override the checks, or something along those lines.

otoh, if the attachment is just not possible because the buffer has been already allocated and mapped by someone with more relaxed constraints.. then I think the driver should be the one returning the error since dma-buf doesn't know this.

The whole "we can push it onto our users" is really on - what that results in is the users ignoring most of the requirements and just doing their own thing, which ultimately ends up with the whole thing turning into a disgusting mess - one which becomes very difficult to fix later.

Ideally at some point, dma-mapping or some helpers would support allocations matching constraints.. I think only actual gpu drivers want to do crazy enough things that they'd want to bypass dma-mapping. If everyone else can use dma-mapping and/or helpers then we make it harder for drivers to do the wrong thing than to do the right thing.

Now, if we're going to do the "more clever" thing you mention above, that rather negates the point of this two-part patch set, which is to provide the union of the DMA capabilities of all users. A union in that case is no longer sane as we'd be tailoring the SG lists to each user.

It doesn't really negate.. a different sg list representing the same physical memory cannot suddenly make the buffer physically contiguous (from the perspective of memory)..

(unless we are not on the same page here, so to speak)

BR, -R

If we aren't going to do the "more clever" thing, then yes, we need this code to calculate that union, but we _also_ need it to do sanity checking right from the start, and refuse conditions which ultimately break the ability to make use of that union - in other words, when the union of the DMA capabilities means that the dmabuf can't be represented.

Unless we do that, we'll just end up with random drivers interpreting what they want from the DMA capabilities, and we'll have some drivers exporting (eg) scatterlists which satisfy the maximum byte size of an element, but ignoring the maximum number of entries or vice versa, and that'll most probably hide the case of "too small a union".

It really doesn't make sense to do both either: that route is even more madness, because we'll end up with two classes of drivers - those which use the union approach, and those which don't.

The KISS principle applies here.

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Thu, Jan 29, 2015 at 5:31 PM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Thu, Jan 29, 2015 at 05:18:33PM -0500, Rob Clark wrote:

...

On Thu, Jan 29, 2015 at 2:26 PM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

Now, if we're going to do the "more clever" thing you mention above, that rather negates the point of this two-part patch set, which is to provide the union of the DMA capabilities of all users. A union in that case is no longer sane as we'd be tailoring the SG lists to each user.

It doesn't really negate.. a different sg list representing the same physical memory cannot suddenly make the buffer physically contiguous (from the perspective of memory)..

(unless we are not on the same page here, so to speak)

If we are really only interested in the "physically contiguous" vs "scattered" differentiation, why can't this be just a simple flag?

I'd be fine with that.. I was trying to make it a bit less of a point solution, but maybe trying to be too generic is not worth it..

There is apparently some hw which has iommu's but small # of tlb entries, and would prefer partially contiguous buffers. But that isn't a hard constraint, and maybe shouldn't be solved w/ max_segment_count. And I'm not sure how common that is.

I think I know where you're coming from on that distinction - most GPUs can cope with their buffers being discontiguous in memory, but scanout and capture hardware tends to need contiguous buffers.

My guess is that you're looking for some way that a GPU driver could allocate a buffer, which can then be imported into the scanout hardware - and when it is, the underlying backing store is converted to a contiguous buffer. Is that the usage scenario you're thinking of?

Pretty much.. and maybe a few slight permutations on that involving cameras / video codecs / etc. But the really-really common case is gpu (with mmu/iommu) + display (without). Just solving this problem would be a really good first step.

BR, -R

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

BR, -R

On Mon, Feb 2, 2015 at 4:46 PM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

That's incorrect - and goes dead against the design of scatterlists.

yeah, a bit of an abuse, although I'm not sure I see a much better way when a device vaddr depends on user context..

Not only that, but it is entirely possible that you may get handed memory via dmabufs for which there are no struct page's associated with that memory - think about display systems which have their own video memory which is accessible to the GPU, but it isn't system memory.

well, I guess anyways when it comes to sharing buffers, it won't be the vram placement of the bo that gets shared ;-)

BR, -R

In those circumstances, you have to use the dma_addr_t's and not the pages.

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Mon, Feb 02, 2015 at 09:46:16PM +0000, Russell King - ARM Linux wrote:

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

That's incorrect - and goes dead against the design of scatterlists.

Not only that, but it is entirely possible that you may get handed memory via dmabufs for which there are no struct page's associated with that memory - think about display systems which have their own video memory which is accessible to the GPU, but it isn't system memory.

In those circumstances, you have to use the dma_addr_t's and not the pages.

Yeah exactly. At least with i915 we'd really want to be able to share stolen memory in some cases, and since that's stolen there's no struct pages for them. On top of that any cpu access is also blocked to that range in the memory controller, so the dma_addr_t is really the _only_ thing you can use to get at those memory ranges. And afaik the camera pipe on intel soc can get there - unfortunately that one doesn't have an upstream driver :(

And just to clarify: All current dma-buf exporter that I've seen implement the sg mapping correctly and _do_ map the sg table into device address space with dma_map_sg. In other words: The dma_addr_t are all valid, it's just that e.g. with ttm no one has bothered to teach ttm a dma-buf correctly. The internal abstraction is all there, ttm-internal buffer object interface match what dma-buf exposes fairly closes (hey I didn't do shit when designing those interfaces ;-) -Daniel

On Tue, Feb 03, 2015 at 08:48:56AM +0100, Daniel Vetter wrote:

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

Hm, what does per-process/context page tables have to do here? At least on i915 we have a two levels of page tables:

• first level for vm/device isolation, used through dma api
• 2nd level for per-gpu-context isolation and context switching, handled internally.

Since atm the dma api doesn't have any context of contexts or different pagetables, I don't see who you could use that at all.

What I've found with *my* etnaviv drm implementation (not Christian's - I found it impossible to work with Christian, especially with the endless "msm doesn't do it that way, so we shouldn't" responses and his attitude towards cherry-picking my development work [*]) is that it's much easier to keep the GPU MMU local to the GPU and under the control of the DRM MM code, rather than attaching the IOMMU to the DMA API and handling it that way.

There are several reasons for that:

1. DRM has a better idea about when the memory needs to be mapped to the GPU, and it can more effectively manage the GPU MMU.

2. The GPU MMU may have TLBs which can only be flushed via a command in the GPU command stream, so it's fundamentally necessary for the MMU to be managed by the GPU driver so that it knows when (and how) to insert the flushes.

* - as a direct result of that, I've stopped all further development of etnaviv drm, and I'm intending to strip it out from my Xorg DDX driver as the etnaviv drm API which Christian wants is completely incompatible with the non-etnaviv drm, and that just creates far too much pain in the DDX driver.

2015-02-03 13:28 GMT+01:00 Russell King - ARM Linux linux@arm.linux.org.uk:

On Tue, Feb 03, 2015 at 08:48:56AM +0100, Daniel Vetter wrote:

...

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

Hm, what does per-process/context page tables have to do here? At least on i915 we have a two levels of page tables:

• first level for vm/device isolation, used through dma api
• 2nd level for per-gpu-context isolation and context switching, handled internally.

Since atm the dma api doesn't have any context of contexts or different pagetables, I don't see who you could use that at all.

What I've found with *my* etnaviv drm implementation (not Christian's - I found it impossible to work with Christian, especially with the endless "msm doesn't do it that way, so we shouldn't" responses and his attitude towards cherry-picking my development work [*]) is that it's much easier to keep the GPU MMU local to the GPU and under the control of the DRM MM code, rather than attaching the IOMMU to the DMA API and handling it that way.

Keep in mind that I tried to reach you several times via mail and irc and you simply ignored me. Did you know that took almost all of your patches (with small changes)? And I needed to cherry pick you patches as they were a) wrong, b) solved in a different way or c) had "hack" in the subject. I am quite sorry that I ended that way, but it is not only my fault!

There are several reasons for that:

1. DRM has a better idea about when the memory needs to be mapped to the GPU, and it can more effectively manage the GPU MMU.

2. The GPU MMU may have TLBs which can only be flushed via a command in the GPU command stream, so it's fundamentally necessary for the MMU to be managed by the GPU driver so that it knows when (and how) to insert the flushes.

• • as a direct result of that, I've stopped all further development of

etnaviv drm, and I'm intending to strip it out from my Xorg DDX driver as the etnaviv drm API which Christian wants is completely incompatible with the non-etnaviv drm, and that just creates far too much pain in the DDX driver.

That is bad, but life moves on.

greets -- Christian Gmeiner, MSc

https://soundcloud.com/christian-gmeiner

On Tue, Feb 3, 2015 at 7:28 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Tue, Feb 03, 2015 at 08:48:56AM +0100, Daniel Vetter wrote:

...

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

Hm, what does per-process/context page tables have to do here? At least on i915 we have a two levels of page tables:

• first level for vm/device isolation, used through dma api
• 2nd level for per-gpu-context isolation and context switching, handled internally.

Since atm the dma api doesn't have any context of contexts or different pagetables, I don't see who you could use that at all.

What I've found with *my* etnaviv drm implementation (not Christian's - I found it impossible to work with Christian, especially with the endless "msm doesn't do it that way, so we shouldn't" responses and his attitude towards cherry-picking my development work [*]) is that it's much easier to keep the GPU MMU local to the GPU and under the control of the DRM MM code, rather than attaching the IOMMU to the DMA API and handling it that way.

There are several reasons for that:

1. DRM has a better idea about when the memory needs to be mapped to the GPU, and it can more effectively manage the GPU MMU.

2. The GPU MMU may have TLBs which can only be flushed via a command in the GPU command stream, so it's fundamentally necessary for the MMU to be managed by the GPU driver so that it knows when (and how) to insert the flushes.

If gpu mmu needs some/all updates to happen from command-stream then probably better to handle it internally..

That is a slightly different scenario from msm, where we have many instances of the same iommu[*] scattered through the SoC in front of various different devices.

BR, -R

[*] at least from iommu register layout, same driver is used for all instances.. but maybe the tlb+walker are maybe more tightly integrated to the gpu, but that is just speculation on implementation details based on some paper I found along the way

• • as a direct result of that, I've stopped all further development of

etnaviv drm, and I'm intending to strip it out from my Xorg DDX driver as the etnaviv drm API which Christian wants is completely incompatible with the non-etnaviv drm, and that just creates far too much pain in the DDX driver.

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Tuesday 03 February 2015 09:04:03 Rob Clark wrote:

On Tue, Feb 3, 2015 at 2:48 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

On Mon, Feb 02, 2015 at 03:30:21PM -0500, Rob Clark wrote:

...

On Mon, Feb 2, 2015 at 11:54 AM, Daniel Vetter daniel@ffwll.ch wrote:

...

...

My initial thought is for dma-buf to not try to prevent something than an exporter can actually do.. I think the scenario you describe could be handled by two sg-lists, if the exporter was clever enough.

That's already needed, each attachment has it's own sg-list. After all there's no array of dma_addr_t in the sg tables, so you can't use one sg for more than one mapping. And due to different iommu different devices can easily end up with different addresses.

Well, to be fair it may not be explicitly stated, but currently one should assume the dma_addr_t's in the dmabuf sglist are bogus. With gpu's that implement per-process/context page tables, I'm not really sure that there is a sane way to actually do anything else..

Hm, what does per-process/context page tables have to do here? At least on i915 we have a two levels of page tables:

• first level for vm/device isolation, used through dma api
• 2nd level for per-gpu-context isolation and context switching, handled internally.

Since atm the dma api doesn't have any context of contexts or different pagetables, I don't see who you could use that at all.

Since I'm stuck w/ an iommu, instead of built in mmu, my plan was to drop use of dma-mapping entirely (incl the current call to dma_map_sg, which I just need until we can use drm_cflush on arm), and attach/detach iommu domains directly to implement context switches. At that point, dma_addr_t really has no sensible meaning for me.

I think what you see here is a quite common hardware setup and we really lack the right abstraction for it at the moment. Everybody seems to work around it with a mix of the dma-mapping API and the iommu API. These are doing different things, and even though the dma-mapping API can be implemented on top of the iommu API, they are not really compatible.

The drm_clflush helpers don't seem like the right solution to me, because all other devices outside of drm will face the same issue, and I suspect we should fill the missing gaps in the API in a more generic way.

Arnd

On Tuesday 03 February 2015 14:41:09 Russell King - ARM Linux wrote:

On Tue, Feb 03, 2015 at 03:17:27PM +0100, Arnd Bergmann wrote:

...

On Tuesday 03 February 2015 09:04:03 Rob Clark wrote:

...

Since I'm stuck w/ an iommu, instead of built in mmu, my plan was to drop use of dma-mapping entirely (incl the current call to dma_map_sg, which I just need until we can use drm_cflush on arm), and attach/detach iommu domains directly to implement context switches. At that point, dma_addr_t really has no sensible meaning for me.

I think what you see here is a quite common hardware setup and we really lack the right abstraction for it at the moment. Everybody seems to work around it with a mix of the dma-mapping API and the iommu API. These are doing different things, and even though the dma-mapping API can be implemented on top of the iommu API, they are not really compatible.

I'd go as far as saying that the "DMA API on top of IOMMU" is more intended to be for a system IOMMU for the bus in question, rather than a device-level IOMMU.

If an IOMMU is part of a device, then the device should handle it (maybe via an abstraction) and not via the DMA API. The DMA API should be handing the bus addresses to the device driver which the device's IOMMU would need to generate. (In other words, in this circumstance, the DMA API shouldn't give you the device internal address.)

Exactly. And the abstraction that people choose at the moment is the iommu API, for better or worse. It makes a lot of sense to use this API if the same iommu is used for other devices as well (which is the case on Tegra and probably a lot of others). Unfortunately the iommu API lacks support for cache management, and probably other things as well, because this was not an issue for the original use case (device assignment on KVM/x86).

This could be done by adding explicit or implied cache management to the IOMMU mapping interfaces, or by extending the dma-mapping interfaces in a way that covers the use case of the device managing its own address space, in addition to the existing coherent and streaming interfaces.

Arnd

On Tuesday 03 February 2015 15:22:05 Russell King - ARM Linux wrote:

On Tue, Feb 03, 2015 at 03:52:48PM +0100, Arnd Bergmann wrote:

...

On Tuesday 03 February 2015 14:41:09 Russell King - ARM Linux wrote:

...

I'd go as far as saying that the "DMA API on top of IOMMU" is more intended to be for a system IOMMU for the bus in question, rather than a device-level IOMMU.

If an IOMMU is part of a device, then the device should handle it (maybe via an abstraction) and not via the DMA API. The DMA API should be handing the bus addresses to the device driver which the device's IOMMU would need to generate. (In other words, in this circumstance, the DMA API shouldn't give you the device internal address.)

Exactly. And the abstraction that people choose at the moment is the iommu API, for better or worse. It makes a lot of sense to use this API if the same iommu is used for other devices as well (which is the case on Tegra and probably a lot of others). Unfortunately the iommu API lacks support for cache management, and probably other things as well, because this was not an issue for the original use case (device assignment on KVM/x86).

This could be done by adding explicit or implied cache management to the IOMMU mapping interfaces, or by extending the dma-mapping interfaces in a way that covers the use case of the device managing its own address space, in addition to the existing coherent and streaming interfaces.

Don't we already have those in the DMA API? dma_sync_*() ?

dma_map_sg() - sets up the system MMU and deals with initial cache coherency handling. Device IOMMU being the responsibility of the GPU driver.

dma_sync_*() works with whatever comes out of dma_map_*(), true, but this is not what they want to do here.

The GPU can then do dma_sync_*() on the scatterlist as is necessary to synchronise the cache coherency (while respecting the ownership rules - which are very important on ARM to follow as some sync()s are destructive to any dirty data in the CPU cache.)

dma_unmap_sg() tears down the system MMU and deals with the final cache handling.

Why do we need more DMA API interfaces?

The dma_map_* interfaces assign the virtual addresses internally, using typically either a global address space for all devices, or one address space per device.

There are multiple things that this cannot do, and that is why the drivers use the iommu API directly:

- use one address space per 'struct mm' - map user memory with bus_address == user_address - map memory into the GPU without having a permanent kernel mapping - map memory first, and do the initial cache flushes later

Arnd

On Tuesday 03 February 2015 15:54:04 Russell King - ARM Linux wrote:

On Tue, Feb 03, 2015 at 04:31:13PM +0100, Arnd Bergmann wrote:

...

The dma_map_* interfaces assign the virtual addresses internally, using typically either a global address space for all devices, or one address space per device.

We shouldn't be doing one address space per device for precisely this reason. We should be doing one address space per *bus*. I did have a nice diagram to illustrate the point in my previous email, but I deleted it, I wish I hadn't... briefly:

Fig. 1. +------------------+ |+-----+ device | CPU--L1cache--L2cache--Memory--SysMMU---<iobus>----IOMMU--> | |+-----+ | +------------------+

Fig.1 represents what I'd call the "GPU" issue that we're talking about in this thread.

Fig. 2. CPU--L1cache--L2cache--Memory--SysMMU---<iobus>--IOMMU--device

The DMA API should be responsible (at the very least) for everything on the left of "<iobus>" in and should be providing a dma_addr_t which is representative of what the device (in Fig.1) as a whole sees. That's the "system" part.

I believe this is the approach which is taken by x86 and similar platforms, simply because they tend not to have an IOMMU on individual devices (and if they did, eg, on a PCI card, it's clearly the responsibility of the device driver.)

Whether the DMA API also handles the IOMMU in Fig.1 or 2 is questionable. For fig.2, it is entirely possible that the same device could appear without an IOMMU, and in that scenario, you would want the IOMMU to be handled transparently.

However, by doing so for everything, you run into exactly the problem which is being discussed here - the need to separate out the cache coherency from the IOMMU aspects. You probably also have a setup very similar to fig.1 (which is certainly true of Vivante GPUs.)

If you have the need to separately control both, then using the DMA API to encapsulate both does not make sense - at which point, the DMA API should be responsible for the minimum only - in other words, everything to the left of <iobus> (so including the system MMU.) The control of the device IOMMU should be the responsibility of device driver in this case.

So, dma_map_sg() would be responsible for dealing with the CPU cache coherency issues, and setting up the system MMU. dma_sync_*() would be responsible for the CPU cache coherency issues, and dma_unmap_sg() would (again) deal with the CPU cache and tear down the system MMU mappings.

Meanwhile, the device driver has ultimate control over its IOMMU, the creation and destruction of mappings and context switches at the appropriate times.

I agree for the case you are describing here. From what I understood from Rob was that he is looking at something more like:

Fig 3 CPU--L1cache--L2cache--Memory--IOMMU---<iobus>--device

where the IOMMU controls one or more contexts per device, and is shared across GPU and non-GPU devices. Here, we need to use the dmap-mapping interface to set up the IO page table for any device that is unable to address all of system RAM, and we can use it for purposes like isolation of the devices. There are also cases where using the IOMMU is not optional.

So unlike the scenario you describe, the driver cannot at the same time control the cache (using the dma-mapping API) and the I/O page tables (using the iommu API or some internal functions).

Arnd

On Tuesday 03 February 2015 11:22:01 Rob Clark wrote:

On Tue, Feb 3, 2015 at 11:12 AM, Arnd Bergmann arnd@arndb.de wrote:

...

I agree for the case you are describing here. From what I understood from Rob was that he is looking at something more like:

Fig 3 CPU--L1cache--L2cache--Memory--IOMMU---<iobus>--device

where the IOMMU controls one or more contexts per device, and is shared across GPU and non-GPU devices. Here, we need to use the dmap-mapping interface to set up the IO page table for any device that is unable to address all of system RAM, and we can use it for purposes like isolation of the devices. There are also cases where using the IOMMU is not optional.

Actually, just to clarify, the IOMMU instance is specific to the GPU.. not shared with other devices. Otherwise managing multiple contexts would go quite badly..

But other devices have their own instance of the same IOMMU.. so same driver could be used.

I think from the driver perspective, I'd view those two cases as identical. Not sure if Russell agrees with that.

Arnd

On Tuesday 03 February 2015 21:04:35 Daniel Vetter wrote:

• On many soc people love to reuse iommus with the same or similar interface all over the place. The solution thus far adopted on arm platforms is to write an iommu driver for those and then implement the dma-api on top of this iommu.

  But if we unconditionally do this then we rob the gpu driver's ability to control its private iommu like it wants to, because a lot of the functionality is lost behind the dma api abstraction.

I believe in case of rockchips, msm, exynos and tegra, the same iommu is used directly by the DRM driver while it is used implicitly by the dma-mapping API. We have run into some problems with this in 3.19, but they should be solvable.

Again assuming I'm not confused can't we just solve this by pushing the dma api abstraction down one layer for just the gpu, and let it use its private iommmu directly? Steps for binding a buffer would be:

1. dma_map_sg
2. Noodle the dma_addr_t out of the sg table and feed those into a 2nd

level mapping set up through the iommu api for the gpu-private mmu.

If you want to do that, you run into the problem of telling the driver core about it. We associate the device with an iommu in the device tree, describing there how it is wired up.

The driver core creates a platform_device for this and checks if it an iommu mapping is required or wanted for the device, which is then set up. When the device driver wants to create its own iommu mapping, this conflicts with the one that is already there. We can't just skip the iommu setup for all devices because it may be needed sometimes, and I don't really want to see hacks where the driver core knows which devices are GPUs and skips the mapping for them, which would be a layering violation.

Again, this is what i915 and all the ttm based drivers already do, except that we don't use the generic iommu interfaces but have our own (i915 has its interface in i915_gem_gtt.c, ttm just calls them tt for translation tables ...).

Right, if you have a private iommu, there is no problem. The tricky part is using a single driver for the system-level translation and the gpu private mappings when there is only one type of iommu in the system.

Arnd

On Tue, Feb 03, 2015 at 10:42:26PM +0100, Arnd Bergmann wrote:

Right, if you have a private iommu, there is no problem. The tricky part is using a single driver for the system-level translation and the gpu private mappings when there is only one type of iommu in the system.

You've got a problem anyway with this approach. If you look at my figure 2 and apply it to this scenario, you have two MMUs stacked on top of each other. That's something that (afaik) we don't support, but it's entirely possible that will come along with ARM64.

It may not be nice to have to treat GPUs specially, but I think we really do need to, and forget the idea that the GPU's IOMMU (as opposed to a system MMU) should appear in a generic form in DT.

On Tue, Feb 03, 2015 at 05:12:40PM +0100, Arnd Bergmann wrote:

On Tuesday 03 February 2015 15:54:04 Russell King - ARM Linux wrote:

...

On Tue, Feb 03, 2015 at 04:31:13PM +0100, Arnd Bergmann wrote:

...

The dma_map_* interfaces assign the virtual addresses internally, using typically either a global address space for all devices, or one address space per device.

We shouldn't be doing one address space per device for precisely this reason. We should be doing one address space per *bus*. I did have a nice diagram to illustrate the point in my previous email, but I deleted it, I wish I hadn't... briefly:

Fig. 1. +------------------+ |+-----+ device | CPU--L1cache--L2cache--Memory--SysMMU---<iobus>----IOMMU--> | |+-----+ | +------------------+

Fig.1 represents what I'd call the "GPU" issue that we're talking about in this thread.

Fig. 2. CPU--L1cache--L2cache--Memory--SysMMU---<iobus>--IOMMU--device

The DMA API should be responsible (at the very least) for everything on the left of "<iobus>" in and should be providing a dma_addr_t which is representative of what the device (in Fig.1) as a whole sees. That's the "system" part.

I believe this is the approach which is taken by x86 and similar platforms, simply because they tend not to have an IOMMU on individual devices (and if they did, eg, on a PCI card, it's clearly the responsibility of the device driver.)

Whether the DMA API also handles the IOMMU in Fig.1 or 2 is questionable. For fig.2, it is entirely possible that the same device could appear without an IOMMU, and in that scenario, you would want the IOMMU to be handled transparently.

However, by doing so for everything, you run into exactly the problem which is being discussed here - the need to separate out the cache coherency from the IOMMU aspects. You probably also have a setup very similar to fig.1 (which is certainly true of Vivante GPUs.)

If you have the need to separately control both, then using the DMA API to encapsulate both does not make sense - at which point, the DMA API should be responsible for the minimum only - in other words, everything to the left of <iobus> (so including the system MMU.) The control of the device IOMMU should be the responsibility of device driver in this case.

So, dma_map_sg() would be responsible for dealing with the CPU cache coherency issues, and setting up the system MMU. dma_sync_*() would be responsible for the CPU cache coherency issues, and dma_unmap_sg() would (again) deal with the CPU cache and tear down the system MMU mappings.

Meanwhile, the device driver has ultimate control over its IOMMU, the creation and destruction of mappings and context switches at the appropriate times.

I agree for the case you are describing here. From what I understood from Rob was that he is looking at something more like:

Fig 3 CPU--L1cache--L2cache--Memory--IOMMU---<iobus>--device

where the IOMMU controls one or more contexts per device, and is shared across GPU and non-GPU devices. Here, we need to use the dmap-mapping interface to set up the IO page table for any device that is unable to address all of system RAM, and we can use it for purposes like isolation of the devices. There are also cases where using the IOMMU is not optional.

Okay, but switching contexts is not something which the DMA API has any knowledge of (so it can't know which context to associate with which mapping.) While it knows which device, it has no knowledge (nor is there any way for it to gain knowledge) about contexts.

My personal view is that extending the DMA API in this way feels quite dirty - it's a violation of the DMA API design, which is to (a) demark the buffer ownership between CPU and DMA agent, and (b) to translate buffer locations into a cookie which device drivers can use to instruct their device to access that memory. To see why, consider... that you map a buffer to a device in context A, and then you switch to context B, which means the dma_addr_t given previously is no longer valid. You then try to unmap it... which is normally done using the (now no longer valid) dma_addr_t.

It seems to me that to support this at DMA API level, we would need to completely revamp the DMA API, which IMHO isn't going to be nice. (It would mean that we end up with three APIs - the original PCI DMA API, the existing DMA API, and some new DMA API.)

Do we have any views on how common this feature is?

On Tue, Feb 03, 2015 at 12:35:34PM -0500, Rob Clark wrote:

On Tue, Feb 3, 2015 at 11:58 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

Okay, but switching contexts is not something which the DMA API has any knowledge of (so it can't know which context to associate with which mapping.) While it knows which device, it has no knowledge (nor is there any way for it to gain knowledge) about contexts.

My personal view is that extending the DMA API in this way feels quite dirty - it's a violation of the DMA API design, which is to (a) demark the buffer ownership between CPU and DMA agent, and (b) to translate buffer locations into a cookie which device drivers can use to instruct their device to access that memory. To see why, consider... that you map a buffer to a device in context A, and then you switch to context B, which means the dma_addr_t given previously is no longer valid. You then try to unmap it... which is normally done using the (now no longer valid) dma_addr_t.

It seems to me that to support this at DMA API level, we would need to completely revamp the DMA API, which IMHO isn't going to be nice. (It would mean that we end up with three APIs - the original PCI DMA API, the existing DMA API, and some new DMA API.)

Do we have any views on how common this feature is?

I can't think of cases outside of GPU's.. if it were more common I'd be in favor of teaching dma api about multiple contexts, but right now I think that would just amount to forcing a lot of churn on everyone else for the benefit of GPU's.

IMHO it makes more sense for GPU drivers to bypass the dma api if they need to. Plus, sooner or later, someone will discover that with some trick or optimization they can get moar fps, but the extra layer of abstraction will just be getting in the way.

See my other reply, but all existing full-blown drivers don't bypass the dma api. Instead it's just a two-level scheme: 1. First level is dma api. Might or might not contain a system iommu. 2. 2nd level is the gpu-private iommu which is also used for per context address spaces. Thus far all drivers just rolled their own drivers for this (it's kinda fused to the chips on x86 hw anyway), but it looks like using the iommu api gives us a somewhat suitable abstraction for code sharing.

Imo you need both, otherwise we start leaking stuff like cpu cache flushing all over the place. Looking at i915 (where the dma api assumes that everything is coherent, which is kinda not the case) that won't be pretty. And there's still the issue that you might nest a system iommu and a 2nd level iommu for per-context pagetables (this is real and what's going on right now on intel hw). -Daniel

On Tue, Feb 3, 2015 at 9:52 AM, Arnd Bergmann arnd@arndb.de wrote:

On Tuesday 03 February 2015 14:41:09 Russell King - ARM Linux wrote:

...

On Tue, Feb 03, 2015 at 03:17:27PM +0100, Arnd Bergmann wrote:

...

On Tuesday 03 February 2015 09:04:03 Rob Clark wrote:

...

Since I'm stuck w/ an iommu, instead of built in mmu, my plan was to drop use of dma-mapping entirely (incl the current call to dma_map_sg, which I just need until we can use drm_cflush on arm), and attach/detach iommu domains directly to implement context switches. At that point, dma_addr_t really has no sensible meaning for me.

I think what you see here is a quite common hardware setup and we really lack the right abstraction for it at the moment. Everybody seems to work around it with a mix of the dma-mapping API and the iommu API. These are doing different things, and even though the dma-mapping API can be implemented on top of the iommu API, they are not really compatible.

I'd go as far as saying that the "DMA API on top of IOMMU" is more intended to be for a system IOMMU for the bus in question, rather than a device-level IOMMU.

If an IOMMU is part of a device, then the device should handle it (maybe via an abstraction) and not via the DMA API. The DMA API should be handing the bus addresses to the device driver which the device's IOMMU would need to generate. (In other words, in this circumstance, the DMA API shouldn't give you the device internal address.)

Exactly. And the abstraction that people choose at the moment is the iommu API, for better or worse. It makes a lot of sense to use this API if the same iommu is used for other devices as well (which is the case on Tegra and probably a lot of others). Unfortunately the iommu API lacks support for cache management, and probably other things as well, because this was not an issue for the original use case (device assignment on KVM/x86).

This could be done by adding explicit or implied cache management to the IOMMU mapping interfaces, or by extending the dma-mapping interfaces in a way that covers the use case of the device managing its own address space, in addition to the existing coherent and streaming interfaces.

I think for gpu's, we'd prefer explicit and less abstraction.. which is probably opposite of what every other driver would want

In the end, my eventual goal is explicit control of tlb flush, and control of my address space. And in fact in some cases we are going to want to use the gpu to bang on iommu registers to do context switches and tlb flushes. (Which is obviously not the first step.. and something that is fairly difficult to get right/secure.. but the performance win seems significant so I'm not sure we can avoid it.)

BR, -R

    Arnd

On Tue, Feb 03, 2015 at 09:04:03AM -0500, Rob Clark wrote:

Since I'm stuck w/ an iommu, instead of built in mmu, my plan was to drop use of dma-mapping entirely (incl the current call to dma_map_sg, which I just need until we can use drm_cflush on arm), and attach/detach iommu domains directly to implement context switches. At that point, dma_addr_t really has no sensible meaning for me.

So how do you intend to import from a subsystem which only gives you the dma_addr_t?

If you aren't passing system memory, you have no struct page. You can't fake up a struct page. What this means is that struct scatterlist can't represent it any other way.

On Tue, Feb 03, 2015 at 09:44:57AM -0500, Rob Clark wrote:

On Tue, Feb 3, 2015 at 9:37 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

On Tue, Feb 03, 2015 at 09:04:03AM -0500, Rob Clark wrote:

...

Since I'm stuck w/ an iommu, instead of built in mmu, my plan was to drop use of dma-mapping entirely (incl the current call to dma_map_sg, which I just need until we can use drm_cflush on arm), and attach/detach iommu domains directly to implement context switches. At that point, dma_addr_t really has no sensible meaning for me.

So how do you intend to import from a subsystem which only gives you the dma_addr_t?

If you aren't passing system memory, you have no struct page. You can't fake up a struct page. What this means is that struct scatterlist can't represent it any other way.

Tell the exporter to stop using carveouts, and give me proper memory instead.. ;-)

Well, at least on these SoC's, I think the only valid use for carveout memory is the bootloader splashscreen. And I was planning on just hanging on to that for myself for fbdev scanout buffer or other internal (non shared) usage..

I wasn't thinking about carveouts - as I already mentioned earlier in this thread, it may be memory which couldn't possibly ever be system memory - for example, a separate chunk of memory which is tightly coupled to the graphics system but not so to the CPU.

In such a case, we wouldn't want to use that as normal system memory, but we would want to allocate framebuffers and the like from it, and maybe pass them around.

While it may not be appropriate for MSM, it's still something that needs to be considered, because there may be (and I know there are) dmabuf users which do pass memory this way.

So, what I'm saying is that for the purposes of the dmabuf API, we can't mandate that the scatterlists will contain a valid struct page pointer. It'd probably be a good idea for the importer to validate the scatterlist at import time if it has this requirement.

However, thinking about this more, I think that from a generic design point of view, we really should limit the "struct page" usage to a special MSM-ism - something which should definitely not be copied by other drivers. As has been mentioned previously, if there is a system MMU which needs to be programmed to map system memory onto the bus, the struct page becomes absolutely useless, and the only thing that gives you the correct "handle" to that memory is the dma_addr_t.

Finally, note that n_mapped = dma_map_sg(dev, sg, n_ent, dir) - n_mapped can be less than n_ent when there's the presence of an IOMMU, since an IOMMU is permitted to coalesce individual scatterlist entries if it so chooses, and when walking the scatterlist for DMA purposes, the scatterlist sg_dma_*() accessors should be used, and it should be iterated over from 0 to n_mapped, not 0 to n_ent. It's important to realise that in driver code, sg->length may not be the same as sg_dma_len(sg) for exactly this reason:

#ifdef CONFIG_NEED_SG_DMA_LENGTH #define sg_dma_len(sg) ((sg)->dma_length) #else #define sg_dma_len(sg) ((sg)->length) #endif

On Wed, Feb 11, 2015 at 6:12 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

On Wed, Feb 11, 2015 at 09:28:37AM +0100, Marek Szyprowski wrote:

...

Hello,

On 2015-01-27 09:25, Sumit Semwal wrote:

...

Add some helpers to share the constraints of devices while attaching to the dmabuf buffer.

At each attach, the constraints are calculated based on the following:

• max_segment_size, max_segment_count, segment_boundary_mask from device_dma_parameters.

In case the attaching device's constraints don't match up, attach() fails.

At detach, the constraints are recalculated based on the remaining attached devices.

Two helpers are added:

• dma_buf_get_constraints - which gives the current constraints as calculated during each attach on the buffer till the time,
• dma_buf_recalc_constraints - which recalculates the constraints for all currently attached devices for the 'paranoid' ones amongst us.

The idea of this patch is largely taken from Rob Clark's RFC at https://lkml.org/lkml/2012/7/19/285, and the comments received on it.

Cc: Rob Clark robdclark@gmail.com Signed-off-by: Sumit Semwal sumit.semwal@linaro.org

The code looks okay, although it will probably will work well only with typical cases like 'contiguous memory needed' or 'no constraints at all' (iommu).

Which is a damn good reason to NAK it - by that admission, it's a half-baked idea.

If all we want to know is whether the importer can accept only contiguous memory or not, make a flag to do that, and allow the exporter to test this flag. Don't over-engineer this to make it _seem_ like it can do something that it actually totally fails with.

jfyi, I agree with that.. I think the flag is probably the right approach to start with. At the end of the day it *is* still just an in-kernel API (and not something that ends up as userspace ABI) so when we come up with the use case to make it more generic we can. Vs. making it look like something more generic when it isn't really yet.

As I've already pointed out, there's a major problem if you have already had a less restrictive attachment which has an active mapping, and a new more restrictive attachment comes along later.

It seems from Rob's descriptions that we also need another flag in the importer to indicate whether it wants to have a valid struct page in the scatter list, or whether it (correctly) uses the DMA accessors on the scatter list - so that exporters can reject importers which are buggy.

to be completely generic, we would really need a way that the device could take over only just the last iommu (in case there were multiple levels of address translation)..

I'm not completely sure, but I *think* the other arm gpu's have their own internal mmu for doing context switching, etc, so if there is an additional iommu in front of them they may actually still want to use the normal dma api's. Someone please contradict me if I am wrong. If this ends up being an issue only for msm, then I'm completely ok with the easier option of a less generic solution..

BR, -R

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

On Wed, Feb 11, 2015 at 7:56 AM, Daniel Vetter daniel@ffwll.ch wrote:

On Wed, Feb 11, 2015 at 06:23:52AM -0500, Rob Clark wrote:

...

On Wed, Feb 11, 2015 at 6:12 AM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

As I've already pointed out, there's a major problem if you have already had a less restrictive attachment which has an active mapping, and a new more restrictive attachment comes along later.

It seems from Rob's descriptions that we also need another flag in the importer to indicate whether it wants to have a valid struct page in the scatter list, or whether it (correctly) uses the DMA accessors on the scatter list - so that exporters can reject importers which are buggy.

to be completely generic, we would really need a way that the device could take over only just the last iommu (in case there were multiple levels of address translation)..

I still hold that if the dma api steals the iommu your gpu needs for context switching then that's a bug in the platform setup code. dma api really doesn't have any concept of switchable hw contexts. So trying to work around this brokeness by mandating it as a valid dma-buf use-case is totally backwards.

sure, my only point is that if I'm the odd man out, I can live with a hack (ie. requiring drm/msm to be aware enough of the platform to know if there is >1 level of address translation and frob'ing my 'struct device' accordingly)... no point in a generic solution for one user. I like to be practical.

BR, -R

-Daniel

Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch

On Wed, Feb 11, 2015 at 01:20:24PM +0100, Marek Szyprowski wrote:

Hello,

On 2015-02-11 12:12, Russell King - ARM Linux wrote:

...

Which is a damn good reason to NAK it - by that admission, it's a half-baked idea.

If all we want to know is whether the importer can accept only contiguous memory or not, make a flag to do that, and allow the exporter to test this flag. Don't over-engineer this to make it _seem_ like it can do something that it actually totally fails with.

As I've already pointed out, there's a major problem if you have already had a less restrictive attachment which has an active mapping, and a new more restrictive attachment comes along later.

It seems from Rob's descriptions that we also need another flag in the importer to indicate whether it wants to have a valid struct page in the scatter list, or whether it (correctly) uses the DMA accessors on the scatter list - so that exporters can reject importers which are buggy.

Okay, but flag-based approach also have limitations.

Yes, the flag-based approach doesn't let you describe in detail what the importer can accept - which, given the issues that I've raised is a *good* thing. We won't be misleading anyone into thinking that we can do something that's really half-baked, and which we have no present requirement for.

This is precisely what Linus talks about when he says "don't over- engineer" - if we over-engineer this, we end up with something that sort-of works, and that's a bad thing.

The Keep It Simple approach here makes total sense - what are our current requirements - to be able to say that an importer can only accept: - contiguous memory rather than a scatterlist - scatterlists with struct page pointers

Does solving that need us to compare all the constraints of each and every importer, possibly ending up with constraints which can't be satisfied? No. Does the flag approach satisfy the requirements? Yes.

Frankly, if we want to make it really portable and sharable between devices, then IMO we should get rid of struct scatterlist and replace it with simple array of pfns in dma_buf. This way at least the problem of missing struct page will be solved and the buffer representation will be also a bit more compact.

... and move the mapping and unmapping of the PFNs to the importer, which IMHO is where it should already be (so the importer can decide when it should map the buffer itself independently of getting the details of the buffer.)

Such solution however also requires extending dma-mapping API to handle mapping and unmapping of such pfn arrays. The advantage of this approach is the fact that it will be completely new API, so it can be designed well from the beginning.

As far as I'm aware, there was no big discussion of the dma_buf API - it's something that just appeared one day (I don't remember seeing it discussed.) So, that may well be a good thing if it means we can get these kinds of details better hammered out.

However, I don't share your view of "completely new API" - that would be far too disruptive. I think we can modify the existing API, to achieve our goals.

I don't think changing the dma-mapping API just for this case is really on though - if we're passed a list of PFNs, they either must be all associated with a struct page - iow, pfn_valid(pfn) returns true for all of them or none of them. If none of them, then we need to be able to convert those PFNs to a dma_addr_t for the target device (yes, that may need the dma-mapping API augmenting.)

However, if they are associated with a struct page, then we should use the established APIs and use a scatterlist, otherwise we're looking at rewriting all IOMMUs and all DMA mapping implementations to handle what would become a special case for dma_buf.

I'd rather... Keep It Simple.

So, maybe, as a first step, let's augment dma_buf with a pair of functions which get the "raw" unmapped scatterlist:

struct sg_table *dma_buf_get_scatterlist(struct dma_buf_attachment *attach) { struct sg_table *sg_table;

might_sleep();

if (!attach->dmabuf->ops->get_scatterlist) return ERR_PTR(-EINVAL);

sg_table = attach->dmabuf->ops->get_scatterlist(attach); if (!sg_table) sg_table = ERR_PTR(-ENOMEM);

return sg_table; }

void dma_buf_put_scatterlist(struct dma_buf_attachment *attach, struct sg_table *sg_table) { might_sleep();

attach->dmabuf->ops->put_scatterlist(attach, sg_table); }

Implementations should arrange for dma_buf_get_scatterlist() to return the EINVAL error pointer if they are unable to provide an unmapped scatterlist (in other words, they are exporting a set of PFNs or already-mapped dma_addr_t's.) This can be done by either not implementing the get_scatterlist method, or by implementing it and returning that forementioned error pointer value.

Where these two are implemented and used, the importer is responsible for calling dma_map_sg() and dma_unmap_sg() on the returned scatterlist table.

unsigned long *dma_buf_get_pfns(struct dma_buf_attachment *attach) { unsigned long *pfns;

might_sleep();

if (!attach->dmabuf->ops->get_pfns) return ERR_PTR(-EINVAL);

return attach->dmabuf->ops->get_pfns(attach); }

void dma_buf_put_pfns(struct dma_buf_attachment *attach, unsigned long *pfns) { might_sleep();

attach->dmabuf->ops->put_pfns(attach, pfns); }

Similar to the above, but this gets a list of PFNs. Each PFN entry prior to the last describes a page starting at offset 0 extending to the end of the page. The last PFN entry describes a page starting at offset 0 and extending to the offset of the attachment size within the page. Again, if not implemented or it is not possible to represent the buffer as PFNs, it returns -EINVAL.

For the time being, we keep the existing dma_buf_map_attachment() and dma_buf_unmap_attachment() while we transition users over to the new interfaces.

We may wish to augment struct dma_buf_attachment with a couple of flags to indicate which of these the attached dma_buf supports, so that drivers can deal with these themselves.

We may also wish in the longer term to keep dma_buf_map_attachment() but implement it as a wrapper around get_scatterlist() as a helper to provide its existing functionality - providing a mapped scatterlist. Possibly also including get_pfns() in that as well if we need to.

However, I would still like more thought put into Rob's issue to see whether we can solve his problem with using the dma_addr_t in a more elegant way. (I wish I had some hardware to experiment with for that.)

Hi Sumit,

On 05/05/2015 04:41 PM, Sumit Semwal wrote:

Hi Russell, everyone,

First up, sincere apologies for being awol for sometime; had some personal / medical things to take care of, and then I thought I'd wait for the merge window to get over before beginning to discuss this again.

On 11 February 2015 at 21:53, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

On Wed, Feb 11, 2015 at 01:20:24PM +0100, Marek Szyprowski wrote:

...

Hello,

On 2015-02-11 12:12, Russell King - ARM Linux wrote:

...

Which is a damn good reason to NAK it - by that admission, it's a half-baked idea.

If all we want to know is whether the importer can accept only contiguous memory or not, make a flag to do that, and allow the exporter to test this flag. Don't over-engineer this to make it _seem_ like it can do something that it actually totally fails with.

As I've already pointed out, there's a major problem if you have already had a less restrictive attachment which has an active mapping, and a new more restrictive attachment comes along later.

It seems from Rob's descriptions that we also need another flag in the importer to indicate whether it wants to have a valid struct page in the scatter list, or whether it (correctly) uses the DMA accessors on the scatter list - so that exporters can reject importers which are buggy.

Okay, but flag-based approach also have limitations.

Yes, the flag-based approach doesn't let you describe in detail what the importer can accept - which, given the issues that I've raised is a *good* thing. We won't be misleading anyone into thinking that we can do something that's really half-baked, and which we have no present requirement for.

This is precisely what Linus talks about when he says "don't over- engineer" - if we over-engineer this, we end up with something that sort-of works, and that's a bad thing.

The Keep It Simple approach here makes total sense - what are our current requirements - to be able to say that an importer can only accept:

• contiguous memory rather than a scatterlist
• scatterlists with struct page pointers

Does solving that need us to compare all the constraints of each and every importer, possibly ending up with constraints which can't be satisfied? No. Does the flag approach satisfy the requirements? Yes.

So, for basic constraint-sharing, we'll just go with the flag based approach, with a flag (best place for it is still dev->dma_params I suppose) for denoting contiguous or scatterlist. Is that agreed, then? Also, with this idea, of course, there won't be any helpers for trying to calculate constraints; it would be totally the exporter's responsibility to handle it via the attach() dma_buf_op if it wishes to.

What's wrong with the proposed max_segment_count? Many media devices do have a limited max_segment_count and that should be taken into account.

Although to be fair I have to say that in practice the limited segment counts are all well above what is needed for a normal capture buffer, but it might be reached if you have video strides > line width, so each line has its own segment (or two, if there is a page boundary in the middle of the line). It's a somewhat contrived use-case, though, although I have done this once myself.

Anyway, the worst-case number of segments would be:

height * ((bytesperline + PAGE_SIZE - 1) / PAGE_SIZE)

That might well exceed the max segment count for some devices.

I think I have also seen devices in the past that have a coarse-grained IOMMU that uses very large segment sizes, but have a very limited segment count. We don't have media drivers like that, and to be honest I am not sure whether we should bother too much with this corner case.

...

...

Frankly, if we want to make it really portable and sharable between devices, then IMO we should get rid of struct scatterlist and replace it with simple array of pfns in dma_buf. This way at least the problem of missing struct page will be solved and the buffer representation will be also a bit more compact.

... and move the mapping and unmapping of the PFNs to the importer, which IMHO is where it should already be (so the importer can decide when it should map the buffer itself independently of getting the details of the buffer.)

...

Such solution however also requires extending dma-mapping API to handle mapping and unmapping of such pfn arrays. The advantage of this approach is the fact that it will be completely new API, so it can be designed well from the beginning.

As far as I'm aware, there was no big discussion of the dma_buf API - it's something that just appeared one day (I don't remember seeing it discussed.) So, that may well be a good thing if it means we can get these kinds of details better hammered out.

However, I don't share your view of "completely new API" - that would be far too disruptive. I think we can modify the existing API, to achieve our goals.

I don't think changing the dma-mapping API just for this case is really on though - if we're passed a list of PFNs, they either must be all associated with a struct page - iow, pfn_valid(pfn) returns true for all of them or none of them. If none of them, then we need to be able to convert those PFNs to a dma_addr_t for the target device (yes, that may need the dma-mapping API augmenting.)

However, if they are associated with a struct page, then we should use the established APIs and use a scatterlist, otherwise we're looking at rewriting all IOMMUs and all DMA mapping implementations to handle what would become a special case for dma_buf.

I'd rather... Keep It Simple.

+1 for Keep it simple, and the idea overall. Though I suspect more dma-buf users (dri / v4l friends?) should comment if this doesn't help solve things on some platforms / subsystems that they care about.

...

So, maybe, as a first step, let's augment dma_buf with a pair of functions which get the "raw" unmapped scatterlist:

struct sg_table *dma_buf_get_scatterlist(struct dma_buf_attachment *attach) { struct sg_table *sg_table;

    might_sleep();

    if (!attach->dmabuf->ops->get_scatterlist)
            return ERR_PTR(-EINVAL);

    sg_table = attach->dmabuf->ops->get_scatterlist(attach);
    if (!sg_table)
            sg_table = ERR_PTR(-ENOMEM);

    return sg_table;

}

void dma_buf_put_scatterlist(struct dma_buf_attachment *attach, struct sg_table *sg_table) { might_sleep();

    attach->dmabuf->ops->put_scatterlist(attach, sg_table);

}

Implementations should arrange for dma_buf_get_scatterlist() to return the EINVAL error pointer if they are unable to provide an unmapped scatterlist (in other words, they are exporting a set of PFNs or already-mapped dma_addr_t's.) This can be done by either not implementing the get_scatterlist method, or by implementing it and returning that forementioned error pointer value.

Where these two are implemented and used, the importer is responsible for calling dma_map_sg() and dma_unmap_sg() on the returned scatterlist table.

unsigned long *dma_buf_get_pfns(struct dma_buf_attachment *attach) { unsigned long *pfns;

    might_sleep();

    if (!attach->dmabuf->ops->get_pfns)
            return ERR_PTR(-EINVAL);

    return attach->dmabuf->ops->get_pfns(attach);

}

void dma_buf_put_pfns(struct dma_buf_attachment *attach, unsigned long *pfns) { might_sleep();

    attach->dmabuf->ops->put_pfns(attach, pfns);

}

Similar to the above, but this gets a list of PFNs. Each PFN entry prior to the last describes a page starting at offset 0 extending to the end of the page. The last PFN entry describes a page starting at offset 0 and extending to the offset of the attachment size within the page. Again, if not implemented or it is not possible to represent the buffer as PFNs, it returns -EINVAL.

For the time being, we keep the existing dma_buf_map_attachment() and dma_buf_unmap_attachment() while we transition users over to the new interfaces.

We may wish to augment struct dma_buf_attachment with a couple of flags to indicate which of these the attached dma_buf supports, so that drivers can deal with these themselves.

Could I please send a patchset first for the constraint-flags addition, and then take this up in a following patch-set, once we have agreement from other stake holders as well?

+1

One of the main problems end-users are faced with today is that they do not know which device should be the exporter of buffers and which should be the importer. This depends on the constraints and right now applications have no way of knowing this. It's nuts that this hasn't been addressed yet since it is the main complaint I am getting.

And it is something that the V4L2 API needs to export to userland anyway for both the above and some other V4L2-specific reasons.

BTW, one thing I didn't see in the constraints discussion (but I didn't read everything, so I may very well have missed it), is reporting whether memory is opaque (i.e. cannot be mapped by non-trusted devices). No, I don't have such hardware, but I know it exists. All the constraints mentioned so far apply to such memory as well, but this is an additional flag (or perhaps some trust ID). I don't think anyone made drivers for such hardware, although I recently saw someone working on something like that.

Does anyone know about someone working in this area? Or existing code for this?

All I am saying is that this is sure to appear at some point.

Regards,

Hans

Russell: would it be ok if we discuss it offline more? I am afraid I am not as knowledgeable on this topic, and would probably request your help / guidance here.

...

We may also wish in the longer term to keep dma_buf_map_attachment() but implement it as a wrapper around get_scatterlist() as a helper to provide its existing functionality - providing a mapped scatterlist. Possibly also including get_pfns() in that as well if we need to.

However, I would still like more thought put into Rob's issue to see whether we can solve his problem with using the dma_addr_t in a more elegant way. (I wish I had some hardware to experiment with for that.)

-- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net.

Best regards, ~Sumit. _______________________________________________ Linaro-mm-sig mailing list Linaro-mm-sig@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-mm-sig

On 06/03/15 10:41, Russell King - ARM Linux wrote:

On Wed, Jun 03, 2015 at 08:39:55AM +0200, Hans Verkuil wrote:

...

Hi Sumit,

On 05/05/2015 04:41 PM, Sumit Semwal wrote:

...

Hi Russell, everyone,

First up, sincere apologies for being awol for sometime; had some personal / medical things to take care of, and then I thought I'd wait for the merge window to get over before beginning to discuss this again.

On 11 February 2015 at 21:53, Russell King - ARM Linux linux@arm.linux.org.uk wrote:

...

On Wed, Feb 11, 2015 at 01:20:24PM +0100, Marek Szyprowski wrote:

...

Hello,

On 2015-02-11 12:12, Russell King - ARM Linux wrote:

...

Which is a damn good reason to NAK it - by that admission, it's a half-baked idea.

If all we want to know is whether the importer can accept only contiguous memory or not, make a flag to do that, and allow the exporter to test this flag. Don't over-engineer this to make it _seem_ like it can do something that it actually totally fails with.

As I've already pointed out, there's a major problem if you have already had a less restrictive attachment which has an active mapping, and a new more restrictive attachment comes along later.

It seems from Rob's descriptions that we also need another flag in the importer to indicate whether it wants to have a valid struct page in the scatter list, or whether it (correctly) uses the DMA accessors on the scatter list - so that exporters can reject importers which are buggy.

Okay, but flag-based approach also have limitations.

Yes, the flag-based approach doesn't let you describe in detail what the importer can accept - which, given the issues that I've raised is a *good* thing. We won't be misleading anyone into thinking that we can do something that's really half-baked, and which we have no present requirement for.

This is precisely what Linus talks about when he says "don't over- engineer" - if we over-engineer this, we end up with something that sort-of works, and that's a bad thing.

The Keep It Simple approach here makes total sense - what are our current requirements - to be able to say that an importer can only accept:

• contiguous memory rather than a scatterlist
• scatterlists with struct page pointers

Does solving that need us to compare all the constraints of each and every importer, possibly ending up with constraints which can't be satisfied? No. Does the flag approach satisfy the requirements? Yes.

So, for basic constraint-sharing, we'll just go with the flag based approach, with a flag (best place for it is still dev->dma_params I suppose) for denoting contiguous or scatterlist. Is that agreed, then? Also, with this idea, of course, there won't be any helpers for trying to calculate constraints; it would be totally the exporter's responsibility to handle it via the attach() dma_buf_op if it wishes to.

What's wrong with the proposed max_segment_count? Many media devices do have a limited max_segment_count and that should be taken into account.

So what happens if you have a dma_buf exporter, and several dma_buf importers. One dma_buf importer attaches to the exporter, and asks for the buffer, and starts making use of the buffer. This export has many scatterlist segments.

Another dma_buf importer attaches to the same buffer, and now asks for the buffer, but the number of scatterlist segments exceeds it's requirement.

You can't reallocate the buffer because it's in-use by another importer. There is no way to revoke the buffer from the other importer. So there is no way to satisfy this importer's requirements.

What I'm showing is that the idea that exporting these parameters fixes some problem is just an illusion - it may work for the single importer case, but doesn't for the multiple importer case.

Importers really have two choices here: either they accept what the exporter is giving them, or they reject it.

I agree completely with that.

The other issue here is that DMA scatterlists are _not_ really that determinable in terms of number of entries when it comes to systems with system IOMMUs. System IOMMUs, which should be integrated into the DMA API, are permitted to coalesce entries in the physical page range. For example:

nsg = 128; n = dma_map_sg(dev, sg, nsg, DMA_TO_DEVICE);

Here, n might be 4 if the system IOMMU has been able to coalesce the 128 entries down to 4 IOMMU entries - and that means for DMA purposes, only the first four scatterlist entries should be walked (this is why dma_map_sg() returns a positive integer when mapping.)

Each struct device has a set of parameters which control how the IOMMU entries are coalesced:

struct device_dma_parameters { /* * a low level driver may set these to teach IOMMU code about * sg limitations. */ unsigned int max_segment_size; unsigned long segment_boundary_mask; };

and this is independent of the dma_buf API. This doesn't indicate the maximum number of segments, but as I've shown above, it's not something that you can say "I want a scatterlist for this memory with only 32 segments" so it's totally unclear how an exporter would limit that.

The only thing an exporter could do would be to fail the export if the buffer didn't end up having fewer than the requested scatterlist entries, which is something the importer can do too.

Right.

...

One of the main problems end-users are faced with today is that they do not know which device should be the exporter of buffers and which should be the importer. This depends on the constraints and right now applications have no way of knowing this. It's nuts that this hasn't been addressed yet since it is the main complaint I am getting.

IT's nuts that we've ended up in this situation in the first place. This was bound to happen as soon as the dma_buf sharing was introduced, because it immediately introduced this problem. I don't think there is any easy solution to it, and what's being proposed with flags and other stuff is just trying to paper over the problem.

This was the first thing raised in the initial discussions. My suggestion at the time was to give userspace limited information about the buffer restrictions: Physically contiguous, scatter-gather and 'weird'. But obviously you need segment_boundary_mask and max_segment_size as well.

And the application can decide based on that info which device has the most restrictive requirements and make that the exporter.

I am not sure whether there is any sense in exporting the max_segment_count to userspace (probably not), but I see no reason why we can't set it internally. That said, a single flag is OK for me as well.

What you're actually asking is that each dmabuf exporting subsystem needs to publish their DMA parameters to userspace, and userspace then gets to decide which dmabuf exporter should be used.

Yes, that was the initial plan.

That's not a dmabuf problem, that's a subsystem problem,

Well, yes, but it doesn't hurt to sync which DMA parameters are exposed with what dma-buf uses.

but even so, we don't have a standardised way to export that information (and I'd suspect that it would be very difficult to get agreements between subsystems on a standard ioctl and/or data structure.) In my experience, getting cross- subsystem agreement in the kernel with anything is very difficult, you normally end up with 60% of people agreeing, and the other 40% going off and doing something completely different because they object to it (figures vary, 90% of all statistics are made up on the spot!)

I don't care which ioctl or other mechanism a subsystem uses to expose the information. Each subsystem should design their own method for that. Imposing a standard API for that generally doesn't work for the reasons you give.

But deciding *which* minimum set of information is exposed, that is another matter and that should be synced. And the easiest starting point for that is that the device will store that information internally in device_dma_parameters.

The various subsystems can then make APIs to expose that info.

Regards,

Hans