Video Time Generator drivers are used to synchronize the compositor and tvout hardware IPs by providing line count, sample count, synchronization signals (HSYNC, VSYNC) and top and bottom fields indication. VTG are used by pair for each data path (main or auxiliary): one for master and one for slave.

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com

--- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/sti/Kconfig | 11 + drivers/gpu/drm/sti/Makefile | 3 + drivers/gpu/drm/sti/sti_vtg.c | 430 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_vtg.h | 20 ++ drivers/gpu/drm/sti/sti_vtg_utils.c | 99 +++++++++ drivers/gpu/drm/sti/sti_vtg_utils.h | 26 +++ 8 files changed, 592 insertions(+) create mode 100644 drivers/gpu/drm/sti/Kconfig create mode 100644 drivers/gpu/drm/sti/Makefile create mode 100644 drivers/gpu/drm/sti/sti_vtg.c create mode 100644 drivers/gpu/drm/sti/sti_vtg.h create mode 100644 drivers/gpu/drm/sti/sti_vtg_utils.c create mode 100644 drivers/gpu/drm/sti/sti_vtg_utils.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index d1cc2f6..0e30029 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -201,3 +201,5 @@ source "drivers/gpu/drm/tegra/Kconfig" source "drivers/gpu/drm/panel/Kconfig"

source "drivers/gpu/drm/bridge/Kconfig" + +source "drivers/gpu/drm/sti/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 5e792b0..44f7b17 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_BOCHS) += bochs/ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_TEGRA) += tegra/ +obj-$(CONFIG_DRM_STI) += sti/ obj-y += i2c/ obj-y += panel/ obj-y += bridge/ diff --git a/drivers/gpu/drm/sti/Kconfig b/drivers/gpu/drm/sti/Kconfig new file mode 100644 index 0000000..b3c751c --- /dev/null +++ b/drivers/gpu/drm/sti/Kconfig @@ -0,0 +1,11 @@ +config DRM_STI + tristate "DRM Support for STMicroelectronics SoC stiH41x Series" + depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) + help + Choose this option to enable DRM on STM stiH41x chipset + +config VTG_STI + tristate "Video Timing Generator for STMicroelectronics SoC stiH41x Series" + depends on DRM_STI + help + Choose this option to enable VTG on STM stiH41x chipset diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile new file mode 100644 index 0000000..33216e1 --- /dev/null +++ b/drivers/gpu/drm/sti/Makefile @@ -0,0 +1,3 @@ +ccflags-y := -Iinclude/drm + +obj-$(CONFIG_VTG_STI) += sti_vtg.o sti_vtg_utils.o diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c new file mode 100644 index 0000000..d3514c1 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -0,0 +1,430 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * Vincent Abriou vincent.abriou@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/notifier.h> + +#include "sti_vtg_utils.h" +#include "sti_vtg.h" + +#define VTG_TYPE_MASTER 0 +#define VTG_TYPE_SLAVE_BY_EXT0 1 + +/* registers offset */ +#define VTG_MODE 0x0000 +#define VTG_CLKLN 0x0008 +#define VTG_HLFLN 0x000C +#define VTG_DRST_AUTOC 0x0010 +#define VTG_VID_TFO 0x0040 +#define VTG_VID_TFS 0x0044 +#define VTG_VID_BFO 0x0048 +#define VTG_VID_BFS 0x004C + +#define VTG_HOST_ITS 0x0078 +#define VTG_HOST_ITS_BCLR 0x007C +#define VTG_HOST_ITM_BCLR 0x0088 +#define VTG_HOST_ITM_BSET 0x008C + +#define VTG_H_HD_1 0x00C0 +#define VTG_TOP_V_VD_1 0x00C4 +#define VTG_BOT_V_VD_1 0x00C8 +#define VTG_TOP_V_HD_1 0x00CC +#define VTG_BOT_V_HD_1 0x00D0 + +#define VTG_H_HD_2 0x00E0 +#define VTG_TOP_V_VD_2 0x00E4 +#define VTG_BOT_V_VD_2 0x00E8 +#define VTG_TOP_V_HD_2 0x00EC +#define VTG_BOT_V_HD_2 0x00F0 + +#define VTG_H_HD_3 0x0100 +#define VTG_TOP_V_VD_3 0x0104 +#define VTG_BOT_V_VD_3 0x0108 +#define VTG_TOP_V_HD_3 0x010C +#define VTG_BOT_V_HD_3 0x0110 + +/* IRQ mask */ +#define VTG_IRQ_MASK ((1L<<1) | (1L<<0)) + +/* Delay introduced by the AWG in nb of pixels */ +#define AWG_DELAY_HD (-9) +#define AWG_DELAY_ED (-8) +#define AWG_DELAY_SD (-7) + +static const struct of_device_id vtg_match_types[]; + +/* + * STI VTG data structure + * + * @nb_reg: number of memory resources to register + * @reg_names: names of the memory resources to register + * @regs: ioremapped registers + */ +#define MAX_MEM_REGION 2 +#define VTG_MASTER 0 +#define VTG_SLAVE 1 +struct sti_vtg_data { + int nb_reg; + char *reg_names[MAX_MEM_REGION]; + void __iomem *regs[MAX_MEM_REGION]; +}; + +/* + * STI VTG structure + * + * @dev: pointer to device driver + * @data: data associated to the device + * @irq: VTG irq + * @type: VTG type (main or aux) + * @notifier_list: notifier callback + */ +struct sti_vtg { + struct device *dev; + struct sti_vtg_data data; + int irq; + int type; + struct raw_notifier_head notifier_list; +}; + +/* + * STiH416: + * -------- + * VTG slave is connected to the VTG master by the ext0 input (ext1 input is + * left unconnected). + * + * MPE ! ! SAS + * ________ ! ! ________ + * | | ! ! ext0 | | + * | | _________! !_________ ----->| | + * | VTG | hsync | ! ! | hsync | | VTG | + * | |------------>| VTAC Tx !==>! VTAC Rx |-------- | | + * | master | vsync |_________! !_________| vsync | slave | + * | | ! ! ---->| | + * |________| ! ! ext1 |________| + * ! ! | + * ! ! synchro_irq + * */ +struct sti_vtg_data stih416_vtg_data = { + .nb_reg = 2, + .reg_names = {"master", "slave"}, +}; + +/* + * STiH407: + * -------- + * Only VTG master is used. There is no MPE and SAS domain => only one domain. + * + * MPE + * ________ + * | | + * | | + * | VTG | hsync + * | |------------> + * | master | vsync + * | | + * |________| + * | + * synchro_irq + * */ +struct sti_vtg_data stih407_vtg_data = { + .nb_reg = 1, + .reg_names = {"master"}, +}; + +static int vtg_reset(void __iomem *regs) +{ + writel(1, regs + VTG_DRST_AUTOC); + return 0; +} + +static int vtg_reg_dump(struct device *dev, void __iomem *regs) +{ + dev_dbg(dev, "regs %p\n", regs); + dev_dbg(dev, "VTG_MODE 0x%x\n", readl(regs + VTG_MODE)); + dev_dbg(dev, "VTG_CLKLN 0x%x\n", readl(regs + VTG_CLKLN)); + dev_dbg(dev, "VTG_HLFLN 0x%x\n", readl(regs + VTG_HLFLN)); + dev_dbg(dev, "VTG_VID_TFO 0x%x\n", readl(regs + VTG_VID_TFO)); + dev_dbg(dev, "VTG_VID_BFO 0x%x\n", readl(regs + VTG_VID_BFO)); + dev_dbg(dev, "VTG_VID_TFS 0x%x\n", readl(regs + VTG_VID_TFS)); + dev_dbg(dev, "VTG_VID_BFS 0x%x\n", readl(regs + VTG_VID_BFS)); + dev_dbg(dev, "VTG_H_HD_1 0x%x\n", readl(regs + VTG_H_HD_1)); + dev_dbg(dev, "VTG_TOP_V_VD_1 0x%x\n", readl(regs + VTG_TOP_V_VD_1)); + dev_dbg(dev, "VTG_BOT_V_VD_1 0x%x\n", readl(regs + VTG_BOT_V_VD_1)); + dev_dbg(dev, "VTG_TOP_V_HD_1 0x%x\n", readl(regs + VTG_TOP_V_HD_1)); + dev_dbg(dev, "VTG_BOT_V_HD_1 0x%x\n", readl(regs + VTG_BOT_V_HD_1)); + dev_dbg(dev, "VTG_H_HD_2 0x%x\n", readl(regs + VTG_H_HD_2)); + dev_dbg(dev, "VTG_TOP_V_VD_2 0x%x\n", readl(regs + VTG_TOP_V_VD_2)); + dev_dbg(dev, "VTG_BOT_V_VD_2 0x%x\n", readl(regs + VTG_BOT_V_VD_2)); + dev_dbg(dev, "VTG_TOP_V_HD_2 0x%x\n", readl(regs + VTG_TOP_V_HD_2)); + dev_dbg(dev, "VTG_BOT_V_HD_2 0x%x\n", readl(regs + VTG_BOT_V_HD_2)); + dev_dbg(dev, "VTG_H_HD_3 0x%x\n", readl(regs + VTG_H_HD_3)); + dev_dbg(dev, "VTG_TOP_V_VD_3 0x%x\n", readl(regs + VTG_TOP_V_VD_3)); + dev_dbg(dev, "VTG_BOT_V_VD_3 0x%x\n", readl(regs + VTG_BOT_V_VD_3)); + dev_dbg(dev, "VTG_TOP_V_HD_3 0x%x\n", readl(regs + VTG_TOP_V_HD_3)); + dev_dbg(dev, "VTG_BOT_V_HD_3 0x%x\n", readl(regs + VTG_BOT_V_HD_3)); + return 0; +} + +static int vtg_write_reg(void __iomem *regs, + int type, const struct drm_display_mode *mode) +{ + int fo, fs, h_hd, v_vd, v_hd; + + writel(mode->htotal, regs + VTG_CLKLN); + writel(mode->vtotal * 2, regs + VTG_HLFLN); + + fo = (mode->vtotal - mode->vsync_start + 1) << 16; + fo |= mode->htotal - mode->hsync_start; + writel(fo, regs + VTG_VID_TFO); + writel(fo, regs + VTG_VID_BFO); + + fs = (mode->vdisplay + mode->vtotal - mode->vsync_start + 1) << 16; + fs |= mode->hdisplay + mode->htotal - mode->hsync_start; + writel(fs, regs + VTG_VID_TFS); + writel(fs, regs + VTG_VID_BFS); + + /* Prepare VTG set 1 for HDMI and VTG set 3 for HD DAC */ + h_hd = (mode->hsync_end - mode->hsync_start) << 16; + writel(h_hd, regs + VTG_H_HD_1); + + v_vd = (mode->vsync_end - mode->vsync_start + 1) << 16; + v_vd |= 1; + writel(v_vd, regs + VTG_TOP_V_VD_1); + writel(v_vd, regs + VTG_BOT_V_VD_1); + writel(0, regs + VTG_TOP_V_HD_1); + writel(0, regs + VTG_BOT_V_HD_1); + + /* Prepare VTG set 2 for for HD DCS */ + writel(h_hd, regs + VTG_H_HD_2); + writel(v_vd, regs + VTG_TOP_V_VD_2); + writel(v_vd, regs + VTG_BOT_V_VD_2); + writel(0, regs + VTG_TOP_V_HD_2); + writel(0, regs + VTG_BOT_V_HD_2); + + /* Prepare VTG set 3 for HD Analog in HD mode */ + h_hd = (mode->hsync_end - mode->hsync_start + AWG_DELAY_HD) << 16; + h_hd |= mode->htotal + AWG_DELAY_HD; + writel(h_hd, regs + VTG_H_HD_3); + + v_vd = (mode->vsync_end - mode->vsync_start) << 16; + v_vd |= mode->vtotal; + writel(v_vd, regs + VTG_TOP_V_VD_3); + writel(v_vd, regs + VTG_BOT_V_VD_3); + + v_hd = (mode->htotal + AWG_DELAY_HD) << 16; + v_hd |= mode->htotal + AWG_DELAY_HD; + writel(v_hd, regs + VTG_TOP_V_HD_3); + writel(v_hd, regs + VTG_BOT_V_HD_3); + + /* Mode */ + writel(type, regs + VTG_MODE); + return 0; +} + +static int vtg_disable_irq(void __iomem *regs) +{ + /* Clear interrupt status and mask */ + writel(0xFFFF, regs + VTG_HOST_ITS_BCLR); + writel(0xFFFF, regs + VTG_HOST_ITM_BCLR); + return 0; +} + +static int vtg_enable_irq(void __iomem *regs) +{ + vtg_disable_irq(regs); + writel(VTG_IRQ_MASK, regs + VTG_HOST_ITM_BSET); + return 0; +} + +int vtg_set_config(struct device *dev, const struct drm_display_mode *mode) +{ + struct sti_vtg *vtg = dev_get_drvdata(dev); + struct sti_vtg_data *data = &vtg->data; + + if (!vtg) + return 1; + + if (!data->regs[VTG_MASTER]) + return 1; + + /* write slave / master configuration */ + if (data->regs[VTG_SLAVE]) + vtg_write_reg(data->regs[VTG_SLAVE], + VTG_TYPE_SLAVE_BY_EXT0, mode); + + vtg_write_reg(data->regs[VTG_MASTER], VTG_TYPE_MASTER, mode); + + /* reset slave and then master */ + if (data->regs[VTG_SLAVE]) + vtg_reset(data->regs[VTG_SLAVE]); + + vtg_reset(data->regs[VTG_MASTER]); + + /* Enable irq for the vtg vblank synchro */ + if (data->regs[VTG_SLAVE]) + vtg_enable_irq(data->regs[VTG_SLAVE]); + else + vtg_enable_irq(data->regs[VTG_MASTER]); + + if (data->regs[VTG_SLAVE]) + vtg_reg_dump(dev, data->regs[VTG_SLAVE]); + + vtg_reg_dump(dev, data->regs[VTG_MASTER]); + + return 0; +} + +int vtg_register_client(struct device *dev, struct notifier_block *nb) +{ + struct sti_vtg *vtg = dev_get_drvdata(dev); + return raw_notifier_chain_register(&vtg->notifier_list, nb); +} + +int vtg_unregister_client(struct device *dev, struct notifier_block *nb) +{ + struct sti_vtg *vtg = dev_get_drvdata(dev); + return raw_notifier_chain_unregister(&vtg->notifier_list, nb); +} + +static irqreturn_t vtg_irq_thread(int irq, void *arg) +{ + struct sti_vtg *vtg = arg; + struct sti_vtg_data *data = &vtg->data; + void __iomem *regs; + u32 status; + + if (data->regs[VTG_SLAVE]) + regs = data->regs[VTG_SLAVE]; + else + regs = data->regs[VTG_MASTER]; + + status = readl(regs + VTG_HOST_ITS); + + writel(status, regs + VTG_HOST_ITS_BCLR); + /* TODO: check why this sync bus write solves the problem which + * is that without this line, the handler is sometimes called twice, + * first with status = 1 or 2, and immediately after with status=0 + */ + /* sync bus write */ + readl(regs + VTG_HOST_ITS); + + raw_notifier_call_chain(&vtg->notifier_list, + VTG_VBLANK_EVENT, &vtg->type); + + return IRQ_HANDLED; +} + +static const char *vtg_get_name(struct sti_vtg *vtg) +{ + if (vtg->type == VTG_MAIN) + return "main"; + else if (vtg->type == VTG_AUX) + return "aux"; + else + return "?"; +} + +static int vtg_compositor_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct sti_vtg *vtg; + struct resource *res; + char irq_name[32]; + struct sti_vtg_data *data; + int i; + int ret; + + if (!np) + return -ENXIO; + + vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL); + if (!vtg) { + DRM_ERROR("Failed to allocate VTG context\n"); + return -ENOMEM; + } + + vtg->dev = dev; + + /* populate data structure depending on compatibility */ + BUG_ON(!of_match_node(vtg_match_types, np)->data); + + memcpy(&vtg->data, of_match_node(vtg_match_types, np)->data, + sizeof(struct sti_vtg_data)); + + data = &vtg->data; + + /* Get resources */ + for (i = 0; i < data->nb_reg; i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + data->reg_names[i]); + if (!res) { + DRM_ERROR("Invalid resource\n"); + return -ENOMEM; + } + data->regs[i] = devm_ioremap_nocache(dev, + res->start, + resource_size(res)); + if (IS_ERR(data->regs[i])) + return PTR_ERR(data->regs[i]); + } + + vtg->irq = platform_get_irq_byname(pdev, "synchro_irq"); + if (IS_ERR_VALUE(vtg->irq)) { + DRM_ERROR("Failed to get VTG interrupt\n"); + return vtg->irq; + } + + snprintf(irq_name, sizeof(irq_name), "vsync-%s", vtg_get_name(vtg)); + + RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list); + + ret = devm_request_threaded_irq(dev, vtg->irq, NULL, vtg_irq_thread, + IRQF_ONESHOT, irq_name, vtg); + if (IS_ERR_VALUE(ret)) { + DRM_ERROR("Failed to register VTG interrupt\n"); + return ret; + } + + if (of_property_read_bool(np, "vtg-aux")) { + vtg->type = VTG_AUX; + vtg_aux = dev; + } else { + vtg->type = VTG_MAIN; + vtg_main = dev; + } + + platform_set_drvdata(pdev, vtg); + + DRM_INFO("%s VTG %s\n", __func__, vtg_get_name(vtg)); + + return 0; +} + +static const struct of_device_id vtg_match_types[] = { + { + .compatible = "st,stih416-vtg", + .data = &stih416_vtg_data, + }, + { + .compatible = "st,stih407-vtg", + .data = &stih407_vtg_data, + }, + { /* end node */ } +}; + +struct platform_driver sti_vtg_driver = { + .driver = { + .name = "sti-vtg", + .owner = THIS_MODULE, + .of_match_table = vtg_match_types, + }, + .probe = vtg_compositor_probe, +}; diff --git a/drivers/gpu/drm/sti/sti_vtg.h b/drivers/gpu/drm/sti/sti_vtg.h new file mode 100644 index 0000000..da67eb3 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_vtg.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_VTG_H_ +#define _STI_VTG_H_ + +#include <linux/platform_device.h> +#include <drm/drmP.h> + +extern struct device *vtg_main; +extern struct device *vtg_aux; + +int vtg_set_config(struct device *dev, const struct drm_display_mode *mode); +int vtg_register_client(struct device *dev, struct notifier_block *nb); +int vtg_unregister_client(struct device *dev, struct notifier_block *nb); + +#endif diff --git a/drivers/gpu/drm/sti/sti_vtg_utils.c b/drivers/gpu/drm/sti/sti_vtg_utils.c new file mode 100644 index 0000000..06bb4b4 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_vtg_utils.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/platform_device.h> + +#include "sti_vtg_utils.h" +#include "sti_vtg.h" + +struct device *vtg_main; +struct device *vtg_aux; + +int sti_vtg_setconfig(int main_aux, const struct drm_display_mode *mode) +{ + if (main_aux == VTG_MAIN && vtg_main) + return vtg_set_config(vtg_main, mode); + + if (main_aux == VTG_AUX && vtg_aux) + return vtg_set_config(vtg_aux, mode); + + return 1; +} + +int sti_vtg_register_client(int main_aux, struct notifier_block *nb) +{ + if (main_aux == VTG_MAIN && vtg_main) + return vtg_register_client(vtg_main, nb); + + if (main_aux == VTG_AUX && vtg_aux) + return vtg_register_client(vtg_aux, nb); + + return 1; +} + +int sti_vtg_unregister_client(int main_aux, struct notifier_block *nb) +{ + if (main_aux == VTG_MAIN && vtg_main) + return vtg_unregister_client(vtg_main, nb); + + if (main_aux == VTG_AUX && vtg_aux) + return vtg_unregister_client(vtg_aux, nb); + + return 1; +} + +/* + * Active Front Sync Back Active + * Region Porch Porch Region + * <---------------><-------->0<---------><--------><-----------------> + * + * ///////////////| | ///////////////| + * /////////////// | | /////////////// | + * /////////////// |......... ..........|/////////////// | + * 0___________ x/ymin x/ymax + * + * <--[hv]display--> <--[hv]display--> + * <--[hv]sync_start---------> <--[hv]sync_start- + * <--[hv]sync_end-----------------------> <--[hv]sync_end--- + * <--[hv]total------------------------------------> <--[hv]total------ + */ + +/* + * sti_vtg_get_line_number + * + * @mode: display mode to be used + * @y: line + * + * Return the line number according to the display mode taking + * into account the Sync and Back Porch information. + * Video frame line numbers start at 1, y starts at 0. + * In interlaced modes the start line is the field line number of the odd + * field, but y is still defined as a progressive frame. + */ +u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y) +{ + int start_line = mode.vtotal - mode.vsync_start + 1; + + if (mode.flags & DRM_MODE_FLAG_INTERLACE) + start_line *= 2; + + return start_line + y; +} + +/* + * sti_vtg_get_pixel_number + * + * @mode: display mode to be used + * @x: row + * + * Return the pixel number according to the display mode taking + * into account the Sync and Back Porch information. + * Pixels are counted from 0. + */ +u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x) +{ + return mode.htotal - mode.hsync_start + x; +} diff --git a/drivers/gpu/drm/sti/sti_vtg_utils.h b/drivers/gpu/drm/sti/sti_vtg_utils.h new file mode 100644 index 0000000..03d81ba --- /dev/null +++ b/drivers/gpu/drm/sti/sti_vtg_utils.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_VTG_UTILS_H_ +#define _STI_VTG_UTILS_H_ + +#include <drm/drmP.h> + +#define VTG_MAIN 0 +#define VTG_AUX 1 + +#define VTG_VBLANK_EVENT 1 + +int sti_vtg_setconfig(int main_aux, const struct drm_display_mode *mode); +int sti_vtg_register_client(int main_aux, struct notifier_block *nb); +int sti_vtg_unregister_client(int main_aux, struct notifier_block *nb); + +u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y); +u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x); + +#endif

Add driver for HDMI ouput

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Makefile | 5 + drivers/gpu/drm/sti/sti_hdmi.c | 503 +++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_hdmi.h | 195 +++++++++++ drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c | 398 +++++++++++++++++++++++ drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 224 +++++++++++++ 5 files changed, 1325 insertions(+) create mode 100644 drivers/gpu/drm/sti/sti_hdmi.c create mode 100644 drivers/gpu/drm/sti/sti_hdmi.h create mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c create mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c

diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 79fdcb6..2bb3035 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -1,4 +1,9 @@ ccflags-y := -Iinclude/drm

+stidrm-y := sti_hdmi.o \ + sti_hdmi_tx3g0c55phy.o \ + sti_hdmi_tx3g4c28phy.o + +obj-$(CONFIG_DRM_STI) += stidrm.o obj-$(CONFIG_VTAC_STI) += sti_vtac_tx.o sti_vtac_rx.o obj-$(CONFIG_VTG_STI) += sti_vtg.o sti_vtg_utils.o diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c new file mode 100644 index 0000000..5bbee6b --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi.c @@ -0,0 +1,503 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Vincent Abriou vincent.abriou@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/hdmi.h> +#include <linux/module.h> +#include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_edid.h> + +#include "sti_hdmi.h" +#include "sti_vtg_utils.h" + +/* Reference to the hdmi device */ +struct device *hdmi_dev; + +/* + * Helper to write bit field + * + * @addr: register to update + * @val: value to write + * @mask: bit field mask to use + */ +static inline void hdmi_reg_writemask(void __iomem *addr, u32 val, u32 mask) +{ + u32 old = readl(addr); + + val = (val & mask) | (old & ~mask); + writel(val, addr); +} + +/* + * HDMI interrupt handler + * + * @irq: irq number + * @arg: connector structure + */ +static irqreturn_t hdmi_irq_thread(int irq, void *arg) +{ + struct sti_hdmi *hdmi = arg; + u32 status; + + /* read interrupt status */ + status = readl(hdmi->regs + HDMI_INT_STA); + + /* PLL lock interrupt */ + if (status & HDMI_INT_DLL_LCK) { + hdmi->event_received = true; + wake_up_interruptible(&hdmi->wait_event); + } + + /* Hot plug detection */ + if (status & HDMI_INT_HOT_PLUG) { + hdmi->hpd = gpio_get_value(hdmi->hpd_gpio); + if (hdmi->drm_dev) + drm_helper_hpd_irq_event(hdmi->drm_dev); + } + + /* Sw reset completed */ + if (status & HDMI_INT_SW_RST) { + hdmi->event_received = true; + wake_up_interruptible(&hdmi->wait_event); + } + + /* clear interrupt status */ + writel(status, hdmi->regs + HDMI_INT_CLR); + + /* TODO: check why this sync bus write solves the problem which + * is that without this line, the handler is sometimes called twice + */ + /* sync bus write */ + readl(hdmi->regs + HDMI_INT_STA); + + return IRQ_HANDLED; +} + +/* + * Start hdmi phy interface + * + * @hdmi: pointer on the hdmi internal structure + * + * Return -1 if error occurs + */ +static int hdmi_phy_start(struct sti_hdmi *hdmi) +{ + DRM_DEBUG_DRIVER("\n"); + + if (hdmi->tx3g0c55phy) + return sti_hdmi_tx3g0c55phy_start(hdmi); + + return sti_hdmi_tx3g4c28phy_start(hdmi); +} + +/* + * Stop hdmi phy interface + * + * @hdmi: pointer on the hdmi internal structure + */ +static void hdmi_phy_stop(struct sti_hdmi *hdmi) +{ + DRM_DEBUG_DRIVER("\n"); + + if (hdmi->tx3g0c55phy) + sti_hdmi_tx3g0c55phy_stop(hdmi); + else + sti_hdmi_tx3g4c28phy_stop(hdmi); +} + +/* + * Set hdmi active area depending on the drm display mode selected + * + * @hdmi: pointer on the hdmi internal structure + */ +static void hdmi_active_area(struct sti_hdmi *hdmi) +{ + u32 xmin, xmax; + u32 ymin, ymax; + + DRM_DEBUG_DRIVER("\n"); + + /* + * Active Front Sync Back Active + * Region Porch Porch Region + * <---------------><-------->0<---------><--------><-----------------> + * + * ///////////////| | ///////////////| + * /////////////// | | /////////////// | + * /////////////// |......... ..........|/////////////// | + * 0___________ x/ymin x/ymax + * + * <--[hv]display--> <--[hv]display--> + * <--[hv]sync_start---------> <--[hv]sync_start- + * <--[hv]sync_end-----------------------> <--[hv]sync_end--- + * <--[hv]total------------------------------------> <--[hv]total------ + */ + + xmin = sti_vtg_get_pixel_number(hdmi->mode, 0); + xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay - 1); + ymin = sti_vtg_get_line_number(hdmi->mode, 0); + ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); + + writel(xmin, hdmi->regs + HDMI_ACTIVE_VID_XMIN); + writel(xmax, hdmi->regs + HDMI_ACTIVE_VID_XMAX); + writel(ymin, hdmi->regs + HDMI_ACTIVE_VID_YMIN); + writel(ymax, hdmi->regs + HDMI_ACTIVE_VID_YMAX); + + DRM_DEBUG_DRIVER("xmin=%d xmax=%d ymin=%d ymax=%d\n", + xmin, xmax, ymin, ymax); +} + +/* + * Overall hdmi configuration + * + * @hdmi: pointer on the hdmi internal structure + */ +static void hdmi_config(struct sti_hdmi *hdmi) +{ + u32 val; + u32 mask; + + DRM_DEBUG_DRIVER("\n"); + + /* Clear overrun and underrun fifo */ + mask = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; + val = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; + + /* Enable HDMI mode not DVI */ + mask |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS; + val |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS; + + /* Enable sink term detection */ + mask |= HDMI_CFG_SINK_TERM_DET_EN; + val |= HDMI_CFG_SINK_TERM_DET_EN; + + /* Set Hsync polarity */ + if ((hdmi->mode.flags && DRM_MODE_FLAG_NHSYNC) + == DRM_MODE_FLAG_NHSYNC) { + DRM_DEBUG_DRIVER("H Sync Negative\n"); + mask |= HDMI_CFG_H_SYNC_POL_NEG; + val |= HDMI_CFG_H_SYNC_POL_NEG; + } + + /* Set Vsync polarity */ + if ((hdmi->mode.flags && DRM_MODE_FLAG_NVSYNC) + == DRM_MODE_FLAG_NVSYNC) { + DRM_DEBUG_DRIVER("V Sync Negative\n"); + mask |= HDMI_CFG_V_SYNC_POL_NEG; + val |= HDMI_CFG_V_SYNC_POL_NEG; + } + + /* Enable HDMI */ + mask |= HDMI_CFG_DEVICE_EN; + val |= HDMI_CFG_DEVICE_EN; + + hdmi_reg_writemask(hdmi->regs + HDMI_CFG, val, mask); +} + +/* + * Prepare and configure the AVI infoframe + * + * AVI infoframe are transmitted at least once per two video field and + * contains information about HDMI transmission mode such as color space, + * colorimetry, ... + * + * @hdmi: pointer on the hdmi internal structure + * + * Return negative value if error occurs + */ +static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi) +{ + struct drm_display_mode *mode = &hdmi->mode; + struct hdmi_avi_infoframe infoframe; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; + u8 *frame = buffer + HDMI_INFOFRAME_HEADER_SIZE - 1; + u32 val; + u32 mask; + int ret; + + DRM_DEBUG_DRIVER("\n"); + + ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode); + if (ret < 0) { + DRM_ERROR("failed to setup AVI infoframe: %d\n", ret); + return ret; + } + + /* TODO: remove static infoframe configuration */ + infoframe.colorspace = HDMI_COLORSPACE_RGB; + infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; + infoframe.colorimetry = HDMI_COLORIMETRY_NONE; + infoframe.pixel_repeat = 0; + + ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer)); + if (ret < 0) { + DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); + return ret; + } + + /* Disable transmission slot for AVI infoframe */ + val = HDMI_IFRAME_DISABLED; + mask = HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, HDMI_IFRAME_SLOT_AVI); + hdmi_reg_writemask(hdmi->regs + HDMI_SW_DI_CFG, val, mask); + + /* Infoframe header */ + val = buffer[0x0]; + val |= buffer[0x1] << 8; + val |= buffer[0x2] << 16; + writel(val, hdmi->regs + HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI)); + /* Infoframe packet bytes */ + val = frame[0x0]; + val |= frame[0x1] << 8; + val |= frame[0x2] << 16; + val |= frame[0x3] << 24; + writel(val, hdmi->regs + HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI)); + val = frame[0x4]; + val |= frame[0x5] << 8; + val |= frame[0x6] << 16; + val |= frame[0x7] << 24; + writel(val, hdmi->regs + HDMI_SW_DI_N_PKT_WORD1(HDMI_IFRAME_SLOT_AVI)); + val = frame[0x8]; + val |= frame[0x9] << 8; + val |= frame[0xA] << 16; + val |= frame[0xB] << 24; + writel(val, hdmi->regs + HDMI_SW_DI_N_PKT_WORD2(HDMI_IFRAME_SLOT_AVI)); + val = frame[0xC]; + val |= frame[0xD] << 8; + writel(val, hdmi->regs + HDMI_SW_DI_N_PKT_WORD3(HDMI_IFRAME_SLOT_AVI)); + + /* Enable transmission slot for AVI infoframe */ + /* According to the hdmi specification, AVI infoframe should be + * transmitted at least once per two video fields */ + val = HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_FIELD, HDMI_IFRAME_SLOT_AVI); + mask = HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, HDMI_IFRAME_SLOT_AVI); + hdmi_reg_writemask(hdmi->regs + HDMI_SW_DI_CFG, val, mask); + + return 0; +} + +/* + * Software reset of the hdmi subsystem + * + * @hdmi: pointer on the hdmi internal structure + * + * Return -1 if error occurs + */ +#define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */ +static int hdmi_swreset(struct sti_hdmi *hdmi) +{ + u32 val; + u32 mask; + + DRM_DEBUG_DRIVER("\n"); + + /* Enable hdmi_audio clock only during hdmi reset */ + if (clk_prepare_enable(hdmi->clk_audio)) + DRM_INFO("Failed to prepare/enable hdmi_audio clk\n"); + + /* Sw reset */ + mask = HDMI_CFG_SW_RST_EN; + val = HDMI_CFG_SW_RST_EN; + + hdmi->event_received = false; + hdmi_reg_writemask(hdmi->regs + HDMI_CFG, val, mask); + + /* Wait reset completed */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received == true, + msecs_to_jiffies + (HDMI_TIMEOUT_SWRESET)); + + /* + * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is + * set to '1' and clk_audio is running. + */ + if ((readl(hdmi->regs + HDMI_STA) & HDMI_STA_SW_RST) == 0) + DRM_INFO("Warning: HDMI sw reset timeout occurs\n"); + + mask = HDMI_CFG_SW_RST_EN; + val = ~HDMI_CFG_SW_RST_EN; + hdmi_reg_writemask(hdmi->regs + HDMI_CFG, val, mask); + + /* Disable hdmi_audio clock. Not used anymore for drm purpose. */ + clk_disable_unprepare(hdmi->clk_audio); + + return 0; +} + +/* + * Attach the I2C ddc client to allow hdmi i2c communication + * + * @ddc: i2c client + */ +static struct i2c_client *hdmi_ddc; +void sti_hdmi_attach_ddc_client(struct i2c_client *ddc) +{ + DRM_DEBUG_DRIVER("\n"); + + if (ddc) + hdmi_ddc = ddc; +} + +/* + * Get modes from edid + * + * @drm_connector: pointer on the drm connector + */ +static int sti_hdmi_get_modes(struct drm_connector *drm_connector) +{ + struct edid *edid; + int count; + + DRM_DEBUG_DRIVER("\n"); + + if ((!hdmi_ddc) || (!hdmi_ddc->adapter)) + goto fail; + + edid = drm_get_edid(drm_connector, hdmi_ddc->adapter); + if (!edid) + goto fail; + + count = drm_add_edid_modes(drm_connector, edid); + if (count) + drm_mode_connector_update_edid_property(drm_connector, edid); + else + DRM_ERROR("Add edid modes failed\n"); + + kfree(edid); + return count; + +fail: + DRM_ERROR("Can not read HDMI EDID\n"); + return -1; +} + +static int sti_hdmi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sti_hdmi *hdmi; + struct device_node *np = dev->of_node; + struct resource *res; + int ret; + + DRM_INFO("%s\n", __func__); + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) { + DRM_ERROR("Failed to allocate memory for hdmi\n"); + return -ENOMEM; + } + + hdmi->dev = pdev->dev; + + /* Get resources */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg"); + if (!res) { + DRM_ERROR("Invalid hdmi resource\n"); + return -ENOMEM; + } + hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + if (IS_ERR(hdmi->regs)) + return PTR_ERR(hdmi->regs); + + if (of_device_is_compatible(np, "st,stih416-hdmi")) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "syscfg"); + if (!res) { + DRM_ERROR("Invalid syscfg resource\n"); + return -ENOMEM; + } + hdmi->syscfg = devm_ioremap_nocache(dev, res->start, + resource_size(res)); + if (IS_ERR(hdmi->syscfg)) + return PTR_ERR(hdmi->syscfg); + + hdmi->tx3g0c55phy = true; + } + + /* Get clock resources */ + hdmi->clk_pix = devm_clk_get(dev, "hdmi_pix"); + if (IS_ERR(hdmi->clk_pix)) { + DRM_ERROR("Cannot get hdmi_pix clock\n"); + return PTR_ERR(hdmi->clk_pix); + } + + hdmi->clk_tmds = devm_clk_get(dev, "hdmi_tmds"); + if (IS_ERR(hdmi->clk_tmds)) { + DRM_ERROR("Cannot get hdmi_tmds clock\n"); + return PTR_ERR(hdmi->clk_tmds); + } + + hdmi->clk_phy = devm_clk_get(dev, "hdmi_phy"); + if (IS_ERR(hdmi->clk_phy)) { + DRM_ERROR("Cannot get hdmi_phy clock\n"); + return PTR_ERR(hdmi->clk_phy); + } + + hdmi->clk_audio = devm_clk_get(dev, "hdmi_audio"); + if (IS_ERR(hdmi->clk_audio)) { + DRM_ERROR("Cannot get hdmi_audio clock\n"); + return PTR_ERR(hdmi->clk_audio); + } + + hdmi->hpd_gpio = of_get_named_gpio(np, "hdmi,hpd-gpio", 0); + if (hdmi->hpd_gpio < 0) { + DRM_ERROR("Failed to get hdmi hpd-gpio\n"); + return -EIO; + } + + hdmi->hpd = gpio_get_value(hdmi->hpd_gpio); + + init_waitqueue_head(&hdmi->wait_event); + + /* Get irq ressources */ + hdmi->irq = platform_get_irq_byname(pdev, "hdmi_irq"); + + ret = devm_request_threaded_irq(dev, hdmi->irq, NULL, + hdmi_irq_thread, IRQF_ONESHOT, + "hdmi_irq", hdmi); + if (ret) { + DRM_ERROR("Failed to register hdmi interrupt\n"); + return ret; + } + + /* Get reset resources */ + hdmi->reset = devm_reset_control_get(dev, "hdmi"); + /* Take hdmi out of reset */ + if (!IS_ERR(hdmi->reset)) + reset_control_deassert(hdmi->reset); + + hdmi_dev = &hdmi->dev; + + platform_set_drvdata(pdev, hdmi); + + return 0; +} + +static struct of_device_id hdmi_match_types[] = { + { + .compatible = "st,stih416-hdmi", + }, + { + .compatible = "st,stih407-hdmi", + }, + { /* end node */ } +}; + +struct platform_driver sti_hdmi_driver = { + .driver = { + .name = "sti-hdmi", + .owner = THIS_MODULE, + .of_match_table = hdmi_match_types, + }, + .probe = sti_hdmi_probe, +}; + +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/sti/sti_hdmi.h b/drivers/gpu/drm/sti/sti_hdmi.h new file mode 100644 index 0000000..c14c683 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Vincent Abriou vincent.abriou@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_HDMI_H_ +#define _STI_HDMI_H_ + +#include <linux/platform_device.h> + +#include <drm/drmP.h> + +/* HDMI v2.9 macro cell */ +#define HDMI_CFG 0x0000 +#define HDMI_INT_EN 0x0004 +#define HDMI_INT_STA 0x0008 +#define HDMI_INT_CLR 0x000C +#define HDMI_STA 0x0010 +#define HDMI_ACTIVE_VID_XMIN 0x0100 +#define HDMI_ACTIVE_VID_XMAX 0x0104 +#define HDMI_ACTIVE_VID_YMIN 0x0108 +#define HDMI_ACTIVE_VID_YMAX 0x010C +#define HDMI_DFLT_CHL0_DAT 0x0110 +#define HDMI_DFLT_CHL1_DAT 0x0114 +#define HDMI_DFLT_CHL2_DAT 0x0118 +#define HDMI_SW_DI_1_HEAD_WORD 0x0210 +#define HDMI_SW_DI_1_PKT_WORD0 0x0214 +#define HDMI_SW_DI_1_PKT_WORD1 0x0218 +#define HDMI_SW_DI_1_PKT_WORD2 0x021C +#define HDMI_SW_DI_1_PKT_WORD3 0x0220 +#define HDMI_SW_DI_1_PKT_WORD4 0x0224 +#define HDMI_SW_DI_1_PKT_WORD5 0x0228 +#define HDMI_SW_DI_1_PKT_WORD6 0x022C +#define HDMI_SW_DI_CFG 0x0230 + +#define HDMI_IFRAME_SLOT_AVI 1 + +#define XCAT(prefix, x, suffix) prefix ## x ## suffix +#define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD) +#define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0) +#define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1) +#define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2) +#define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3) +#define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4) +#define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5) +#define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6) + +#define HDMI_IFRAME_DISABLED 0x0 +#define HDMI_IFRAME_SINGLE_SHOT 0x1 +#define HDMI_IFRAME_FIELD 0x2 +#define HDMI_IFRAME_FRAME 0x3 +#define HDMI_IFRAME_MASK 0x3 +#define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */ + +#define HDMI_CFG_DEVICE_EN_SHIFT 0 +#define HDMI_CFG_DEVICE_EN (1 << HDMI_CFG_DEVICE_EN_SHIFT) +#define HDMI_CFG_HDMI_NOT_DVI_SHIFT 1 +#define HDMI_CFG_HDMI_NOT_DVI (1 << HDMI_CFG_HDMI_NOT_DVI_SHIFT) +#define HDMI_CFG_HDCP_EN_SHIFT 2 +#define HDMI_CFG_HDCP_EN (1 << HDMI_CFG_HDCP_EN_SHIFT) +#define HDMI_CFG_ESS_NOT_OESS_SHIFT 3 +#define HDMI_CFG_ESS_NOT_OESS (1 << HDMI_CFG_ESS_NOT_OESS_SHIFT) +#define HDMI_CFG_H_SYNC_POL_NEG_SHIFT 4 +#define HDMI_CFG_H_SYNC_POL_NEG (1 << HDMI_CFG_H_SYNC_POL_NEG_SHIFT) +#define HDMI_CFG_SINK_TERM_DET_EN_SHIFT 5 +#define HDMI_CFG_SINK_TERM_DET_EN (1 << HDMI_CFG_SINK_TERM_DET_EN_SHIFT) +#define HDMI_CFG_V_SYNC_POL_NEG_SHIFT 6 +#define HDMI_CFG_V_SYNC_POL_NEG (1 << HDMI_CFG_V_SYNC_POL_NEG_SHIFT) +#define HDMI_CFG_422_EN_SHIFT 8 +#define HDMI_CFG_422_EN (1 << HDMI_CFG_422_EN_SHIFT) +#define HDMI_CFG_FIFO_OVERRUN_CLR_SHIFT 12 +#define HDMI_CFG_FIFO_OVERRUN_CLR (1 << HDMI_CFG_FIFO_OVERRUN_CLR_SHIFT) +#define HDMI_CFG_FIFO_UNDERRUN_CLR_SHIFT 13 +#define HDMI_CFG_FIFO_UNDERRUN_CLR (1 << HDMI_CFG_FIFO_UNDERRUN_CLR_SHIFT) +#define HDMI_CFG_SW_RST_EN_SHIFT 31 +#define HDMI_CFG_SW_RST_EN (1 << HDMI_CFG_SW_RST_EN_SHIFT) + +#define HDMI_INT_GLOBAL (1 << 0) +#define HDMI_INT_SW_RST (1 << 1) +#define HDMI_INT_IFRAME (1 << 2) +#define HDMI_INT_PIX_CAP (1 << 3) +#define HDMI_INT_HOT_PLUG (1 << 4) +#define HDMI_INT_DLL_LCK (1 << 5) +#define HDMI_INT_NEW_FRAME (1 << 6) +#define HDMI_INT_GENCTRL_PKT (1 << 7) +#define HDMI_INT_SPDIF_FIFO_OVERRUN (1 << 8) +#define HDMI_INT_VID_FIFO_UNDERRUN (1 << 9) +#define HDMI_INT_VID_FIFO_OVERRUN (1 << 10) +#define HDMI_INT_SINK_TERM_PRESENT (1 << 11) +#define HDMI_INT_DI_2 (1 << 16) +#define HDMI_INT_DI_3 (1 << 17) +#define HDMI_INT_DI_4 (1 << 18) +#define HDMI_INT_DI_5 (1 << 19) +#define HDMI_INT_DI_6 (1 << 20) +#define HDMI_INT_DI_DMA_VSYNC_DONE (1 << 21) +#define HDMI_INT_DI_VSYNC_DONE (1 << 22) + +#define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \ + | HDMI_INT_DLL_LCK \ + | HDMI_INT_HOT_PLUG \ + | HDMI_INT_GLOBAL) + +#define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \ + | HDMI_INT_GENCTRL_PKT \ + | HDMI_INT_NEW_FRAME \ + | HDMI_INT_DLL_LCK \ + | HDMI_INT_HOT_PLUG \ + | HDMI_INT_PIX_CAP \ + | HDMI_INT_SW_RST \ + | HDMI_INT_GLOBAL) + +#define HDMI_STA_SW_RST_SHIFT 1 +#define HDMI_STA_SW_RST (1 << HDMI_STA_SW_RST_SHIFT) +#define HDMI_STA_PIX_CAP_SHIFT 3 +#define HDMI_STA_PIX_CAP (1 << HDMI_STA_PIX_CAP_SHIFT) +#define HDMI_STA_HOT_PLUG_SHIFT 4 +#define HDMI_STA_HOT_PLUG (1 << HDMI_STA_HOT_PLUG_SHIFT) +#define HDMI_STA_DLL_LCK_SHIFT 5 +#define HDMI_STA_DLL_LCK (1 << HDMI_STA_DLL_LCK_SHIFT) +#define HDMI_STA_SINK_TERM_SHIFT 6 +#define HDMI_STA_SINK_TERM (1 << HDMI_STA_SINK_TERM_SHIFT) +#define HDMI_STA_FIFO_SAMPLES_SHIFT 8 +#define HDMI_STA_FIFO_SAMPLES (0x1F << HDMI_STA_FIFO_SAMPLES_SHIFT) + +/* + * STI hdmi structure + * + * @dev: driver device + * @drm_dev: pointer to drm device + * @mode: current display mode selected + * @regs: hdmi register + * @syscfg: syscfg register for pll rejection configuration + * @clk_pix: hdmi pixel clock + * @clk_tmds: hdmi tmds clock + * @clk_phy: hdmi phy clock + * @clk_audio: hdmi audio clock + * @irq: hdmi interrupt number + * @tx3g0c55phy: true if 3g0c55phy is supported + * @enabled: true if hdmi is enabled else false + * @hpd_gpio: hdmi hot plug detect gpio number + * @hpd: hot plug detect status + * @wait_event: wait event + * @event_received: wait event status + * @reset: reset control of the hdmi phy + */ +struct sti_hdmi { + struct device dev; + struct drm_device *drm_dev; + struct drm_display_mode mode; + void __iomem *regs; + void __iomem *syscfg; + struct clk *clk_pix; + struct clk *clk_tmds; + struct clk *clk_phy; + struct clk *clk_audio; + int irq; + bool tx3g0c55phy; + bool enabled; + int hpd_gpio; + bool hpd; + wait_queue_head_t wait_event; + bool event_received; + struct reset_control *reset; +}; + +/* hdmi phy config structure + * + * A pointer to an array of these structures is passed to a TMDS (HDMI) output + * via the control interface to provide board and SoC specific + * configurations of the HDMI PHY. Each entry in the array specifies a hardware + * specific configuration for a given TMDS clock frequency range. + * + * @min_tmds_freq: Lower bound of TMDS clock frequency this entry applies to + * @max_tmds_freq: Upper bound of TMDS clock frequency this entry applies to + * @config: SoC specific register configuration + */ +struct hdmi_phy_config { + u32 min_tmds_freq; + u32 max_tmds_freq; + u32 config[4]; +}; + +void sti_hdmi_attach_ddc_client(struct i2c_client *ddc); + +int sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi); +void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi); +void sti_hdmi_tx3g0c55phy_show(struct sti_hdmi *hdmi, struct seq_file *m); + +int sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi); +void sti_hdmi_tx3g4c28phy_stop(struct sti_hdmi *hdmi); +void sti_hdmi_tx3g4c28phy_show(struct sti_hdmi *hdmi, struct seq_file *m); + +extern struct i2c_driver ddc_driver; +#endif diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c new file mode 100644 index 0000000..547e9ee --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c @@ -0,0 +1,398 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Vincent Abriou vincent.abriou@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include "sti_hdmi.h" + +#define HDMI_SRZ_PLL_CFG 0x0504 +#define HDMI_SRZ_TAP_1 0x0508 +#define HDMI_SRZ_TAP_2 0x050C +#define HDMI_SRZ_TAP_3 0x0510 +#define HDMI_SRZ_CTRL 0x0514 + +#define HDMI_SRZ_PLL_CFG_POWER_DOWN (1 << 0) +#define HDMI_SRZ_PLL_CFG_VCOR_SHIFT 1 +#define HDMI_SRZ_PLL_CFG_VCOR_425MHZ 0 +#define HDMI_SRZ_PLL_CFG_VCOR_850MHZ 1 +#define HDMI_SRZ_PLL_CFG_VCOR_1700MHZ 2 +#define HDMI_SRZ_PLL_CFG_VCOR_3000MHZ 3 +#define HDMI_SRZ_PLL_CFG_VCOR_MASK 3 +#define HDMI_SRZ_PLL_CFG_VCOR(x) (x << HDMI_SRZ_PLL_CFG_VCOR_SHIFT) +#define HDMI_SRZ_PLL_CFG_NDIV_SHIFT 8 +#define HDMI_SRZ_PLL_CFG_NDIV_MASK (0x1F << HDMI_SRZ_PLL_CFG_NDIV_SHIFT) +#define HDMI_SRZ_PLL_CFG_MODE_SHIFT 16 +#define HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ 0x1 +#define HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ 0x4 +#define HDMI_SRZ_PLL_CFG_MODE_27_MHZ 0x5 +#define HDMI_SRZ_PLL_CFG_MODE_33_75_MHZ 0x6 +#define HDMI_SRZ_PLL_CFG_MODE_40_5_MHZ 0x7 +#define HDMI_SRZ_PLL_CFG_MODE_54_MHZ 0x8 +#define HDMI_SRZ_PLL_CFG_MODE_67_5_MHZ 0x9 +#define HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ 0xA +#define HDMI_SRZ_PLL_CFG_MODE_81_MHZ 0xB +#define HDMI_SRZ_PLL_CFG_MODE_82_5_MHZ 0xC +#define HDMI_SRZ_PLL_CFG_MODE_108_MHZ 0xD +#define HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ 0xE +#define HDMI_SRZ_PLL_CFG_MODE_165_MHZ 0xF +#define HDMI_SRZ_PLL_CFG_MODE_MASK 0xF +#define HDMI_SRZ_PLL_CFG_MODE(x) (x << HDMI_SRZ_PLL_CFG_MODE_SHIFT) + +#define HDMI_SRZ_CTRL_POWER_DOWN (1 << 0) +#define HDMI_SRZ_CTRL_EXTERNAL_DATA_EN (1 << 1) + +/* sysconf registers */ +#define HDMI_REJECTION_PLL_CONFIGURATION 0x0858 /* SYSTEM_CONFIG2534 */ +#define HDMI_REJECTION_PLL_STATUS 0x0948 /* SYSTEM_CONFIG2594 */ + +#define REJECTION_PLL_HDMI_ENABLE_SHIFT 0 +#define REJECTION_PLL_HDMI_ENABLE_MASK (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT) +#define REJECTION_PLL_HDMI_PDIV_SHIFT 24 +#define REJECTION_PLL_HDMI_PDIV_MASK (0x7 << REJECTION_PLL_HDMI_PDIV_SHIFT) +#define REJECTION_PLL_HDMI_NDIV_SHIFT 16 +#define REJECTION_PLL_HDMI_NDIV_MASK (0xFF << REJECTION_PLL_HDMI_NDIV_SHIFT) +#define REJECTION_PLL_HDMI_MDIV_SHIFT 8 +#define REJECTION_PLL_HDMI_MDIV_MASK (0xFF << REJECTION_PLL_HDMI_MDIV_SHIFT) + +#define REJECTION_PLL_HDMI_REJ_PLL_LOCK (0x1 << 0) + +#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */ + +#define HDMI_WAIT_PLL_REJECTION_STATUS 1000 + +/* pll mode structure + * + * A pointer to an array of these structures is passed to a TMDS (HDMI) output + * via the control interface to provide board and SoC specific + * configurations of the HDMI PHY. Each entry in the array specifies a hardware + * specific configuration for a given TMDS clock frequency range. The array + * should be terminated with an entry that has all fields set to zero. + * + * @min: Lower bound of TMDS clock frequency this entry applies to + * @max: Upper bound of TMDS clock frequency this entry applies to + * @mode: SoC specific register configuration + */ +struct pllmode { + u32 min; + u32 max; + u32 mode; +}; +#define NB_PLL_MODE 7 +static struct pllmode pllmodes[NB_PLL_MODE] = { + {13500000, 13513500, HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ}, + {25174800, 25200000, HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ}, + {27000000, 27027000, HDMI_SRZ_PLL_CFG_MODE_27_MHZ}, + {54000000, 54054000, HDMI_SRZ_PLL_CFG_MODE_54_MHZ}, + {72000000, 74250000, HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ}, + {108000000, 108108000, HDMI_SRZ_PLL_CFG_MODE_108_MHZ}, + {148351648, 297000000, HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ} +}; + +#define NB_HDMI_PHY_CONFIG 5 +static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = { + {0, 40000000, {0x00101010, 0x00101010, 0x00101010, 0x02} }, + {40000000, 140000000, {0x00111111, 0x00111111, 0x00111111, 0x02} }, + {140000000, 160000000, {0x00131313, 0x00101010, 0x00101010, 0x02} }, + {160000000, 250000000, {0x00131313, 0x00111111, 0x00111111, 0x03FE} }, + {250000000, 300000000, {0x00151515, 0x00101010, 0x00101010, 0x03FE} }, +}; + +/* + * Helper to write bit field + * + * @addr: register to update + * @val: value to write + * @mask: bit field mask to use + */ +static inline void reg_writemask(void __iomem *addr, u32 val, u32 mask) +{ + u32 old = readl(addr); + + val = (val & mask) | (old & ~mask); + writel(val, addr); +} + +/* + * Enable the old BCH/rejection PLL is now reused to provide the CLKPXPLL + * clock input to the new PHY PLL that generates the serializer clock + * (TMDS*10) and the TMDS clock which is now fed back into the HDMI + * formatter instead of the TMDS clock line from ClockGenB. + * + * @hdmi: pointer on the hdmi internal structure + * + * Return -1 if error occurs + */ +static int enable_pll_rejection(struct sti_hdmi *hdmi) +{ + int inputclock; + u32 mdiv; + u32 ndiv; + u32 pdiv; + u32 mask; + u32 val; + int i; + + DRM_DEBUG_DRIVER("\n"); + + inputclock = hdmi->mode.clock * 1000; + + DRM_DEBUG_DRIVER("hdmi rejection pll input clock = %dHz\n", inputclock); + + /* Force to power down the HDMI rejection PLL */ + mask = REJECTION_PLL_HDMI_ENABLE_MASK; + val = 0x0 << REJECTION_PLL_HDMI_ENABLE_SHIFT; + reg_writemask(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION, + val, mask); + + /* Check the HDMI rejection PLL is really down */ + for (i = 0; i < HDMI_WAIT_PLL_REJECTION_STATUS; i++) { + val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS); + if ((val & REJECTION_PLL_HDMI_REJ_PLL_LOCK) == 0) + break; + } + if (i == HDMI_WAIT_PLL_REJECTION_STATUS) { + DRM_ERROR("hdmi rejection pll is not well powered down\n"); + return -1; + } + + /* Power up the HDMI rejection PLL */ + /* + * Note: On this SoC (stiH416) we are forced to have the input clock + * be equal to the HDMI pixel clock. + * + * The values here have been suggested by validation however they are + * still provisional and subject to change. + * + * PLLout = (Fin*Mdiv) / ((2 * Ndiv) / 2^Pdiv) + */ + if (inputclock < 50000000) { + /* + * For slower clocks we need to multiply more to keep the + * internal VCO frequency within the physical specification + * of the PLL. + */ + pdiv = 4; + ndiv = 240; + mdiv = 30; + } else { + pdiv = 2; + ndiv = 60; + mdiv = 30; + } + + mask = REJECTION_PLL_HDMI_PDIV_MASK | + REJECTION_PLL_HDMI_NDIV_MASK | + REJECTION_PLL_HDMI_MDIV_MASK | REJECTION_PLL_HDMI_ENABLE_MASK; + val = (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) | + (ndiv << REJECTION_PLL_HDMI_NDIV_SHIFT) | + (mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) | + (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT); + reg_writemask(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION, + val, mask); + + /* Check the HDMI rejection PLL is really up */ + for (i = 0; i < HDMI_WAIT_PLL_REJECTION_STATUS; i++) { + val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS); + if ((val & REJECTION_PLL_HDMI_REJ_PLL_LOCK) != 0) + break; + } + if (i == HDMI_WAIT_PLL_REJECTION_STATUS) { + DRM_ERROR("hdmi rejection pll is not well powered up\n"); + return -1; + } + + DRM_DEBUG_DRIVER("hdmi rejection pll locked\n"); + + return 0; +} + +/* + * Disable the pll rejection + * + * @hdmi: pointer on the hdmi internal structure + */ +static void disable_pll_rejection(struct sti_hdmi *hdmi) +{ + int i; + u32 val; + u32 mask; + + DRM_DEBUG_DRIVER("\n"); + + mask = REJECTION_PLL_HDMI_ENABLE_MASK; + val = 0x0 << REJECTION_PLL_HDMI_ENABLE_SHIFT; + reg_writemask(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION, + val, mask); + + /* Check the HDMI rejection PLL is really down */ + for (i = 0; i < HDMI_WAIT_PLL_REJECTION_STATUS; i++) { + val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS); + if ((val & REJECTION_PLL_HDMI_REJ_PLL_LOCK) == 0) + break; + } + if (i == HDMI_WAIT_PLL_REJECTION_STATUS) + DRM_ERROR("hdmi rejection pll is not well powered down\n"); + else + DRM_DEBUG_DRIVER("hdmi rejection pll is powered down\n"); +} + +/* + * Start hdmi phy macro cell tx3g0c55 + * + * @hdmi: pointer on the hdmi internal structure + * + * Return -1 if error occurs + */ +int sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi) +{ + u32 ckpxpll = hdmi->mode.clock * 1000; + u32 tmdsck; + u32 freqvco; + u32 pllctrl = 0; + u32 val; + int i; + + if (enable_pll_rejection(hdmi)) + return -1; + + DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll); + + /* TODO: manage DeepColor (30, 36 and 48 bits) and pixel repetition */ + + /* Assuming no pixel repetition and 24bits color */ + tmdsck = ckpxpll; + pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT; + + /* + * Setup the PLL mode parameter based on the ckpxpll. If we haven't got + * a clock frequency supported by one of the specific PLL modes then we + * will end up using the generic mode (0) which only supports a 10x + * multiplier, hence only 24bit color. + */ + for (i = 0; i < NB_PLL_MODE; i++) { + if (ckpxpll >= pllmodes[i].min && ckpxpll <= pllmodes[i].max) + pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode); + } + + freqvco = tmdsck * 10; + if (freqvco <= 425000000UL) + pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ); + else if (freqvco <= 850000000UL) + pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ); + else if (freqvco <= 1700000000UL) + pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ); + else if (freqvco <= 2970000000UL) + pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ); + else { + DRM_ERROR("PHY serializer clock out of range\n"); + goto err; + } + + /* + * Configure and power up the PHY PLL + */ + hdmi->event_received = false; + DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl); + writel(pllctrl, hdmi->regs + HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received == true, + msecs_to_jiffies + (HDMI_TIMEOUT_PLL_LOCK)); + + if ((readl(hdmi->regs + HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { + DRM_ERROR("hdmi phy pll not locked\n"); + goto err; + } + + DRM_DEBUG_DRIVER("got PHY PLL Lock\n"); + + /* + * To configure the source termination and pre-emphasis appropriately + * for different high speed TMDS clock frequencies a phy configuration + * table must be provided, tailored to the SoC and board combination. + */ + for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) { + if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) && + (hdmiphy_config[i].max_tmds_freq >= tmdsck)) { + val = hdmiphy_config[i].config[0]; + writel(val, hdmi->regs + HDMI_SRZ_TAP_1); + val = hdmiphy_config[i].config[1]; + writel(val, hdmi->regs + HDMI_SRZ_TAP_2); + val = hdmiphy_config[i].config[2]; + writel(val, hdmi->regs + HDMI_SRZ_TAP_3); + val = hdmiphy_config[i].config[3]; + val |= HDMI_SRZ_CTRL_EXTERNAL_DATA_EN; + val &= ~HDMI_SRZ_CTRL_POWER_DOWN; + writel(val, hdmi->regs + HDMI_SRZ_CTRL); + + DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x 0x%x\n", + hdmiphy_config[i].config[0], + hdmiphy_config[i].config[1], + hdmiphy_config[i].config[2], + hdmiphy_config[i].config[3]); + return 0; + } + } + + /* + * Default, power up the serializer with no pre-emphasis or source + * termination. + */ + writel(0x0, hdmi->regs + HDMI_SRZ_TAP_1); + writel(0x0, hdmi->regs + HDMI_SRZ_TAP_2); + writel(0x0, hdmi->regs + HDMI_SRZ_TAP_3); + writel(HDMI_SRZ_CTRL_EXTERNAL_DATA_EN, hdmi->regs + HDMI_SRZ_CTRL); + + return 0; + +err: + disable_pll_rejection(hdmi); + + return -1; +} + +/* + * Stop hdmi phy macro cell tx3g0c55 + * + * @hdmi: pointer on the hdmi internal structure + */ +void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi) +{ + DRM_DEBUG_DRIVER("\n"); + + hdmi->event_received = false; + + writel(HDMI_SRZ_CTRL_POWER_DOWN, hdmi->regs + HDMI_SRZ_CTRL); + writel(HDMI_SRZ_PLL_CFG_POWER_DOWN, hdmi->regs + HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received == true, + msecs_to_jiffies + (HDMI_TIMEOUT_PLL_LOCK)); + + if ((readl(hdmi->regs + HDMI_STA) & HDMI_STA_DLL_LCK) == 1) + DRM_ERROR("hdmi phy pll not well disabled\n"); + else + DRM_DEBUG_DRIVER("hdmi phy pll disabled\n"); + + disable_pll_rejection(hdmi); +} + +/* + * Debugfs + */ +#define HDMI_DBG_DUMP(reg) seq_printf(m, "\n %-25s 0x%08X", #reg, \ + readl(hdmi->regs + reg)) +void sti_hdmi_tx3g0c55phy_show(struct sti_hdmi *hdmi, struct seq_file *m) +{ + HDMI_DBG_DUMP(HDMI_SRZ_PLL_CFG); + HDMI_DBG_DUMP(HDMI_SRZ_TAP_1); + HDMI_DBG_DUMP(HDMI_SRZ_TAP_2); + HDMI_DBG_DUMP(HDMI_SRZ_TAP_3); + HDMI_DBG_DUMP(HDMI_SRZ_CTRL); + seq_puts(m, "\n"); +} diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c b/drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c new file mode 100644 index 0000000..6e0bc2c --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Vincent Abriou vincent.abriou@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include "sti_hdmi.h" + +#define HDMI_SRZ_CFG 0x504 +#define HDMI_SRZ_PLL_CFG 0x510 +#define HDMI_SRZ_ICNTL 0x518 +#define HDMI_SRZ_CALCODE_EXT 0x520 + +#define HDMI_SRZ_CFG_EN (1L<<0) +#define HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT (1L<<1) +#define HDMI_SRZ_CFG_EXTERNAL_DATA (1L<<16) +#define HDMI_SRZ_CFG_RBIAS_EXT (1L<<17) +#define HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION (1L<<18) +#define HDMI_SRZ_CFG_EN_BIASRES_DETECTION (1L<<19) +#define HDMI_SRZ_CFG_EN_SRC_TERMINATION (1L<<24) + +#define HDMI_SRZ_CFG_INTERNAL_MASK (HDMI_SRZ_CFG_EN | \ + HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT | \ + HDMI_SRZ_CFG_EXTERNAL_DATA | \ + HDMI_SRZ_CFG_RBIAS_EXT | \ + HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION | \ + HDMI_SRZ_CFG_EN_BIASRES_DETECTION | \ + HDMI_SRZ_CFG_EN_SRC_TERMINATION) + +#define PLL_CFG_EN (1L<<0) +#define PLL_CFG_NDIV_SHIFT (8) +#define PLL_CFG_IDF_SHIFT (16) +#define PLL_CFG_ODF_SHIFT (24) + +#define ODF_DIV_1 (0) +#define ODF_DIV_2 (1) +#define ODF_DIV_4 (2) +#define ODF_DIV_8 (3) + +#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */ + +struct plldividers_s { + uint32_t min; + uint32_t max; + uint32_t idf; + uint32_t odf; +}; + +/* + * Functional specification recommended values + */ +#define NB_PLL_MODE 5 +static struct plldividers_s plldividers[NB_PLL_MODE] = { + {0, 20000000, 1, ODF_DIV_8}, + {20000000, 42500000, 2, ODF_DIV_8}, + {42500000, 85000000, 4, ODF_DIV_4}, + {85000000, 170000000, 8, ODF_DIV_2}, + {170000000, 340000000, 16, ODF_DIV_1} +}; + +#define NB_HDMI_PHY_CONFIG 2 +static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = { + {0, 250000000, {0x0, 0x0, 0x0, 0x0} }, + {250000000, 300000000, {0x1110, 0x0, 0x0, 0x0} }, +}; + +/* + * Start hdmi phy macro cell tx3g4c28 + * + * @hdmi: pointer on the hdmi internal structure + * + * Return -1 if error occurs + */ +int sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) +{ + u32 ckpxpll = hdmi->mode.clock * 1000; + u32 tmdsck; + u32 idf; + u32 odf; + u32 pllctrl = 0; + u32 val; + int i; + bool foundplldivides = false; + + DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll); + + for (i = 0; i < NB_PLL_MODE; i++) { + if (ckpxpll >= plldividers[i].min && + ckpxpll < plldividers[i].max) { + idf = plldividers[i].idf; + odf = plldividers[i].odf; + foundplldivides = true; + break; + } + } + + if (!foundplldivides) { + DRM_ERROR("input TMDS clock speed (%d) not supported\n", + ckpxpll); + goto err; + } + + /* TODO: manage DeepColor (30, 36 and 48 bits) and pixel repetition */ + + /* Assuming no pixel repetition and 24bits color */ + tmdsck = ckpxpll; + pllctrl |= 40 << PLL_CFG_NDIV_SHIFT; + + if (tmdsck > 340000000) { + DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck); + goto err; + } + + pllctrl |= idf << PLL_CFG_IDF_SHIFT; + pllctrl |= odf << PLL_CFG_ODF_SHIFT; + + /* + * Configure and power up the PHY PLL + */ + hdmi->event_received = false; + DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl); + writel((pllctrl | PLL_CFG_EN), hdmi->regs + HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received == true, + msecs_to_jiffies + (HDMI_TIMEOUT_PLL_LOCK)); + + if ((readl(hdmi->regs + HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { + DRM_ERROR("hdmi phy pll not locked\n"); + goto err; + } + + DRM_DEBUG_DRIVER("got PHY PLL Lock\n"); + + val = (HDMI_SRZ_CFG_EN | + HDMI_SRZ_CFG_EXTERNAL_DATA | + HDMI_SRZ_CFG_EN_BIASRES_DETECTION | + HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION); + + if (tmdsck > 165000000) + val |= HDMI_SRZ_CFG_EN_SRC_TERMINATION; + + /* + * To configure the source termination and pre-emphasis appropriately + * for different high speed TMDS clock frequencies a phy configuration + * table must be provided, tailored to the SoC and board combination. + */ + for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) { + if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) && + (hdmiphy_config[i].max_tmds_freq >= tmdsck)) { + val |= (hdmiphy_config[i].config[0] + & ~HDMI_SRZ_CFG_INTERNAL_MASK); + writel(val, hdmi->regs + HDMI_SRZ_CFG); + val = hdmiphy_config[i].config[1]; + writel(val, hdmi->regs + HDMI_SRZ_ICNTL); + val = hdmiphy_config[i].config[2]; + writel(val, hdmi->regs + HDMI_SRZ_CALCODE_EXT); + DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x\n", + hdmiphy_config[i].config[0], + hdmiphy_config[i].config[1], + hdmiphy_config[i].config[2]); + return 0; + } + } + + /* + * Default, power up the serializer with no pre-emphasis or + * output swing correction + */ + writel(val, hdmi->regs + HDMI_SRZ_CFG); + writel(0x0, hdmi->regs + HDMI_SRZ_ICNTL); + writel(0x0, hdmi->regs + HDMI_SRZ_CALCODE_EXT); + + return 0; + +err: + return -1; +} + +/* + * Stop hdmi phy macro cell tx3g4c28 + * + * @hdmi: pointer on the hdmi internal structure + */ +void sti_hdmi_tx3g4c28phy_stop(struct sti_hdmi *hdmi) +{ + int val = 0; + + DRM_DEBUG_DRIVER("\n"); + + hdmi->event_received = false; + + val = HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION; + val |= HDMI_SRZ_CFG_EN_BIASRES_DETECTION; + writel(val, hdmi->regs + HDMI_SRZ_CFG); + writel(0, hdmi->regs + HDMI_SRZ_PLL_CFG); + + /* wait PLL interrupt */ + wait_event_interruptible_timeout(hdmi->wait_event, + hdmi->event_received == true, + msecs_to_jiffies + (HDMI_TIMEOUT_PLL_LOCK)); + + if ((readl(hdmi->regs + HDMI_STA) & HDMI_STA_DLL_LCK) == 1) + DRM_ERROR("hdmi phy pll not well disabled\n"); + else + DRM_DEBUG_DRIVER("hdmi phy pll disabled\n"); +} + +/* + * Debugfs + */ +#define HDMI_DBG_DUMP(reg) seq_printf(m, "\n %-25s 0x%08X", #reg, \ + readl(hdmi->regs + reg)) +void sti_hdmi_tx3g4c28phy_show(struct sti_hdmi *hdmi, struct seq_file *m) +{ + HDMI_DBG_DUMP(HDMI_SRZ_CFG); + HDMI_DBG_DUMP(HDMI_SRZ_PLL_CFG); + HDMI_DBG_DUMP(HDMI_SRZ_ICNTL); + HDMI_DBG_DUMP(HDMI_SRZ_CALCODE_EXT); + seq_puts(m, "\n"); +}

Add I2C client driver to retrieve EDID.

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Makefile | 3 ++- drivers/gpu/drm/sti/sti_ddc.c | 56 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/sti/sti_ddc.c

diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 2bb3035..b6f596a 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -2,7 +2,8 @@ ccflags-y := -Iinclude/drm

stidrm-y := sti_hdmi.o \ sti_hdmi_tx3g0c55phy.o \ - sti_hdmi_tx3g4c28phy.o + sti_hdmi_tx3g4c28phy.o \ + sti_ddc.o

obj-$(CONFIG_DRM_STI) += stidrm.o obj-$(CONFIG_VTAC_STI) += sti_vtac_tx.o sti_vtac_rx.o diff --git a/drivers/gpu/drm/sti/sti_ddc.c b/drivers/gpu/drm/sti/sti_ddc.c new file mode 100644 index 0000000..147a704 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_ddc.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ +#include <drm/drmP.h> + +#include <linux/kernel.h> +#include <linux/i2c.h> +#include <linux/module.h> + +#include "sti_hdmi.h" + +static int sti_hdmi_ddc_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + sti_hdmi_attach_ddc_client(client); + + DRM_INFO("%s attached %s into i2c adapter successfully\n", + __func__, client->name); + + return 0; +} + +static int sti_hdmi_ddc_remove(struct i2c_client *client) +{ + DRM_INFO("%s detached %s from i2c adapter successfully\n", + __func__, client->name); + + return 0; +} + +static struct i2c_device_id sti_ddc_idtable[] = { + {"sti-hdmiddc", 0}, + {}, +}; + +static struct of_device_id hdmiddc_match_types[] = { + { + .compatible = "st,sti-hdmiddc", + }, { + /* end node */ + } +}; + +struct i2c_driver ddc_driver = { + .driver = { + .name = "sti-hdmiddc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(hdmiddc_match_types), + }, + .id_table = sti_ddc_idtable, + .probe = sti_hdmi_ddc_probe, + .remove = sti_hdmi_ddc_remove, + .command = NULL, +};

TVout hardware block is responsible to dispatch the data flow coming from compositor block to any of the output (HDMI or Analog TV). It control when output are start/stop and configure according the require flow path.

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Makefile | 4 +- drivers/gpu/drm/sti/sti_hda.c | 373 ++++++++++++++++++++++ drivers/gpu/drm/sti/sti_hda.h | 14 + drivers/gpu/drm/sti/sti_hdmi.c | 542 +++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_hdmi.h | 3 + drivers/gpu/drm/sti/sti_tvout.c | 682 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_tvout.h | 105 +++++++ 7 files changed, 1722 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/sti/sti_hda.h create mode 100644 drivers/gpu/drm/sti/sti_tvout.c create mode 100644 drivers/gpu/drm/sti/sti_tvout.h

diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 134ae6d..447eccf 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -1,6 +1,8 @@ ccflags-y := -Iinclude/drm

-stidrm-y := sti_hdmi.o \ +stidrm-y := \ + sti_tvout.o \ + sti_hdmi.o \ sti_hdmi_tx3g0c55phy.o \ sti_hdmi_tx3g4c28phy.o \ sti_hda.o \ diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c index 03ed120..02a6f3a 100644 --- a/drivers/gpu/drm/sti/sti_hda.c +++ b/drivers/gpu/drm/sti/sti_hda.c @@ -10,6 +10,8 @@

#include <drm/drmP.h>

+#include "sti_hda.h" + /* HDformatter registers */ #define HDA_ANA_CFG 0x0000 #define HDA_ANA_SCALE_CTRL_Y 0x0004 @@ -371,6 +373,377 @@ static int sti_hda_get_modes(struct drm_connector *drm_connector) return count; }

+/* + * Start hd analog + * + * @connector: pointer on the tvout HD analog connector + * + * Return 0 on success + */ +static int sti_hda_start(struct sti_tvout_connector *connector) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + u32 val, i, mode_idx; + u32 src_filter_y, src_filter_c; + u32 *coef_y, *coef_c; + u32 filter_mode; + + DRM_DEBUG_DRIVER("\n"); + + /* Prepare/enable clocks */ + if (clk_prepare_enable(hda->clk_pix)) + DRM_ERROR("Failed to prepare/enable hda_pix clk\n"); + if (clk_prepare_enable(hda->clk_hddac)) + DRM_ERROR("Failed to prepare/enable hda_hddac clk\n"); + + hda->enabled = true; + + if (!hda_get_mode_idx(hda->mode, &mode_idx)) { + DRM_ERROR("Undefined mode\n"); + return 1; + } + + switch (hda_supported_modes[mode_idx].vid_cat) { + case VID_HD_148M: + DRM_ERROR("Beyond HD analog capabilities\n"); + return 1; + case VID_HD_74M: + /* HD use alternate 2x filter */ + filter_mode = CFG_AWG_FLTR_MODE_HD; + src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X; + src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X; + coef_y = coef_y_alt_2x; + coef_c = coef_c_alt_2x; + break; + case VID_ED: + /* ED uses 4x filter */ + filter_mode = CFG_AWG_FLTR_MODE_ED; + src_filter_y = HDA_ANA_SRC_Y_CFG_4X; + src_filter_c = HDA_ANA_SRC_C_CFG_4X; + coef_y = coef_yc_4x; + coef_c = coef_yc_4x; + break; + case VID_SD: + DRM_ERROR("Not supported\n"); + return 1; + default: + DRM_ERROR("Undefined resolution\n"); + return 1; + } + DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx); + + /* Enable HD Video DACs */ + hda_enable_hd_dacs(hda, true); + + /* Configure scaler */ + writel(SCALE_CTRL_Y_DFLT, hda->regs + HDA_ANA_SCALE_CTRL_Y); + writel(SCALE_CTRL_CB_DFLT, hda->regs + HDA_ANA_SCALE_CTRL_CB); + writel(SCALE_CTRL_CR_DFLT, hda->regs + HDA_ANA_SCALE_CTRL_CR); + + /* Configure sampler */ + writel(src_filter_y, hda->regs + HDA_ANA_SRC_Y_CFG); + writel(src_filter_c, hda->regs + HDA_ANA_SRC_C_CFG); + for (i = 0; i < SAMPLER_COEF_NB; i++) { + writel(coef_y[i], hda->regs + HDA_COEFF_Y_PH1_TAP123 + i * 4); + writel(coef_c[i], hda->regs + HDA_COEFF_C_PH1_TAP123 + i * 4); + } + + /* Configure main HDFormatter */ + val = 0; + val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? + 0 : CFG_AWG_ASYNC_VSYNC_MTD; + val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); + val |= filter_mode; + writel(val, hda->regs + HDA_ANA_CFG); + + /* Configure AWG */ + sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr, + hda_supported_modes[mode_idx].nb_instr); + + /* Enable AWG */ + hda_reg_writemask(hda->regs + HDA_ANA_CFG, 1, CFG_AWG_ASYNC_EN); + + return 0; +} + +/* + * Stop HD analog + * + * @connector: pointer on the tvout HD analog connector + */ +static void sti_hda_stop(struct sti_tvout_connector *connector) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + + if (!hda->enabled) + return; + + DRM_DEBUG_DRIVER("\n"); + + /* Disable HD DAC and AWG */ + hda_reg_writemask(hda->regs + HDA_ANA_CFG, 0, CFG_AWG_ASYNC_EN); + hda_enable_hd_dacs(hda, false); + + /* Disable/unprepare hda clock */ + clk_disable_unprepare(hda->clk_hddac); + clk_disable_unprepare(hda->clk_pix); + + hda->enabled = false; +} + +/* + * Check if the drm display mode in supported by the HD analog + * + * @connector: pointer on the tvout HD analog connector + * @mode: drm display mode + * + * Return 0 if supported + */ +#define CLK_TOLERANCE_HZ 50 +static int sti_hda_check_mode(struct sti_tvout_connector *connector, + struct drm_display_mode *mode) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + int target = mode->clock * 1000; + int target_min = target - CLK_TOLERANCE_HZ; + int target_max = target + CLK_TOLERANCE_HZ; + int result; + int idx; + + if (!hda_get_mode_idx(*mode, &idx)) { + return 1; + } else { + result = clk_round_rate(hda->clk_pix, target); + + DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", + target, result); + + if ((result < target_min) || (result > target_max)) { + DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n", + target); + return 1; + } + } + + return 0; +} + +/* + * Set the drm display mode in the local structure + * + * @connector: pointer on the tvout HD analog connector + * @mode: drm display mode + * + * Return 0 on success + */ +static int sti_hda_set_mode(struct sti_tvout_connector *connector, + struct drm_display_mode *mode) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + u32 mode_idx; + int hddac_rate; + int ret; + + DRM_DEBUG_DRIVER("\n"); + + memcpy(&hda->mode, mode, sizeof(struct drm_display_mode)); + + if (!hda_get_mode_idx(hda->mode, &mode_idx)) { + DRM_ERROR("Undefined mode\n"); + return 1; + } + + switch (hda_supported_modes[mode_idx].vid_cat) { + case VID_HD_74M: + /* HD use alternate 2x filter */ + hddac_rate = mode->clock * 1000 * 2; + break; + case VID_ED: + /* ED uses 4x filter */ + hddac_rate = mode->clock * 1000 * 4; + break; + default: + DRM_ERROR("Undefined mode\n"); + return 1; + } + + /* HD DAC = 148.5Mhz or 108 Mhz */ + ret = clk_set_rate(hda->clk_hddac, hddac_rate); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n", + hddac_rate); + return ret; + } + + /* HDformatter clock = compositor clock */ + ret = clk_set_rate(hda->clk_pix, mode->clock * 1000); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n", + mode->clock * 1000); + return ret; + } + + return 0; +} + +/* + * Detect if HD analog is connected + * + * @connector: pointer on the tvout HD analog connector + * + * Return true if HD analog cable is connected which is assumed to be always + * the case + */ +static bool sti_hda_detect(struct sti_tvout_connector *connector) +{ + DRM_DEBUG_DRIVER("\n"); + + return true; +} + +/* + * Check if HD analog is enabled + * + * @connector: pointer on the tvout HD analog connector + * + * Return true if HD analog is enabled + */ +static bool sti_hda_is_enabled(struct sti_tvout_connector *connector) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + + return hda->enabled; +} + +/* + * Prepare/configure HD analog + * + * @connector: pointer on the tvout HD analog connector + */ +static void sti_hda_prepare(struct sti_tvout_connector *connector) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + + DRM_DEBUG_DRIVER("\n"); + + /* reset HDF */ + writel(0x00000000, hda->regs + HDA_ANA_CFG); + writel(0x00000000, hda->regs + HDA_ANA_ANC_CTRL); +} + +/* + * Debugfs + */ + +#define HDA_DBG_DUMP(reg) seq_printf(m, "\n %-25s 0x%08X", #reg, \ + readl(hda->regs + reg)) + +static void hda_dbg_cfg(struct seq_file *m, int val) +{ + seq_puts(m, "\t AWG "); + seq_puts(m, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); +} + +static void hda_dbg_awgi(struct seq_file *m, void __iomem *reg) +{ + int i; + + seq_puts(m, "\n HDA_SYNC_AWGI "); + for (i = 0; i < 10; i++) + seq_printf(m, "%04X ", readl(reg + i * 4)); + seq_puts(m, "..."); +} + +static void hda_dbg_video_dacs_ctrl(struct seq_file *m, void __iomem *reg) +{ + u32 val = readl(reg); + u32 mask; + + switch ((u32)reg & VIDEO_DACS_CONTROL_MASK) { + case VIDEO_DACS_CONTROL_SYSCFG2535: + mask = DAC_CFG_HD_OFF_MASK; + break; + case VIDEO_DACS_CONTROL_SYSCFG5072: + mask = DAC_CFG_HD_HZUVW_OFF_MASK; + break; + default: + DRM_INFO("Video DACS control register not supported!"); + return; + } + + seq_puts(m, "\n"); + + seq_printf(m, "\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); + seq_puts(m, "\tHD DACs "); + seq_puts(m, val & mask ? "disabled" : "enabled"); +} + +static void sti_hda_dbg_show(struct sti_tvout_connector *connector, + struct seq_file *m) +{ + struct sti_hda *hda = (struct sti_hda *)connector->priv; + + seq_puts(m, "\n"); + seq_printf(m, "\nHD Analog: (virt base addr = 0x%p)", hda->regs); + HDA_DBG_DUMP(HDA_ANA_CFG); + hda_dbg_cfg(m, readl(hda->regs + HDA_ANA_CFG)); + HDA_DBG_DUMP(HDA_ANA_SCALE_CTRL_Y); + HDA_DBG_DUMP(HDA_ANA_SCALE_CTRL_CB); + HDA_DBG_DUMP(HDA_ANA_SCALE_CTRL_CR); + HDA_DBG_DUMP(HDA_ANA_ANC_CTRL); + HDA_DBG_DUMP(HDA_ANA_SRC_Y_CFG); + HDA_DBG_DUMP(HDA_ANA_SRC_C_CFG); + hda_dbg_awgi(m, hda->regs + HDA_SYNC_AWGI); + if (hda->video_dacs_ctrl) + hda_dbg_video_dacs_ctrl(m, hda->video_dacs_ctrl); +} + +/* + * create the HD analog output + * + * @tvout: pointer on the tvout information + * + * Return pointer on the created tvout connector or NULL if error occurs + */ +struct sti_tvout_connector *sti_hda_create(struct sti_tvout *tvout) +{ + struct sti_hda *hda = container_of(hda_dev, struct sti_hda, dev); + struct device *dev = &hda->dev; + struct sti_tvout_connector *connector; + + DRM_DEBUG_DRIVER("\n"); + + if (!hda) { + DRM_INFO("%s: No hda device probed\n", __func__); + return NULL; + } + + connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); + if (!connector) { + DRM_ERROR("Failed to allocate memory for connector\n"); + goto connector_alloc_failed; + } + + /* Set the drm device handle */ + hda->drm_dev = tvout->drm_dev; + + connector->priv = (void *)hda; + connector->start = sti_hda_start; + connector->stop = sti_hda_stop; + connector->get_modes = sti_hda_get_modes; + connector->check_mode = sti_hda_check_mode; + connector->set_mode = sti_hda_set_mode; + connector->detect = sti_hda_detect; + connector->is_enabled = sti_hda_is_enabled; + connector->prepare = sti_hda_prepare; + connector->dbg_show = sti_hda_dbg_show; + + return connector; + +connector_alloc_failed: + return NULL; +} + static int sti_hda_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; diff --git a/drivers/gpu/drm/sti/sti_hda.h b/drivers/gpu/drm/sti/sti_hda.h new file mode 100644 index 0000000..e88b30e --- /dev/null +++ b/drivers/gpu/drm/sti/sti_hda.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) STMicroelectronics SA 2014 + * Authors: Fabien Dessenne fabien.dessenne@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_HDA_H_ +#define _STI_HDA_H_ + +#include "sti_tvout.h" + +struct sti_tvout_connector *sti_hda_create(struct sti_tvout *tvout); + +#endif diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c index 5bbee6b..99e2be5 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.c +++ b/drivers/gpu/drm/sti/sti_hdmi.c @@ -379,6 +379,548 @@ fail: return -1; }

+/* + * Start hdmi + * + * @connector: pointer on the tvout hdmi connector + * + * Return -1 if error occurs + */ +static int sti_hdmi_start(struct sti_tvout_connector *connector) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + int ret = 0; + + DRM_DEBUG_DRIVER("\n"); + + /* Prepare/enable clocks */ + if (clk_prepare_enable(hdmi->clk_pix)) + DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n"); + if (clk_prepare_enable(hdmi->clk_tmds)) + DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n"); + if (clk_prepare_enable(hdmi->clk_phy)) + DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n"); + + hdmi->enabled = true; + + /* Program hdmi serializer and start phy */ + ret = hdmi_phy_start(hdmi); + if (ret) { + DRM_ERROR("Unable to start hdmi phy\n"); + return ret; + } + + /* Program hdmi active area */ + hdmi_active_area(hdmi); + + /* Enable working interrupts */ + writel(HDMI_WORKING_INT, hdmi->regs + HDMI_INT_EN); + + /* Program hdmi config */ + hdmi_config(hdmi); + + /* Program AVI infoframe */ + ret = hdmi_avi_infoframe_config(hdmi); + if (ret) + DRM_ERROR("Unable to configure AVI infoframe\n"); + + /* Sw reset */ + ret = hdmi_swreset(hdmi); + if (ret) + DRM_ERROR("Unable to perform the hdmi sw reset\n"); + + return ret; +} + +/* + * Stop hdmi + * + * @connector: pointer on the tvout hdmi connector + */ +static void sti_hdmi_stop(struct sti_tvout_connector *connector) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + u32 val; + u32 mask; + + if (!hdmi->enabled) + return; + + DRM_DEBUG_DRIVER("\n"); + + /* Disable HDMI */ + mask = HDMI_CFG_DEVICE_EN; + val = ~HDMI_CFG_DEVICE_EN; + + hdmi_reg_writemask(hdmi->regs + HDMI_CFG, val, mask); + + /* Stop the phy */ + hdmi_phy_stop(hdmi); + + /* Disable/unprepare hdmi clock */ + clk_disable_unprepare(hdmi->clk_phy); + clk_disable_unprepare(hdmi->clk_tmds); + clk_disable_unprepare(hdmi->clk_pix); + + hdmi->enabled = false; +} + +/* + * Check if the drm display mode in supported by the hdmi + * + * @connector: pointer on the tvout hdmi connector + * @mode: drm display mode + * + * Return -1 if not supported + */ +#define CLK_TOLERANCE_HZ 50 +static int sti_hdmi_check_mode(struct sti_tvout_connector *connector, + struct drm_display_mode *mode) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + int target = mode->clock * 1000; + int target_min = target - CLK_TOLERANCE_HZ; + int target_max = target + CLK_TOLERANCE_HZ; + int result; + + result = clk_round_rate(hdmi->clk_pix, target); + + DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", + target, result); + + if ((result < target_min) || (result > target_max)) { + DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target); + return -1; + } + + return 0; +} + +/* + * Set the drm display mode in the local structure + * + * @connector: pointer on the tvout hdmi connector + * @mode: drm display mode + * + * Return -1 if error occurs + */ +/* FS bits */ +static int sti_hdmi_set_mode(struct sti_tvout_connector *connector, + struct drm_display_mode *mode) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + int ret; + + DRM_DEBUG_DRIVER("\n"); + + /* Copy the drm display mode in the connector local structure */ + memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode)); + + /* Update clock framerate according to the selected mode */ + ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n", + mode->clock * 1000); + return ret; + } + ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000); + if (ret < 0) { + DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n", + mode->clock * 1000); + return ret; + } + + return 0; +} + +/* + * Detect if hdmi is connected + * + * @connector: pointer on the tvout hdmi connector + * + * Return true if hdmi cable is connected + */ +static bool sti_hdmi_detect(struct sti_tvout_connector *connector) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + + DRM_DEBUG_DRIVER("\n"); + + if (hdmi->hpd) { + DRM_DEBUG_DRIVER("hdmi cable connected\n"); + return true; + } else + DRM_DEBUG_DRIVER("hdmi cable disconnected\n"); + + return false; +} + +/* + * Check if hdmi is enabled + * + * @connector: pointer on the tvout hdmi connector + * + * Return true if hdmi is enabled + */ +static bool sti_hdmi_is_enabled(struct sti_tvout_connector *connector) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + + return hdmi->enabled; +} + +/* + * Prepare/configure hdmi + * + * @connector: pointer on the tvout hdmi connector + */ +static void sti_hdmi_prepare(struct sti_tvout_connector *connector) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + + DRM_DEBUG_DRIVER("\n"); + + /* HDMI initialisation */ + writel(0x00000000, hdmi->regs + HDMI_CFG); + writel(0xffffffff, hdmi->regs + HDMI_INT_CLR); + + /* Ensure the PHY is completely powered down */ + hdmi_phy_stop(hdmi); + + /* Set the default channel data to be a dark red */ + writel(0x0000, hdmi->regs + HDMI_DFLT_CHL0_DAT); + writel(0x0000, hdmi->regs + HDMI_DFLT_CHL1_DAT); + writel(0x0060, hdmi->regs + HDMI_DFLT_CHL2_DAT); +} + +/* + * Debugfs + */ +#define HDMI_DBG_DUMP(reg) seq_printf(m, "\n %-25s 0x%08X", #reg, \ + readl(hdmi->regs + reg)) +#define HDMI_DBG_DUMP_DI(reg, slot) HDMI_DBG_DUMP(reg(slot)) +#define MAX_STRING_LENGTH 40 + +static void hdmi_dbg_cfg(struct seq_file *m, int val) +{ + int tmp; + char str[MAX_STRING_LENGTH]; + static const char *const mode[] = { "DVI", "HDMI" }; + static const char *const enable[] = { "disable", "enable" }; + static const char *const oess_ess[] = { "OESS enable", "ESS enable" }; + static const char *const polarity[] = { "normal", "inverted" }; + + seq_puts(m, "\t"); + + tmp = (val & HDMI_CFG_HDMI_NOT_DVI) >> HDMI_CFG_HDMI_NOT_DVI_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "mode: %s", mode[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_CFG_HDCP_EN) >> HDMI_CFG_HDCP_EN_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "HDCP: %s", enable[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_CFG_ESS_NOT_OESS) >> HDMI_CFG_ESS_NOT_OESS_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "HDCP mode: %s", oess_ess[tmp]); + seq_printf(m, "%-40s", str); + + seq_printf(m, "\n%-40s", ""); + + tmp = (val & HDMI_CFG_SINK_TERM_DET_EN) >> + HDMI_CFG_SINK_TERM_DET_EN_SHIFT; + snprintf(str, MAX_STRING_LENGTH, + "Sink term detection: %s", enable[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_CFG_H_SYNC_POL_NEG) >> HDMI_CFG_H_SYNC_POL_NEG_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "Hsync polarity: %s", polarity[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_CFG_V_SYNC_POL_NEG) >> HDMI_CFG_V_SYNC_POL_NEG_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "Vsync polarity: %s", polarity[tmp]); + seq_printf(m, "%-40s", str); + + seq_printf(m, "\n%-40s", ""); + + tmp = (val & HDMI_CFG_422_EN) >> HDMI_CFG_422_EN_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "YUV422 format: %s", enable[tmp]); + seq_printf(m, "%-40s", str); +} + +static void hdmi_dbg_sta(struct seq_file *m, int val) +{ + int tmp; + char str[MAX_STRING_LENGTH]; + static const char *const sink_term[] = { "not present", "present" }; + static const char *const pll_lck[] = { "not locked", "locked" }; + static const char *const hot_plug[] = { "not connected", "connected" }; + + seq_puts(m, "\t"); + + tmp = (val & HDMI_STA_FIFO_SAMPLES) >> HDMI_STA_FIFO_SAMPLES_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "fifo: %d samples", tmp); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_STA_SINK_TERM) >> HDMI_STA_SINK_TERM_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "sink term: %s", sink_term[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_STA_DLL_LCK) >> HDMI_STA_DLL_LCK_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "pll: %s", pll_lck[tmp]); + seq_printf(m, "%-40s", str); + + seq_printf(m, "\n%-40s", ""); + + tmp = (val & HDMI_STA_HOT_PLUG) >> HDMI_STA_HOT_PLUG_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "hdmi cable: %s", hot_plug[tmp]); + seq_printf(m, "%-40s", str); +} + +static void hdmi_dbg_sw_di_cfg(struct seq_file *m, int val) +{ + int tmp; + char str[MAX_STRING_LENGTH]; + static const char *const en_di[] = { "no transmission", + "single transmission", "once every field", "once every frame" + }; + + seq_puts(m, "\t"); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); + snprintf(str, MAX_STRING_LENGTH, "Data island 1: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; + snprintf(str, MAX_STRING_LENGTH, "Data island 2: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; + snprintf(str, MAX_STRING_LENGTH, "Data island 3: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); + + seq_printf(m, "\n%-40s", ""); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; + snprintf(str, MAX_STRING_LENGTH, "Data island 4: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; + snprintf(str, MAX_STRING_LENGTH, "Data island 5: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); + + tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; + snprintf(str, MAX_STRING_LENGTH, "Data island 6: %s", en_di[tmp]); + seq_printf(m, "%-40s", str); +} + +static void hdmi_dbg_xmin(struct seq_file *m, int val) +{ + seq_printf(m, "\tXmin: %4d", val & 0x0FFF); +} + +static void hdmi_dbg_xmax(struct seq_file *m, int val) +{ + seq_printf(m, "\tXmax: %4d", val & 0x0FFF); +} + +static void hdmi_dbg_ymin(struct seq_file *m, int val) +{ + seq_printf(m, "\tYmin: %4d", val & 0x0FFF); +} + +static void hdmi_dbg_ymax(struct seq_file *m, int val) +{ + seq_printf(m, "\tYmax: %4d", val & 0x0FFF); +} + +static void sti_hdmi_dbg_show(struct sti_tvout_connector *connector, + struct seq_file *m) +{ + struct sti_hdmi *hdmi = (struct sti_hdmi *)connector->priv; + struct drm_display_mode *mode = &hdmi->mode; + struct hdmi_avi_infoframe info; + char str[MAX_STRING_LENGTH]; + + seq_puts(m, "\n"); + seq_printf(m, "\nHDMI: (virt base addr = 0x%p)", hdmi->regs); + HDMI_DBG_DUMP(HDMI_CFG); + hdmi_dbg_cfg(m, readl(hdmi->regs + HDMI_CFG)); + HDMI_DBG_DUMP(HDMI_INT_EN); + HDMI_DBG_DUMP(HDMI_INT_STA); + HDMI_DBG_DUMP(HDMI_INT_CLR); + HDMI_DBG_DUMP(HDMI_STA); + hdmi_dbg_sta(m, readl(hdmi->regs + HDMI_STA)); + HDMI_DBG_DUMP(HDMI_ACTIVE_VID_XMIN); + hdmi_dbg_xmin(m, readl(hdmi->regs + HDMI_ACTIVE_VID_XMIN)); + HDMI_DBG_DUMP(HDMI_ACTIVE_VID_XMAX); + hdmi_dbg_xmax(m, readl(hdmi->regs + HDMI_ACTIVE_VID_XMAX)); + HDMI_DBG_DUMP(HDMI_ACTIVE_VID_YMIN); + hdmi_dbg_ymin(m, readl(hdmi->regs + HDMI_ACTIVE_VID_YMIN)); + HDMI_DBG_DUMP(HDMI_ACTIVE_VID_YMAX); + hdmi_dbg_ymax(m, readl(hdmi->regs + HDMI_ACTIVE_VID_YMAX)); + HDMI_DBG_DUMP(HDMI_DFLT_CHL0_DAT); + HDMI_DBG_DUMP(HDMI_DFLT_CHL1_DAT); + HDMI_DBG_DUMP(HDMI_DFLT_CHL2_DAT); + HDMI_DBG_DUMP(HDMI_SW_DI_CFG); + hdmi_dbg_sw_di_cfg(m, readl(hdmi->regs + HDMI_SW_DI_CFG)); + if (hdmi->tx3g0c55phy) + sti_hdmi_tx3g0c55phy_show(hdmi, m); + else + sti_hdmi_tx3g4c28phy_show(hdmi, m); + seq_puts(m, "\n"); + + seq_printf(m, "\nAVI Infoframe (Data Island slot N=%d):", + HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI); + HDMI_DBG_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI); + seq_puts(m, "\n"); + if (drm_hdmi_avi_infoframe_from_display_mode(&info, mode) == 0) { + static const char *const colorspace[] = { + "RGB", "YUV422", "YUV444" }; + static const char *const scan_mode[] = { + "none", "overscan", "underscan" }; + static const char *const colorimetry[] = { + "none", "ITU 601", "ITU 709", "extended" }; + static const char *const ext_colorimetry[] = { + "xvYCC 601", "xvYCC 709", "S YCC 601", "Adobe YCC 601", + "Adobe RGB" }; + static const char *const pict_aspect[] = { + "none", "4:3", "16:9" }; + static const char *const active_aspect[] = { + "", "", "16:9 top", "14:9 top", "16:9 center", "", "", + "", "picture", "4:3", "16:9", "14:9", "", "4:3 SP 14:9", + "16:9 SP 14:9", "16:9 SP 4:3" }; + static const char *const quant_range[] = { + "default", "4:3", "16:9" }; + static const char *const nups[] = { + "unknown", "horizontal", "vertical", "both" }; + static const char *const ycc_quant_range[] = { + "limited", "full" }; + static const char *const content_type[] = { + "none", "photo", "cinema", "game" }; + + snprintf(str, MAX_STRING_LENGTH, "\tversion:"); + seq_printf(m, "%-25s %d\n", str, info.version); + snprintf(str, MAX_STRING_LENGTH, "\tlength:"); + seq_printf(m, "%-25s %d\n", str, info.length); + snprintf(str, MAX_STRING_LENGTH, "\tcolorspace:"); + seq_printf(m, "%-25s %s\n", str, colorspace[info.colorspace]); + snprintf(str, MAX_STRING_LENGTH, "\tscan mode:"); + seq_printf(m, "%-25s %s\n", str, scan_mode[info.scan_mode]); + snprintf(str, MAX_STRING_LENGTH, "\tcolorimetry:"); + seq_printf(m, "%-25s %s\n", str, colorimetry[info.colorimetry]); + if (info.colorimetry == HDMI_COLORIMETRY_EXTENDED) { + snprintf(str, MAX_STRING_LENGTH, + " extended colorimetry:"); + seq_printf(m, "%-25s %s\n", str, + ext_colorimetry[info.extended_colorimetry]); + } + snprintf(str, MAX_STRING_LENGTH, "\tpicture aspect:"); + seq_printf(m, "%-25s %s\n", str, + pict_aspect[info.picture_aspect]); + snprintf(str, MAX_STRING_LENGTH, "\tactive aspect:"); + seq_printf(m, "%-25s %s\n", str, + active_aspect[info.active_aspect]); + snprintf(str, MAX_STRING_LENGTH, "\tquantization range:"); + seq_printf(m, "%-25s %s\n", str, + quant_range[info.quantization_range]); + snprintf(str, MAX_STRING_LENGTH, "\tycc quantization range:"); + seq_printf(m, "%-25s %s\n", str, + ycc_quant_range[info.ycc_quantization_range]); + snprintf(str, MAX_STRING_LENGTH, "\tnups:"); + seq_printf(m, "%-25s %s\n", str, nups[info.nups]); + snprintf(str, MAX_STRING_LENGTH, "\tpixel repeat:"); + seq_printf(m, "%-25s %d\n", str, info.pixel_repeat); + snprintf(str, MAX_STRING_LENGTH, "\tactive info valid:"); + seq_printf(m, "%-25s %s\n", str, + info.pixel_repeat ? "true" : "false"); + snprintf(str, MAX_STRING_LENGTH, "\titc:"); + seq_printf(m, "%-25s %s\n", str, info.itc ? "true" : "false"); + snprintf(str, MAX_STRING_LENGTH, "\ttop bar:"); + seq_printf(m, "%-25s %d\n", str, info.top_bar); + snprintf(str, MAX_STRING_LENGTH, "\tbottom bar:"); + seq_printf(m, "%-25s %d\n", str, info.bottom_bar); + snprintf(str, MAX_STRING_LENGTH, "\tleft bar:"); + seq_printf(m, "%-25s %d\n", str, info.left_bar); + snprintf(str, MAX_STRING_LENGTH, "\tright bar:"); + seq_printf(m, "%-25s %d\n", str, info.right_bar); + snprintf(str, MAX_STRING_LENGTH, "\tcontent type:"); + seq_printf(m, "%-25s %s\n", str, + content_type[info.content_type]); + snprintf(str, MAX_STRING_LENGTH, "\tCEA video code:"); + seq_printf(m, "%-25s %d\n", str, info.video_code); + } + + seq_printf(m, "\nHDMI mode: %dx%d%s @%d", + hdmi->mode.hdisplay, + hdmi->mode.vdisplay, + (hdmi->mode.flags & DRM_MODE_FLAG_INTERLACE) ? + "i" : "p", hdmi->mode.vrefresh); +} + +/* + * create the hdmi output + * + * @tvout: pointer on the tvout information + * + * Return pointer on the created tvout connector or NULL if error occurs + */ +struct sti_tvout_connector *sti_hdmi_create(struct sti_tvout *tvout) +{ + struct sti_hdmi *hdmi = container_of(hdmi_dev, struct sti_hdmi, dev); + struct device *dev = &hdmi->dev; + struct sti_tvout_connector *connector; + + DRM_DEBUG_DRIVER("\n"); + + if (!hdmi) { + DRM_INFO("%s: No hdmi device probed\n", __func__); + return NULL; + } + + connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); + if (!connector) { + DRM_ERROR("Failed to allocate memory for connector\n"); + goto connector_alloc_failed; + } + + /* Set the drm device handle */ + hdmi->drm_dev = tvout->drm_dev; + + /* DDC i2c driver */ + if (i2c_add_driver(&ddc_driver)) { + DRM_ERROR("Failed to register ddc i2c driver\n"); + goto i2c_failed; + } + + /* Enable default interrupts */ + writel(HDMI_DEFAULT_INT, hdmi->regs + HDMI_INT_EN); + + connector->priv = (void *)hdmi; + connector->start = sti_hdmi_start; + connector->stop = sti_hdmi_stop; + connector->get_modes = sti_hdmi_get_modes; + connector->check_mode = sti_hdmi_check_mode; + connector->set_mode = sti_hdmi_set_mode; + connector->detect = sti_hdmi_detect; + connector->is_enabled = sti_hdmi_is_enabled; + connector->prepare = sti_hdmi_prepare; + connector->dbg_show = sti_hdmi_dbg_show; + + return connector; + +i2c_failed: + devm_kfree(dev, connector); +connector_alloc_failed: + return NULL; +} + static int sti_hdmi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; diff --git a/drivers/gpu/drm/sti/sti_hdmi.h b/drivers/gpu/drm/sti/sti_hdmi.h index c14c683..ed90a2c 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.h +++ b/drivers/gpu/drm/sti/sti_hdmi.h @@ -11,6 +11,8 @@

#include <drm/drmP.h>

+#include "sti_tvout.h" + /* HDMI v2.9 macro cell */ #define HDMI_CFG 0x0000 #define HDMI_INT_EN 0x0004 @@ -181,6 +183,7 @@ struct hdmi_phy_config { u32 config[4]; };

+struct sti_tvout_connector *sti_hdmi_create(struct sti_tvout *tvout); void sti_hdmi_attach_ddc_client(struct i2c_client *ddc);

int sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi); diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c new file mode 100644 index 0000000..df9a2c3 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -0,0 +1,682 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * Author: Vincent Abriou vincent.abriou@st.com for STMicroelectronics + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> + +#include "sti_tvout.h" +#include "sti_hdmi.h" +#include "sti_hda.h" + +/* glue regsiters */ +#define TVO_CSC_MAIN_M0 0x000 +#define TVO_CSC_MAIN_M1 0x004 +#define TVO_CSC_MAIN_M2 0x008 +#define TVO_CSC_MAIN_M3 0x00c +#define TVO_CSC_MAIN_M4 0x010 +#define TVO_CSC_MAIN_M5 0x014 +#define TVO_CSC_MAIN_M6 0x018 +#define TVO_CSC_MAIN_M7 0x01c +#define TVO_MAIN_IN_VID_FORMAT 0x030 +#define TVO_CSC_AUX_M0 0x100 +#define TVO_CSC_AUX_M1 0x104 +#define TVO_CSC_AUX_M2 0x108 +#define TVO_CSC_AUX_M3 0x10c +#define TVO_CSC_AUX_M4 0x110 +#define TVO_CSC_AUX_M5 0x114 +#define TVO_CSC_AUX_M6 0x118 +#define TVO_CSC_AUX_M7 0x11c +#define TVO_AUX_IN_VID_FORMAT 0x130 +#define TVO_VIP_HDF 0x400 +#define TVO_HD_SYNC_SEL 0x418 +#define TVO_HD_DAC_CFG_OFF 0x420 +#define TVO_VIP_HDMI 0x500 +#define TVO_HDMI_FORCE_COLOR_0 0x504 +#define TVO_HDMI_FORCE_COLOR_1 0x508 +#define TVO_HDMI_CLIP_VALUE_B_CB 0x50c +#define TVO_HDMI_CLIP_VALUE_Y_G 0x510 +#define TVO_HDMI_CLIP_VALUE_R_CR 0x514 +#define TVO_HDMI_SYNC_SEL 0x518 +#define TVO_HDMI_DFV_OBS 0x540 + +#define TVO_IN_FMT_SIGNED (1 << 0) +#define TVO_SYNC_EXT (1 << 4) + +#define TVO_VIP_REORDER_R_SHIFT 24 +#define TVO_VIP_REORDER_G_SHIFT 20 +#define TVO_VIP_REORDER_B_SHIFT 16 +#define TVO_VIP_REORDER_MASK 0x3 +#define TVO_VIP_REORDER_Y_G_SEL 0 +#define TVO_VIP_REORDER_CB_B_SEL 1 +#define TVO_VIP_REORDER_CR_R_SEL 2 + +#define TVO_VIP_CLIP_SHIFT 8 +#define TVO_VIP_CLIP_MASK 0x7 +#define TVO_VIP_CLIP_DISABLED 0 +#define TVO_VIP_CLIP_EAV_SAV 1 +#define TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y 2 +#define TVO_VIP_CLIP_LIMITED_RANGE_CB_CR 3 +#define TVO_VIP_CLIP_PROG_RANGE 4 + +#define TVO_VIP_RND_SHIFT 4 +#define TVO_VIP_RND_MASK 0x3 +#define TVO_VIP_RND_8BIT_ROUNDED 0 +#define TVO_VIP_RND_10BIT_ROUNDED 1 +#define TVO_VIP_RND_12BIT_ROUNDED 2 + +#define TVO_VIP_SEL_INPUT_MASK 0xf +#define TVO_VIP_SEL_INPUT_MAIN 0x0 +#define TVO_VIP_SEL_INPUT_AUX 0x8 +#define TVO_VIP_SEL_INPUT_FORCE_COLOR 0xf +#define TVO_VIP_SEL_INPUT_BYPASS_MASK 0x1 +#define TVO_VIP_SEL_INPUT_BYPASSED 1 + +#define TVO_SYNC_MAIN_VTG_SET_REF 0x00 +#define TVO_SYNC_MAIN_VTG_SET_1 0x01 +#define TVO_SYNC_MAIN_VTG_SET_2 0x02 +#define TVO_SYNC_MAIN_VTG_SET_3 0x03 +#define TVO_SYNC_MAIN_VTG_SET_4 0x04 +#define TVO_SYNC_MAIN_VTG_SET_5 0x05 +#define TVO_SYNC_MAIN_VTG_SET_6 0x06 +#define TVO_SYNC_AUX_VTG_SET_REF 0x10 +#define TVO_SYNC_AUX_VTG_SET_1 0x11 +#define TVO_SYNC_AUX_VTG_SET_2 0x12 +#define TVO_SYNC_AUX_VTG_SET_3 0x13 +#define TVO_SYNC_AUX_VTG_SET_4 0x14 +#define TVO_SYNC_AUX_VTG_SET_5 0x15 +#define TVO_SYNC_AUX_VTG_SET_6 0x16 + +#define TVO_SYNC_HD_DCS_SHIFT 8 + +/* Preformatter conversion matrix */ +static const u32 rgb_to_ycbcr_601[8] = { + 0xF927082E, 0x04C9FEAB, 0x01D30964, 0xFA95FD3D, + 0x0000082E, 0x00002000, 0x00002000, 0x00000000 +}; + +/* 709 RGB to YCbCr */ +static const u32 rgb_to_ycbcr_709[8] = { + 0xF891082F, 0x0367FF40, 0x01280B71, 0xF9B1FE20, + 0x0000082F, 0x00002000, 0x00002000, 0x00000000 +}; + +/* + * Helper to write bit field + * + * @addr: register to update + * @val: value to write + * @mask: bit field mask to use + */ +static inline void tvout_reg_writemask(void __iomem *addr, u32 val, u32 mask) +{ + u32 old = readl(addr); + + val = (val & mask) | (old & ~mask); + writel(val, addr); +} + +/* + * Set the Channel order of a VIP + * + * @vip_reg: VIP regsiter + * @cr_r + * @y_g + * @cb_c : values for each output + */ +static void tvout_vip_set_color_order(void __iomem *vip_reg, + u32 cr_r, u32 y_g, u32 cb_b) +{ + u32 val, mask; + + mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT; + mask |= TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT; + mask |= TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT; + val = cr_r << TVO_VIP_REORDER_R_SHIFT; + val |= y_g << TVO_VIP_REORDER_G_SHIFT; + val |= cb_b << TVO_VIP_REORDER_B_SHIFT; + tvout_reg_writemask(vip_reg, val, mask); +} + +/* + * Set the clipping mode of a VIP + * + * @vip_reg: VIP regsiter + * @range : clipping range + */ +static void tvout_vip_set_clip_mode(void __iomem *vip_reg, u32 range) +{ + tvout_reg_writemask(vip_reg, + range << TVO_VIP_CLIP_SHIFT, + TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT); +} + +/* + * Set the rounded value of a VIP + * + * @vip_reg: VIP regsiter + * @rnd: rounded val per component + */ +static void tvout_vip_set_rnd(void __iomem *vip_reg, u32 rnd) +{ + tvout_reg_writemask(vip_reg, + rnd << TVO_VIP_RND_SHIFT, + TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT); +} + +/* + * Select the VIP input + * + * @vip_reg: VIP regsiter + * @sel_input: selected_input (main/aux + conv) + */ +static void tvout_vip_set_sel_input(void __iomem *vip_reg, + bool main_path, + bool sel_input_logic_inverted, + enum sti_tvout_video_out_type video_out) +{ + u32 sel_input; + + if (main_path) + sel_input = TVO_VIP_SEL_INPUT_MAIN; + else + sel_input = TVO_VIP_SEL_INPUT_AUX; + + switch (video_out) { + case STI_TVOUT_VIDEO_OUT_RGB: + sel_input |= TVO_VIP_SEL_INPUT_BYPASSED; + break; + case STI_TVOUT_VIDEO_OUT_YUV: + sel_input &= ~TVO_VIP_SEL_INPUT_BYPASSED; + break; + } + + /* On stih407 chip the sel_input bypass mode logic is inverted */ + if (sel_input_logic_inverted) + sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK; + + tvout_reg_writemask(vip_reg, sel_input, TVO_VIP_SEL_INPUT_MASK); +} + +/* + * Select the input video signed or unsigned + * + * @vip_reg: VIP regsiter + * @in_vid_signed: used video input format + */ +static void tvout_vip_set_in_vid_fmt(void __iomem *vip_reg, u32 in_vid_fmt) +{ + tvout_reg_writemask(vip_reg, in_vid_fmt, TVO_IN_FMT_SIGNED); +} + +/* + * Start VIP block for HDMI output + * + * @tvout: pointer on tvout structure + * @main_path: true if main path has to be used in the vip configuration + * else aux path is used. + */ +static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path) +{ + struct device_node *node = tvout->dev->of_node; + bool sel_input_logic_inverted = false; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (main_path) { + DRM_DEBUG_DRIVER("main vip for hdmi\n"); + /* Select the input sync for hdmi = VTG set 1 */ + writel(TVO_SYNC_MAIN_VTG_SET_1, + tvout->regs + TVO_HDMI_SYNC_SEL); + } else { + DRM_DEBUG_DRIVER("aux vip for hdmi\n"); + /* Select the input sync for hdmi = VTG set 1 */ + writel(TVO_SYNC_AUX_VTG_SET_1, tvout->regs + TVO_HDMI_SYNC_SEL); + } + + /* Set color channel order */ + tvout_vip_set_color_order(tvout->regs + TVO_VIP_HDMI, + TVO_VIP_REORDER_CR_R_SEL, + TVO_VIP_REORDER_Y_G_SEL, + TVO_VIP_REORDER_CB_B_SEL); + + /* Set clipping mode (Limited range RGB/Y) */ + tvout_vip_set_clip_mode(tvout->regs + TVO_VIP_HDMI, + TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y); + + /* Set round mode (rounded to 8-bit per component) */ + tvout_vip_set_rnd(tvout->regs + TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED); + + if (of_device_is_compatible(node, "st,stih407-tvout")) { + /* Set input video format */ + tvout_vip_set_in_vid_fmt(tvout->regs + TVO_MAIN_IN_VID_FORMAT, + TVO_IN_FMT_SIGNED); + sel_input_logic_inverted = true; + } + + /* Input selection */ + tvout_vip_set_sel_input(tvout->regs + TVO_VIP_HDMI, + main_path, + sel_input_logic_inverted, + STI_TVOUT_VIDEO_OUT_RGB); +} + +/* + * Prepare/configure VIP block for HDMI output + * + * @tvout: pointer on tvout structure + */ +static void tvout_hdmi_prepare(struct sti_tvout *tvout) +{ + dev_dbg(tvout->dev, "%s\n", __func__); + + /* Reset VIP register */ + writel(0x00000000, tvout->regs + TVO_VIP_HDMI); +} + +/* + * Disable HDMI VIP + * + * @tvout: pointer on tvout structure + */ +static void tvout_hdmi_stop(struct sti_tvout *tvout) +{ + dev_dbg(tvout->dev, "%s\n", __func__); + + /* Reset VIP register */ + writel(0x00000000, tvout->regs + TVO_VIP_HDMI); +} + +/* + * Start HDF VIP and HD DAC + * + * @tvout: pointer on tvout structure + * @main_path: true if main path has to be used in the vip configuration + * else aux path is used. + */ +static void tvout_hda_start(struct sti_tvout *tvout, bool main_path) +{ + struct device_node *node = tvout->dev->of_node; + bool sel_input_logic_inverted = false; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (!main_path) { + DRM_ERROR("HD Analog on aux not implemented\n"); + return; + } + + DRM_DEBUG_DRIVER("main vip for HDF\n"); + + /* Set color channel order */ + tvout_vip_set_color_order(tvout->regs + TVO_VIP_HDF, + TVO_VIP_REORDER_CR_R_SEL, + TVO_VIP_REORDER_Y_G_SEL, + TVO_VIP_REORDER_CB_B_SEL); + + /* Set clipping mode (Limited range RGB/Y) */ + tvout_vip_set_clip_mode(tvout->regs + TVO_VIP_HDF, + TVO_VIP_CLIP_LIMITED_RANGE_CB_CR); + + /* Set round mode (rounded to 10-bit per component) */ + tvout_vip_set_rnd(tvout->regs + TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED); + + if (of_device_is_compatible(node, "st,stih407-tvout")) { + /* Set input video format */ + tvout_vip_set_in_vid_fmt(tvout->regs + TVO_MAIN_IN_VID_FORMAT, + TVO_IN_FMT_SIGNED); + sel_input_logic_inverted = true; + } + + /* Input selection */ + tvout_vip_set_sel_input(tvout->regs + TVO_VIP_HDF, + main_path, + sel_input_logic_inverted, + STI_TVOUT_VIDEO_OUT_YUV); + + /* Select the input sync for HD analog = VTG set 3 + * and HD DCS = VTG set 2 */ + writel((TVO_SYNC_MAIN_VTG_SET_2 << TVO_SYNC_HD_DCS_SHIFT) | + TVO_SYNC_MAIN_VTG_SET_3, tvout->regs + TVO_HD_SYNC_SEL); + + /* Power up HD DAC */ + writel(0, tvout->regs + TVO_HD_DAC_CFG_OFF); +} + +/* + * Prepare/configure HDF VIP and HD DAC + * + * @tvout: pointer on tvout structure + */ +static void tvout_hda_prepare(struct sti_tvout *tvout) +{ + dev_dbg(tvout->dev, "%s\n", __func__); + + /* Reset VIP register */ + writel(0x00000000, tvout->regs + TVO_VIP_HDF); + + /* Power down HD DAC */ + writel(1, tvout->regs + TVO_HD_DAC_CFG_OFF); +} + +/* + * Stop HDF VIP and HD DAC + * + * @tvout: pointer on tvout structure + */ +static void tvout_hda_stop(struct sti_tvout *tvout) +{ + dev_dbg(tvout->dev, "%s\n", __func__); + + /* Reset VIP register */ + writel(0x00000000, tvout->regs + TVO_VIP_HDF); + + /* Power down HD DAC */ + writel(1, tvout->regs + TVO_HD_DAC_CFG_OFF); +} + +/* + * Check if the connector is connected + * + * @tvout: pointer on tvout structure + * @type: type of connector + * + * Return true if connected + */ +bool sti_tvout_connector_detect(struct sti_tvout *tvout, + enum sti_tvout_connector_type type) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (connector) + if (connector->detect) + return connector->detect(connector); + + return false; +} + +/* + * Forward drm display mode information to the connector + * + * @tvout: pointer on tvout structure + * @mode: selected display mode + * @type: type of connector + * + * Return -1 if error occurs + */ +int sti_tvout_set_mode(struct sti_tvout *tvout, struct drm_display_mode *mode, + enum sti_tvout_connector_type type) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (connector) + if (connector->set_mode) + return connector->set_mode(connector, mode); + + return -1; +} + +/* + * Get modes + * + * @tvout: pointer on tvout structure + * @type: type of connector + * @drm_connector: pointer on the connector + * + * Return Nb of modes, -1 if error + */ +int sti_tvout_get_modes(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, + struct drm_connector *drm_connector) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (connector) + if (connector->get_modes) + return connector->get_modes(drm_connector); + + return -1; +} + +/* + * Check if the mode is supported + * + * function used to filter unsupported mode + * + * @tvout: pointer on tvout structure + * @type: type of connector + * @mode: drm display mode + * + * Return -1 if error occurs + */ +int sti_tvout_check_mode(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, + struct drm_display_mode *mode) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (connector) + if (connector->check_mode) + return connector->check_mode(connector, mode); + + return -1; +} + +/* + * Prepare / initialize depending on the connector type + * + * @tvout: pointer on tvout structure + * @type: type of connector + * + * Return -1 if error occurs + */ +int sti_tvout_prepare(struct sti_tvout *tvout, + enum sti_tvout_connector_type type) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + int ret = -1; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (connector) + if (connector->prepare) + connector->prepare(connector); + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + tvout_hdmi_prepare(tvout); + ret = 0; + break; + case STI_TVOUT_CONNECTOR_HDA: + tvout_hda_prepare(tvout); + ret = 0; + break; + case STI_TVOUT_CONNECTOR_DVO: + case STI_TVOUT_CONNECTOR_DENC: + default: + /* Not yet supported */ + ret = -1; + break; + } + + return ret; +} + +/* + * Commit / start depending on the connector type + * + * @tvout: pointer on tvout structure + * @type: type of connector + * @main_path: true if main path need to be use (false for aux path) + * + * Return -1 if error occurs + */ +int sti_tvout_commit(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, bool main_path) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + int ret = 0; + u32 matrix_offset; + int i; + + dev_dbg(tvout->dev, "%s\n", __func__); + + if (!connector) + return -1; + + connector->main_path = main_path; + + if (connector->start) { + ret = connector->start(connector); + if (ret) { + DRM_ERROR("Unable to properly start connector\n"); + return -1; + } + } + + /* Set preformatter matrix */ + matrix_offset = main_path ? TVO_CSC_MAIN_M0 : TVO_CSC_AUX_M0; + for (i = 0; i < 8; i++) + writel(rgb_to_ycbcr_601[i], + tvout->regs + matrix_offset + (i * 4)); + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + tvout_hdmi_start(tvout, main_path); + return 0; + case STI_TVOUT_CONNECTOR_HDA: + tvout_hda_start(tvout, main_path); + return 0; + case STI_TVOUT_CONNECTOR_DVO: + case STI_TVOUT_CONNECTOR_DENC: + default: + /* Not yet supported */ + return -1; + } +} + +/* + * Disable / stop the tvout depending on the connector type + * + * @tvout: pointer on tvout structure + * @type: type of connector + */ +void sti_tvout_disable(struct sti_tvout *tvout, + enum sti_tvout_connector_type type) +{ + struct sti_tvout_connector *connector = tvout->connector[type]; + + dev_dbg(tvout->dev, "%s\n", __func__); + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + tvout_hdmi_stop(tvout); + break; + case STI_TVOUT_CONNECTOR_HDA: + tvout_hda_stop(tvout); + break; + case STI_TVOUT_CONNECTOR_DVO: + case STI_TVOUT_CONNECTOR_DENC: + default: + /* Not yet supported */ + return; + } + + if (connector) + if (connector->stop) + connector->stop(connector); +} + +static int sti_tvout_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct sti_tvout *tvout; + struct resource *res; + int ret; + + dev_dbg(dev, "%s\n", __func__); + + if (!node) { + DRM_ERROR("no device node\n"); + return -ENODEV; + } + + tvout = devm_kzalloc(dev, sizeof(*tvout), GFP_KERNEL); + if (!tvout) { + DRM_ERROR("failed to allocate compositor context\n"); + return -ENOMEM; + } + DRM_DEBUG_DRIVER("tvout %p\n", tvout); + tvout->dev = dev; + + /* Get Memory ressources */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tvout-reg"); + if (!res) { + DRM_ERROR("Invalid glue resource\n"); + return -ENOMEM; + } + tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + if (IS_ERR(tvout->regs)) + return PTR_ERR(tvout->regs); + + /* Get reset resources */ + tvout->reset = devm_reset_control_get(dev, "tvout"); + /* Take tvout out of reset */ + if (!IS_ERR(tvout->reset)) + reset_control_deassert(tvout->reset); + + ret = of_platform_populate(node, NULL, NULL, dev); + if (ret) { + DRM_ERROR("failed to add hdmi core\n"); + return ret; + } + + /* List supported tvout connector */ + tvout->connector_create[STI_TVOUT_CONNECTOR_HDMI] = sti_hdmi_create; + tvout->connector_create[STI_TVOUT_CONNECTOR_HDA] = sti_hda_create; + tvout->connector_create[STI_TVOUT_CONNECTOR_DVO] = NULL; + tvout->connector_create[STI_TVOUT_CONNECTOR_DENC] = NULL; + + platform_set_drvdata(pdev, tvout); + + return 0; +} + +static struct of_device_id tvout_match_types[] = { + { + .compatible = "st,stih416-tvout", + }, + { + .compatible = "st,stih407-tvout", + }, + { /* end node */ } +}; + +struct platform_driver sti_tvout_driver = { + .driver = { + .name = "sti-tvout", + .owner = THIS_MODULE, + .of_match_table = tvout_match_types, + }, + .probe = sti_tvout_probe, +}; + +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/sti/sti_tvout.h b/drivers/gpu/drm/sti/sti_tvout.h new file mode 100644 index 0000000..f61a49c --- /dev/null +++ b/drivers/gpu/drm/sti/sti_tvout.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Vincent Abriou vincent.abriou@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_TVOUT_H_ +#define _STI_TVOUT_H_ + +#include <linux/clk.h> + +/* + * STI TVout connector structure + * + * @priv: private structure associated to the connector type + * @start: start the connector + * @stop: stop the connector + * @get_modes: get modes potentially supported + * @check_mode: check if a mode is really supported + * @set_mode: set the drm display mode in the specific connector structure + * @detect: detect if connector is connected + * @prepare: prepare the connector + * @is_enabled: is the connector enabled + * @dbg_show: dump debug information + */ +struct sti_tvout_connector { + void *priv; + bool main_path; + int (*start)(struct sti_tvout_connector *connector); + void (*stop)(struct sti_tvout_connector *connector); + int (*get_modes)(struct drm_connector *drm_connector); + int (*check_mode)(struct sti_tvout_connector *connector, + struct drm_display_mode *mode); + int (*set_mode)(struct sti_tvout_connector *connector, + struct drm_display_mode *mode); + bool (*detect)(struct sti_tvout_connector *connector); + void (*prepare)(struct sti_tvout_connector *connector); + bool (*is_enabled)(struct sti_tvout_connector *connector); + void (*dbg_show)(struct sti_tvout_connector *connector, + struct seq_file *m); +}; + +/* + * enum listing the supported connector + */ +enum sti_tvout_connector_type { + STI_TVOUT_CONNECTOR_HDMI, + STI_TVOUT_CONNECTOR_HDA, + STI_TVOUT_CONNECTOR_DVO, + STI_TVOUT_CONNECTOR_DENC, + STI_TVOUT_CONNECTOR_MAX, +}; + +/* + * enum listing the supported output data format + */ +enum sti_tvout_video_out_type { + STI_TVOUT_VIDEO_OUT_RGB, + STI_TVOUT_VIDEO_OUT_YUV, +}; + +/* + * STI TVout structure + * + * @dev: pointer to driver device + * @regs: registers + * @reset: reset control of the tvout + * @hw_id: HW revision of the IP + * @connector_create: list of function to register a connector + * @connector: list of registered connector + */ +struct sti_tvout { + struct device *dev; + struct drm_device *drm_dev; + void __iomem *regs; + struct reset_control *reset; + int hw_id; + struct sti_tvout_connector *(*connector_create[STI_TVOUT_CONNECTOR_MAX]) + (struct sti_tvout *tvout); + struct sti_tvout_connector *connector[STI_TVOUT_CONNECTOR_MAX]; +}; + +bool sti_tvout_connector_detect(struct sti_tvout *tvout, + enum sti_tvout_connector_type type); +int sti_tvout_set_mode(struct sti_tvout *tvout, + struct drm_display_mode *mode, + enum sti_tvout_connector_type type); +int sti_tvout_get_modes(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, + struct drm_connector *drm_connector); +int sti_tvout_check_mode(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, + struct drm_display_mode *mode); +int sti_tvout_prepare(struct sti_tvout *tvout, + enum sti_tvout_connector_type type); +int sti_tvout_commit(struct sti_tvout *tvout, + enum sti_tvout_connector_type type, + bool main_path); +void sti_tvout_disable(struct sti_tvout *tvout, + enum sti_tvout_connector_type type); + +int sti_tvout_hdmi_dbg_show(struct seq_file *m, void *arg); +int sti_tvout_hda_dbg_show(struct seq_file *m, void *arg); + +#endif

Generic Display Pipeline are one of the compositor input sub-devices. GDP are dedicated to graphic input like RGB plans.

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Makefile | 1 + drivers/gpu/drm/sti/sti_gdp.c | 491 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_gdp.h | 73 ++++++ drivers/gpu/drm/sti/sti_layer.h | 5 + drivers/gpu/drm/sti/sti_vtg.c | 14 +- drivers/gpu/drm/sti/sti_vtg_utils.h | 3 +- 6 files changed, 583 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/sti/sti_gdp.c create mode 100644 drivers/gpu/drm/sti/sti_gdp.h

diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 447eccf..3d1ae3e 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -1,6 +1,7 @@ ccflags-y := -Iinclude/drm

stidrm-y := \ + sti_gdp.o \ sti_tvout.o \ sti_hdmi.o \ sti_hdmi_tx3g0c55phy.o \ diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c new file mode 100644 index 0000000..00ff7f9 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_gdp.c @@ -0,0 +1,491 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> +#include <linux/dma-mapping.h> + +#include "sti_layer.h" +#include "sti_gdp.h" +#include "sti_vtg_utils.h" + +#define ENA_COLOR_FILL (1 << 8) +#define WAIT_NEXT_VSYNC (1 << 31) + +/* GDP color formats */ +#define GDP_RGB565 0x00 +#define GDP_RGB888 0x01 +#define GDP_RGB888_32 0x02 +#define GDP_ARGB8565 0x04 +#define GDP_ARGB8888 0x05 +#define GDP_ARGB1555 0x06 +#define GDP_ARGB4444 0x07 +#define GDP_CLUT8 0x0B +#define GDP_YCBR888 0x10 +#define GDP_YCBR422R 0x12 +#define GDP_AYCBR8888 0x15 + +#define GAM_GDP_CTL_OFFSET 0x00 +#define GAM_GDP_AGC_OFFSET 0x04 +#define GAM_GDP_VPO_OFFSET 0x0C +#define GAM_GDP_VPS_OFFSET 0x10 +#define GAM_GDP_PML_OFFSET 0x14 +#define GAM_GDP_PMP_OFFSET 0x18 +#define GAM_GDP_SIZE_OFFSET 0x1C +#define GAM_GDP_NVN_OFFSET 0x24 +#define GAM_GDP_KEY1_OFFSET 0x28 +#define GAM_GDP_KEY2_OFFSET 0x2C +#define GAM_GDP_PPT_OFFSET 0x34 +#define GAM_GDP_CML_OFFSET 0x3C +#define GAM_GDP_MST_OFFSET 0x68 + +#define GAM_GDP_ALPHARANGE_255 (1 << 5) +#define GAM_GDP_AGC_FULL_RANGE 0x00808080 +#define GAM_GDP_PPT_IGNORE ((1 << 1) | (1 << 0)) +#define GAM_GDP_SIZE_MAX 0x7FF + +static const uint32_t gdp_supported_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB4444, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGB565, + DRM_FORMAT_RGB888, + DRM_FORMAT_AYUV, + DRM_FORMAT_YUV444, + DRM_FORMAT_VYUY, + DRM_FORMAT_C8, +}; + +static const uint32_t *sti_gdp_get_formats(void) +{ + return gdp_supported_formats; +} + +static int sti_gdp_get_nb_formats(void) +{ + return ARRAY_SIZE(gdp_supported_formats); +} + +static int sti_gdp_fourcc2format(int fourcc) +{ + switch (fourcc) { + case DRM_FORMAT_XRGB8888: + return GDP_RGB888_32; + case DRM_FORMAT_ARGB8888: + return GDP_ARGB8888; + case DRM_FORMAT_ARGB4444: + return GDP_ARGB4444; + case DRM_FORMAT_ARGB1555: + return GDP_ARGB1555; + case DRM_FORMAT_RGB565: + return GDP_RGB565; + case DRM_FORMAT_RGB888: + return GDP_RGB888; + case DRM_FORMAT_AYUV: + return GDP_AYCBR8888; + case DRM_FORMAT_YUV444: + return GDP_YCBR888; + case DRM_FORMAT_VYUY: + return GDP_YCBR422R; + case DRM_FORMAT_C8: + return GDP_CLUT8; + } + return -1; +} + +static int sti_gdp_get_alpharange(int format) +{ + switch (format) { + case GDP_ARGB8565: + case GDP_ARGB8888: + case GDP_AYCBR8888: + return GAM_GDP_ALPHARANGE_255; + } + return 0; +} + +/** + * sti_gdp_get_free_nodes + * @layer: gdp layer + * + * Look for a GDP node list that is not currently read by the HW. + * + * RETURNS: + * Pointer to the free GDP node list + */ +static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_layer *layer) +{ + int hw_nvn; + void *virt_nvn; + struct sti_gdp *gdp = layer->gdp; + int i; + + hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); + if (!hw_nvn) + goto end; + + virt_nvn = dma_to_virt(gdp->dev, (dma_addr_t) hw_nvn); + + for (i = 0; i < GDP_NODE_NB_BANK; i++) + if ((virt_nvn != gdp->node_list[i].btm_field) && + (virt_nvn != gdp->node_list[i].top_field)) + return &gdp->node_list[i]; + +end: + return &gdp->node_list[0]; +} + +/** + * sti_gdp_get_current_nodes + * @layer: GDP layer + * + * Look for GDP nodes that are currently read by the HW. + * + * RETURNS: + * Pointer to the current GDP node list + */ +static +struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_layer *layer) +{ + int hw_nvn; + void *virt_nvn; + struct sti_gdp *gdp = layer->gdp; + int i; + + hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); + if (!hw_nvn) + goto end; + + virt_nvn = dma_to_virt(gdp->dev, (dma_addr_t) hw_nvn); + + for (i = 0; i < GDP_NODE_NB_BANK; i++) + if ((virt_nvn == gdp->node_list[i].btm_field) || + (virt_nvn == gdp->node_list[i].top_field)) + return &gdp->node_list[i]; + +end: + return NULL; +} + +/** + * sti_gdp_prepare_layer + * @lay: gdp layer + * @first_prepare: true if it is the first time this function is called + * + * Update the free GDP node list according to the layer properties. + * + * RETURNS: + * 0 on success. + */ +static int sti_gdp_prepare_layer(void *lay, bool first_prepare) +{ + struct sti_layer *layer = (struct sti_layer *)lay; + struct sti_gdp_node_list *list; + struct sti_gdp_node *top_field, *btm_field; + struct drm_display_mode *mode = layer->mode; + struct device *dev = layer->gdp->dev; + int format, depth, bpp; + int rate = mode->clock * 1000; + int res; + u32 ydo, xdo, yds, xds; + + list = sti_gdp_get_free_nodes(layer); + top_field = list->top_field; + btm_field = list->btm_field; + + /* Build the top field from layer params */ + top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; + top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; + format = sti_gdp_fourcc2format(layer->format); + if (format == -1) { + DRM_ERROR("Format not supported by GDP %.4s\n", + (char *)&layer->format); + return 1; + } + top_field->gam_gdp_ctl |= format; + top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); + top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; + + /* pixel memory location */ + drm_fb_get_bpp_depth(layer->format, &depth, &bpp); + top_field->gam_gdp_pml = (u32) layer->paddr + layer->offsets[0]; + top_field->gam_gdp_pml += layer->src_x * (bpp >> 3); + top_field->gam_gdp_pml += layer->src_y * layer->pitches[0]; + + /* input parameters */ + top_field->gam_gdp_pmp = layer->pitches[0]; + top_field->gam_gdp_size = + clamp_val(layer->src_h, 0, GAM_GDP_SIZE_MAX) << 16 | + clamp_val(layer->src_w, 0, GAM_GDP_SIZE_MAX); + + /* output parameters */ + ydo = sti_vtg_get_line_number(*mode, layer->dst_y); + yds = sti_vtg_get_line_number(*mode, layer->dst_y + layer->dst_h - 1); + xdo = sti_vtg_get_pixel_number(*mode, layer->dst_x); + xds = sti_vtg_get_pixel_number(*mode, layer->dst_x + layer->dst_w - 1); + top_field->gam_gdp_vpo = (ydo << 16) | xdo; + top_field->gam_gdp_vps = (yds << 16) | xds; + + /* Same content and chained together */ + memcpy(btm_field, top_field, sizeof(*btm_field)); + top_field->gam_gdp_nvn = virt_to_dma(dev, btm_field); + btm_field->gam_gdp_nvn = virt_to_dma(dev, top_field); + + /* Interlaced mode */ + if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) + btm_field->gam_gdp_pml = top_field->gam_gdp_pml + + layer->pitches[0]; + + if (first_prepare) { + /* Register gdp callback */ + if (sti_vtg_register_client(layer->mixer_id, + &layer->gdp->vtg_field_nb)) { + DRM_ERROR("Cannot register VTG notifier\n"); + return 1; + } + + /* Set and enable gdp clock */ + if (layer->gdp->clk_pix) { + res = clk_set_rate(layer->gdp->clk_pix, rate); + if (res < 0) { + DRM_ERROR("Cannot set rate (%dHz) for gdp\n", + rate); + return 1; + } + + if (clk_prepare_enable(layer->gdp->clk_pix)) { + DRM_ERROR("Failed to prepare/enable gdp\n"); + return 1; + } + } + } + + return 0; +} + +/** + * sti_gdp_commit_layer + * @lay: gdp layer + * + * Update the NVN field of the 'right' field of the current GDP node (being + * used by the HW) with the address of the updated ('free') top field GDP node. + * - In interlaced mode the 'right' field is the bottom field as we update + * frames starting from their top field + * - In progressive mode, we update both bottom and top fields which are + * equal nodes. + * At the next VSYNC, the updated node list will be used by the HW. + * + * RETURNS: + * 0 on success. + */ +static int sti_gdp_commit_layer(void *lay) +{ + struct sti_layer *layer = (struct sti_layer *)lay; + struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(layer); + struct sti_gdp_node *updated_top_node = updated_list->top_field; + struct sti_gdp_node *updated_btm_node = updated_list->btm_field; + struct sti_gdp *gdp = layer->gdp; + u32 dma_updated_top = virt_to_dma(gdp->dev, updated_top_node); + u32 dma_updated_btm = virt_to_dma(gdp->dev, updated_btm_node); + struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(layer); + + dev_dbg(gdp->dev, "Current NVN:0x%X\n", + readl(gdp->regs + GAM_GDP_NVN_OFFSET)); + dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", + (unsigned long)layer->paddr, + readl(gdp->regs + GAM_GDP_PML_OFFSET)); + + if (curr_list == NULL) { + /* First update or invalid node should directly write in the + * hw register */ + writel(gdp->is_curr_top == true ? + dma_updated_btm : dma_updated_top, + gdp->regs + GAM_GDP_NVN_OFFSET); + return 0; + } + + if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) { + if (gdp->is_curr_top == true) { + /* Do not update in the middle of the frame, but + * postpone the update after the bottom field has + * been displayed */ + curr_list->btm_field->gam_gdp_nvn = dma_updated_top; + } else { + /* Direct update to avoid one frame delay */ + writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); + } + } else { + /* Direct update for progressive to avoid one frame delay */ + writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); + } + + return 0; +} + +/** + * sti_gdp_disable_layer + * @lay: gdp layer + * + * Disable a GDP. + * + * RETURNS: + * 0 on success. + */ +static int sti_gdp_disable_layer(void *lay) +{ + int i; + struct sti_layer *layer = (struct sti_layer *)lay; + struct sti_gdp *gdp = layer->gdp; + + /* Set the nodes as 'to be ignored on mixer' */ + for (i = 0; i < GDP_NODE_NB_BANK; i++) { + gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; + gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; + } + + if (sti_vtg_unregister_client(layer->mixer_id, &gdp->vtg_field_nb)) + DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); + + if (gdp->clk_pix) + clk_disable_unprepare(gdp->clk_pix); + + return 0; +} + +/** + * sti_gdp_field_cb + * @nb: notifier block + * @event: event message + * @data: private data + * + * Handle VTG top field and bottom field event. + * + * RETURNS: + * 0 on success. + */ +int sti_gdp_field_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); + + switch (event) { + case VTG_TOP_FIELD_EVENT: + gdp->is_curr_top = true; + break; + case VTG_BOTTOM_FIELD_EVENT: + gdp->is_curr_top = false; + break; + default: + DRM_ERROR("unsupported event: %lu\n", event); + break; + } + + return 0; +} + +/** + * sti_gdp_create + * @dev: device + * @id: gdp id + * @baseaddr: IO addr + * + * Create a gdp object. Allocate memory and initialize parameters. + * + * + * RETURNS: + * Pointer to the created gdp object. + */ +struct sti_gdp *sti_gdp_create(struct device *dev, int id, + void __iomem *baseaddr) +{ + struct sti_gdp *gdp; + struct device_node *np = dev->of_node; + dma_addr_t dma; + void *base; + int i, size; + + gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); + if (!gdp) { + DRM_ERROR("Failed to allocate memory for GDP\n"); + return NULL; + } + + /* Allocate all the nodes within a single memory page */ + size = sizeof(struct sti_gdp_node) * + GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; + + base = dma_alloc_writecombine(dev, size, &dma, GFP_KERNEL | GFP_DMA); + if (!base) { + DRM_ERROR("Failed to allocate memory for GDP node\n"); + goto mem_err; + } + memset(base, 0, size); + + for (i = 0; i < GDP_NODE_NB_BANK; i++) { + if (virt_to_dma(dev, base) & 0xF) { + DRM_ERROR("Mem alignment failed\n"); + goto mem_err; + } + gdp->node_list[i].top_field = base; + DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); + base += sizeof(struct sti_gdp_node); + + if (virt_to_dma(dev, base) & 0xF) { + DRM_ERROR("Mem alignment failed\n"); + goto mem_err; + } + gdp->node_list[i].btm_field = base; + DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); + base += sizeof(struct sti_gdp_node); + } + + gdp->dev = dev; + gdp->regs = baseaddr; + gdp->get_formats = sti_gdp_get_formats; + gdp->get_nb_formats = sti_gdp_get_nb_formats; + gdp->prepare = sti_gdp_prepare_layer; + gdp->commit = sti_gdp_commit_layer; + gdp->disable = sti_gdp_disable_layer; + gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; + + if (of_device_is_compatible(np, "st,stih407-compositor")) { + /* GDP of STiH407 chip have its own pixel clock */ + char *clk_name; + + switch (id) { + case STI_GDP_0: + clk_name = "pix_gdp1"; + break; + case STI_GDP_1: + clk_name = "pix_gdp2"; + break; + case STI_GDP_2: + clk_name = "pix_gdp3"; + break; + case STI_GDP_3: + clk_name = "pix_gdp4"; + break; + default: + DRM_ERROR("GDP id not recognized\n"); + goto err_clk_pix_gdp; + } + + gdp->clk_pix = devm_clk_get(dev, clk_name); + if (IS_ERR(gdp->clk_pix)) { + DRM_ERROR("Cannot get %s clock\n", clk_name); + goto err_clk_pix_gdp; + } + } + + return gdp; + +err_clk_pix_gdp: +mem_err: + devm_kfree(dev, gdp); + return NULL; +} diff --git a/drivers/gpu/drm/sti/sti_gdp.h b/drivers/gpu/drm/sti/sti_gdp.h new file mode 100644 index 0000000..4f7f40b --- /dev/null +++ b/drivers/gpu/drm/sti/sti_gdp.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_GDP_H_ +#define _STI_GDP_H_ + +#include <linux/types.h> + +#define GDP_NODE_NB_BANK 2 +#define GDP_NODE_PER_FIELD 2 + +struct sti_gdp_node { + u32 gam_gdp_ctl; + u32 gam_gdp_agc; + u32 reserved1; + u32 gam_gdp_vpo; + u32 gam_gdp_vps; + u32 gam_gdp_pml; + u32 gam_gdp_pmp; + u32 gam_gdp_size; + u32 reserved2; + u32 gam_gdp_nvn; + u32 gam_gdp_key1; + u32 gam_gdp_key2; + u32 reserved3; + u32 gam_gdp_ppt; + u32 reserved4; + u32 gam_gdp_cml; +}; + +struct sti_gdp_node_list { + struct sti_gdp_node *top_field; + struct sti_gdp_node *btm_field; +}; + +/* + * STI GDP structure + * + * @device: driver device + * @regs: subdevice register + * @clk_pix: pixel clock for the current gdp + * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification + * @is_curr_top: true if the current node processed is the top field + * @get_formats: get GDP supported formats + * @get_nb_formats: get number of format supported + * @prepare: prepare GDP before rendering + * @commit: set GDP for rendering + * @disable: disable GDP + * @node_list: array of node list + */ +struct sti_gdp { + struct device *dev; + void __iomem *regs; + struct clk *clk_pix; + struct notifier_block vtg_field_nb; + bool is_curr_top; + const uint32_t* (*get_formats)(void); + int (*get_nb_formats)(void); + int (*prepare)(void *layer, bool first_prepare); + int (*commit)(void *layer); + int (*disable)(void *layer); + struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; +}; + +struct sti_gdp *sti_gdp_create(struct device *dev, int id, + void __iomem *baseaddr); + +#endif diff --git a/drivers/gpu/drm/sti/sti_layer.h b/drivers/gpu/drm/sti/sti_layer.h index ed8386a..45cd1ea 100644 --- a/drivers/gpu/drm/sti/sti_layer.h +++ b/drivers/gpu/drm/sti/sti_layer.h @@ -10,6 +10,7 @@ #define _STI_LAYER_H_

#include <drm/drmP.h> +#include "sti_gdp.h"

#define to_sti_layer(x) container_of(x, struct sti_layer, plane)

@@ -67,6 +68,7 @@ struct sti_fps_info { * @offsets: offset of 'planes' * @paddr: physical address of the input buffer * @fps_info: frame per second info + * @gdp: related GDP (if the layer is a GDP) */ struct sti_layer { struct drm_plane plane; @@ -74,6 +76,7 @@ struct sti_layer { struct drm_display_mode *mode; enum sti_layer_desc desc; int zorder; + int mixer_id; bool enabled; int src_x, src_y; int src_w, src_h; @@ -84,12 +87,14 @@ struct sti_layer { int offsets[4]; dma_addr_t paddr; struct sti_fps_info fps_info; + struct sti_gdp *gdp; };

struct sti_layer *sti_layer_create(struct device *dev, int desc, void __iomem *baseaddr); int sti_layer_prepare(struct sti_layer *layer, struct drm_framebuffer *fb, struct drm_display_mode *mode, + int mixer_id, int dest_x, int dest_y, int dest_w, int dest_h, int src_x, int src_y, diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index d3514c1..d1ebe98 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -51,7 +51,10 @@ #define VTG_BOT_V_HD_3 0x0110

/* IRQ mask */ -#define VTG_IRQ_MASK ((1L<<1) | (1L<<0)) +#define VTG_IRQ_TOP_FIELD_MASK (1L << 1) +#define VTG_IRQ_BOTTOM_FIELD_MASK (1L << 0) +#define VTG_IRQ_MASK (VTG_IRQ_TOP_FIELD_MASK | \ + VTG_IRQ_BOTTOM_FIELD_MASK)

/* Delay introduced by the AWG in nb of pixels */ #define AWG_DELAY_HD (-9) @@ -315,8 +318,13 @@ static irqreturn_t vtg_irq_thread(int irq, void *arg) /* sync bus write */ readl(regs + VTG_HOST_ITS);

- raw_notifier_call_chain(&vtg->notifier_list, - VTG_VBLANK_EVENT, &vtg->type); + if (status & VTG_IRQ_TOP_FIELD_MASK) { + raw_notifier_call_chain(&vtg->notifier_list, + VTG_TOP_FIELD_EVENT, &vtg->type); + } else { + raw_notifier_call_chain(&vtg->notifier_list, + VTG_BOTTOM_FIELD_EVENT, &vtg->type); + }

return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/sti/sti_vtg_utils.h b/drivers/gpu/drm/sti/sti_vtg_utils.h index 03d81ba..8992a04 100644 --- a/drivers/gpu/drm/sti/sti_vtg_utils.h +++ b/drivers/gpu/drm/sti/sti_vtg_utils.h @@ -14,7 +14,8 @@ #define VTG_MAIN 0 #define VTG_AUX 1

-#define VTG_VBLANK_EVENT 1 +#define VTG_TOP_FIELD_EVENT 1 +#define VTG_BOTTOM_FIELD_EVENT 2

int sti_vtg_setconfig(int main_aux, const struct drm_display_mode *mode); int sti_vtg_register_client(int main_aux, struct notifier_block *nb);

Mixer hardware IP is responsible of mixing the different inputs layers. Z-order is managed by the mixer. We could 2 mixers: one for main path and one for auxilary path

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Makefile | 1 + drivers/gpu/drm/sti/sti_mixer.c | 241 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_mixer.h | 52 +++++++++ 3 files changed, 294 insertions(+) create mode 100644 drivers/gpu/drm/sti/sti_mixer.c create mode 100644 drivers/gpu/drm/sti/sti_mixer.h

diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index 03c8d98..3712435 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -1,6 +1,7 @@ ccflags-y := -Iinclude/drm

stidrm-y := \ + sti_mixer.o \ sti_gdp.o \ sti_vid.o \ sti_tvout.o \ diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c new file mode 100644 index 0000000..ab8daf6 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include "sti_mixer.h" +#include "sti_vtg_utils.h" + +/* Identity: G=Y , B=Cb , R=Cr */ +static const u32 MixerColorSpaceMatIdentity[] = { + 0x10000000, 0x00000000, 0x10000000, 0x00001000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +/* regs offset */ +#define GAM_MIXER_MAIN_CTL 0x00 +#define GAM_MIXER_MAIN_BKC 0x04 +#define GAM_MIXER_MAIN_BCO 0x0C +#define GAM_MIXER_MAIN_BCS 0x10 +#define GAM_MIXER_MAIN_AVO 0x28 +#define GAM_MIXER_MAIN_AVS 0x2C +#define GAM_MIXER_MAIN_CRB 0x34 +#define GAM_MIXER_MAIN_ACT 0x38 +#define GAM_MIXER_MAIN_MBP 0x3C +#define GAM_MIXER_MAIN_MX0 0x80 + +/* id for depth of CRB reg */ +#define GAM_DEPTH_VID0_ID 1 +#define GAM_DEPTH_VID1_ID 2 +#define GAM_DEPTH_GDP0_ID 3 +#define GAM_DEPTH_GDP1_ID 4 +#define GAM_DEPTH_GDP2_ID 5 +#define GAM_DEPTH_GDP3_ID 6 +#define GAM_DEPTH_MASK_ID 7 + +/* mask in CTL reg */ +#define GAM_CTL_BACK_MASK (1 << 0) +#define GAM_CTL_VID0_MASK (1 << 1) +#define GAM_CTL_VID1_MASK (1 << 2) +#define GAM_CTL_GDP0_MASK (1 << 3) +#define GAM_CTL_GDP1_MASK (1 << 4) +#define GAM_CTL_GDP2_MASK (1 << 5) +#define GAM_CTL_GDP3_MASK (1 << 6) + +const char *sti_mixer_to_str(struct sti_mixer *mixer) +{ + switch (mixer->id) { + case STI_MIXER_MAIN: + return "MAIN_MIXER"; + case STI_MIXER_AUX: + return "AUX_MIXER"; + default: + return "<UNKNOWN MIXER>"; + } +} + +static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id) +{ + return readl(mixer->regs + reg_id); +} + +static inline void sti_mixer_reg_write(struct sti_mixer *mixer, + u32 reg_id, u32 val) +{ + writel(val, mixer->regs + reg_id); +} + +static inline void sti_mixer_reg_writemask(struct sti_mixer *mixer, + u32 reg_id, u32 val, u32 mask) +{ + u32 old = sti_mixer_reg_read(mixer, reg_id); + + val = (val & mask) | (old & ~mask); + writel(val, mixer->regs + reg_id); +} + +void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable) +{ + sti_mixer_reg_writemask(mixer, + GAM_MIXER_MAIN_CTL, enable, GAM_CTL_BACK_MASK); +} + +static void sti_mixer_set_background_color(struct sti_mixer *mixer, + int red, int green, int blue) +{ + u32 val = (red << 16) | (green << 8) | blue; + + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BKC, val); +} + +static void sti_mixer_set_background_area(struct sti_mixer *mixer, + struct drm_display_mode *mode) +{ + u32 ydo, xdo, yds, xds; + + ydo = sti_vtg_get_line_number(*mode, 0); + yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); + xdo = sti_vtg_get_pixel_number(*mode, 0); + xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); + + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BCO, ydo << 16 | xdo); + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BCS, yds << 16 | xds); +} + +int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer) +{ + int layer_id = 0, depth = layer->zorder; + u32 mask; + + if (depth >= GAM_MIXER_NB_DEPTH_LEVEL) + return 1; + + switch (layer->desc) { + case STI_GDP_0: + layer_id = GAM_DEPTH_GDP0_ID; + break; + case STI_GDP_1: + layer_id = GAM_DEPTH_GDP1_ID; + break; + case STI_GDP_2: + layer_id = GAM_DEPTH_GDP2_ID; + break; + case STI_GDP_3: + layer_id = GAM_DEPTH_GDP3_ID; + break; + case STI_VID_0: + layer_id = GAM_DEPTH_VID0_ID; + break; + case STI_VID_1: + layer_id = GAM_DEPTH_VID1_ID; + break; + default: + DRM_ERROR("Unknown layer %d\n", layer->desc); + return 1; + } + mask = GAM_DEPTH_MASK_ID << (3 * depth); + layer_id = layer_id << (3 * depth); + + dev_dbg(mixer->dev, "GAM_MIXER_MAIN_CRB val 0x%x mask 0x%x\n", + layer_id, mask); + sti_mixer_reg_writemask(mixer, GAM_MIXER_MAIN_CRB, layer_id, mask); + + dev_dbg(mixer->dev, "Read GAM_MIXER_MAIN_CRB 0x%x\n", + sti_mixer_reg_read(mixer, GAM_MIXER_MAIN_CRB)); + return 0; +} + +int sti_mixer_active_video_area(struct sti_mixer *mixer, + struct drm_display_mode *mode) +{ + u32 ydo, xdo, yds, xds; + + ydo = sti_vtg_get_line_number(*mode, 0); + yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); + xdo = sti_vtg_get_pixel_number(*mode, 0); + xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); + + DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n", + sti_mixer_to_str(mixer), xdo, ydo, xds, yds); + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_AVO, ydo << 16 | xdo); + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_AVS, yds << 16 | xds); + + sti_mixer_set_background_color(mixer, 0xFF, 0, 0); + + sti_mixer_set_background_area(mixer, mode); + sti_mixer_set_background_status(mixer, true); + return 0; +} + +static u32 sti_mixer_get_layer_mask(struct sti_layer *layer) +{ + switch (layer->desc) { + case STI_BACK: + return GAM_CTL_BACK_MASK; + case STI_GDP_0: + return GAM_CTL_GDP0_MASK; + case STI_GDP_1: + return GAM_CTL_GDP1_MASK; + case STI_GDP_2: + return GAM_CTL_GDP2_MASK; + case STI_GDP_3: + return GAM_CTL_GDP3_MASK; + case STI_VID_0: + return GAM_CTL_VID0_MASK; + case STI_VID_1: + return GAM_CTL_VID1_MASK; + default: + return 0; + } +} + +int sti_mixer_set_layer_status(struct sti_mixer *mixer, + struct sti_layer *layer, bool status) +{ + u32 mask, val; + + mask = sti_mixer_get_layer_mask(layer); + if (!mask) { + DRM_ERROR("Can not find layer mask\n"); + return -1; + } + val = status ? mask : 0; + sti_mixer_reg_writemask(mixer, GAM_MIXER_MAIN_CTL, val, mask); + return 0; +} + +void sti_mixer_set_matrix(struct sti_mixer *mixer) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(MixerColorSpaceMatIdentity); i++) + sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_MX0 + (i * 4), + MixerColorSpaceMatIdentity[i]); +} + +struct sti_mixer *sti_mixer_create(struct device *dev, int id, + void __iomem *baseaddr) +{ + struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); + struct device_node *np = dev->of_node; + + dev_dbg(dev, "%s\n", __func__); + if (!mixer) { + DRM_ERROR("Failed to allocated memory for mixer\n"); + return NULL; + } + mixer->regs = baseaddr; + mixer->dev = dev; + mixer->id = id; + + if (of_device_is_compatible(np, "st,stih416-compositor")) + sti_mixer_set_matrix(mixer); + + DRM_DEBUG_DRIVER("%s created. Regs=%p\n", + sti_mixer_to_str(mixer), mixer->regs); + + return mixer; +} diff --git a/drivers/gpu/drm/sti/sti_mixer.h b/drivers/gpu/drm/sti/sti_mixer.h new file mode 100644 index 0000000..a05e21f --- /dev/null +++ b/drivers/gpu/drm/sti/sti_mixer.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_MIXER_H_ +#define _STI_MIXER_H_ + +#include <drm/drmP.h> + +#include "sti_layer.h" + +#define to_sti_mixer(x) container_of(x, struct sti_mixer, drm_crtc) + +/* + * STI Mixer subdevice structure + * + * @dev: driver device + * @regs: mixer registers + * @id: id of the mixer + * @drm_crtc: crtc object link to the mixer + */ +struct sti_mixer { + struct device *dev; + void __iomem *regs; + int id; + struct drm_crtc drm_crtc; +}; + +const char *sti_mixer_to_str(struct sti_mixer *mixer); + +struct sti_mixer *sti_mixer_create(struct device *dev, int id, + void __iomem *baseaddr); + +int sti_mixer_set_layer_status(struct sti_mixer *mixer, + struct sti_layer *layer, bool status); +int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer); +int sti_mixer_active_video_area(struct sti_mixer *mixer, + struct drm_display_mode *mode); + +void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable); + +/* depth in Cross-bar control = z order */ +#define GAM_MIXER_NB_DEPTH_LEVEL 7 + +#define STI_MIXER_MAIN 0 +#define STI_MIXER_AUX 1 + +#endif

Allow to get more detailed debug information on GDP

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/sti_drm_drv.h | 44 +++++++ drivers/gpu/drm/sti/sti_gdp.c | 235 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_gdp.h | 2 + 3 files changed, 281 insertions(+) create mode 100644 drivers/gpu/drm/sti/sti_drm_drv.h

diff --git a/drivers/gpu/drm/sti/sti_drm_drv.h b/drivers/gpu/drm/sti/sti_drm_drv.h new file mode 100644 index 0000000..2633d84 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_drv.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_DRM_DRV_H_ +#define _STI_DRM_DRV_H_ + +#include <linux/platform_device.h> + +#include <drm/drmP.h> + +#include "sti_compositor.h" +#include "sti_tvout.h" + +extern struct platform_driver sti_compositor_driver; +extern struct platform_driver sti_vtac_tx_driver; +extern struct platform_driver sti_vtac_rx_driver; +extern struct platform_driver sti_vtg_driver; +extern struct platform_driver sti_tvout_driver; +extern struct platform_driver sti_hdmi_driver; +extern struct platform_driver sti_hda_driver; + +/* + * STI drm private structure + * This structure is stored as private in the drm_device + * + * @compo: compositor + * @tvout: TV OUT + * @pageflip_evt_list: list of pending page flip requests + * @plane_zorder_property: z-order property for CRTC planes + */ +struct sti_drm_private { + struct sti_compositor *compo; + struct sti_tvout *tvout; + struct list_head pageflip_evt_list; + struct drm_property *plane_zorder_property; +}; + +#define STI_MAX_FB_HEIGHT 4096 +#define STI_MAX_FB_WIDTH 4096 + +#endif diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c index 00ff7f9..095d707 100644 --- a/drivers/gpu/drm/sti/sti_gdp.c +++ b/drivers/gpu/drm/sti/sti_gdp.c @@ -9,9 +9,11 @@ #include <linux/clk.h> #include <linux/dma-mapping.h>

+#include "sti_drm_drv.h" #include "sti_layer.h" #include "sti_gdp.h" #include "sti_vtg_utils.h" +#include "sti_compositor.h"

#define ENA_COLOR_FILL (1 << 8) #define WAIT_NEXT_VSYNC (1 << 31) @@ -29,6 +31,25 @@ #define GDP_YCBR422R 0x12 #define GDP_AYCBR8888 0x15

+#define GDP2STR(fmt) { GDP_ ## fmt, #fmt } + +static struct gdp_format_to_str { + int format; + char name[20]; +} sti_gdp_format_to_str[] = { + GDP2STR(RGB565), + GDP2STR(RGB888), + GDP2STR(RGB888_32), + GDP2STR(ARGB8565), + GDP2STR(ARGB8888), + GDP2STR(ARGB1555), + GDP2STR(ARGB4444), + GDP2STR(CLUT8), + GDP2STR(YCBR888), + GDP2STR(YCBR422R), + GDP2STR(AYCBR8888) + }; + #define GAM_GDP_CTL_OFFSET 0x00 #define GAM_GDP_AGC_OFFSET 0x04 #define GAM_GDP_VPO_OFFSET 0x0C @@ -137,6 +158,9 @@ static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_layer *layer) return &gdp->node_list[i];

end: + DRM_DEBUG_DRIVER("Warning, inconsistent NVN for %s: 0x%08X\n", + sti_layer_to_str(layer), hw_nvn); + return &gdp->node_list[0]; }

@@ -169,6 +193,8 @@ struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_layer *layer) return &gdp->node_list[i];

end: + DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", + hw_nvn, sti_layer_to_str(layer)); return NULL; }

@@ -198,6 +224,9 @@ static int sti_gdp_prepare_layer(void *lay, bool first_prepare) top_field = list->top_field; btm_field = list->btm_field;

+ dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, + sti_layer_to_str(layer), top_field, btm_field); + /* Build the top field from layer params */ top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; @@ -294,6 +323,9 @@ static int sti_gdp_commit_layer(void *lay) u32 dma_updated_btm = virt_to_dma(gdp->dev, updated_btm_node); struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(layer);

+ dev_dbg(gdp->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__, + sti_layer_to_str(layer), + updated_top_node, updated_btm_node); dev_dbg(gdp->dev, "Current NVN:0x%X\n", readl(gdp->regs + GAM_GDP_NVN_OFFSET)); dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", @@ -303,6 +335,8 @@ static int sti_gdp_commit_layer(void *lay) if (curr_list == NULL) { /* First update or invalid node should directly write in the * hw register */ + DRM_DEBUG_DRIVER("%s first update (or invalid node)", + sti_layer_to_str(layer)); writel(gdp->is_curr_top == true ? dma_updated_btm : dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); @@ -342,6 +376,8 @@ static int sti_gdp_disable_layer(void *lay) struct sti_layer *layer = (struct sti_layer *)lay; struct sti_gdp *gdp = layer->gdp;

+ DRM_DEBUG_DRIVER("%s\n", sti_layer_to_str(layer)); + /* Set the nodes as 'to be ignored on mixer' */ for (i = 0; i < GDP_NODE_NB_BANK; i++) { gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; @@ -489,3 +525,202 @@ mem_err: devm_kfree(dev, gdp); return NULL; } + +static void sti_gdp_dbg_ctl(struct seq_file *m, int val) +{ + int i; + + seq_puts(m, "\tColor:"); + for (i = 0; i < ARRAY_SIZE(sti_gdp_format_to_str); i++) { + if (sti_gdp_format_to_str[i].format == (val & 0x1F)) { + seq_printf(m, sti_gdp_format_to_str[i].name); + break; + } + } + if (i == ARRAY_SIZE(sti_gdp_format_to_str)) + seq_puts(m, "<UNKNOWN>"); + + seq_printf(m, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); +} + +static void sti_gdp_dbg_vpo(struct seq_file *m, int val) +{ + seq_printf(m, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); +} + +static void sti_gdp_dbg_vps(struct seq_file *m, int val) +{ + seq_printf(m, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF); +} + +static void sti_gdp_dbg_size(struct seq_file *m, int val) +{ + seq_printf(m, "\t%d x %d", val & 0x07FF, (val >> 16) & 0x07FF); +} + +static void sti_gdp_dbg_nvn(struct seq_file *m, struct device *dev, int val) +{ + seq_puts(m, "\tVirt @: "); + if (val) + seq_printf(m, "%p", dma_to_virt(dev, (dma_addr_t) val)); +} + +static void sti_gdp_dbg_ppt(struct seq_file *m, int val) +{ + if (val & GAM_GDP_PPT_IGNORE) + seq_puts(m, "\tNot displayed on mixer!"); +} + +static void sti_gdp_dbg_mst(struct seq_file *m, int val) +{ + if (val & 1) + seq_puts(m, "\tBUFFER UNDERFLOW!"); +} + +#define GDP_DBG_DUMP(reg) seq_printf(m, "\n " #reg "\t 0x%08X", \ + readl(gdp->regs + reg ## _OFFSET)) + +int sti_gdp_dbg_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + int i, ret; + + ret = mutex_lock_interruptible(&dev->struct_mutex); + if (ret) + return ret; + + if (compo == NULL) { + seq_puts(m, "No compositor available\n"); + goto out; + } + + for (i = 0; i < compo->nb_layers; i++) { + struct drm_plane *plane; + struct drm_crtc *crtc; + struct drm_framebuffer *fb; + struct sti_layer *layer = compo->layer[i]; + struct sti_gdp *gdp = layer->gdp; + if ((layer->desc & STI_LAYER_TYPE_MASK) != STI_GDP) + continue; + seq_printf(m, "\n%s (associated with the mixer_id %d)", + sti_layer_to_str(layer), layer->mixer_id); + seq_printf(m, "\t %d frame updates", + layer->fps_info.curr_frame_counter); + + GDP_DBG_DUMP(GAM_GDP_CTL); + sti_gdp_dbg_ctl(m, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_AGC); + GDP_DBG_DUMP(GAM_GDP_VPO); + sti_gdp_dbg_vpo(m, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_VPS); + sti_gdp_dbg_vps(m, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_PML); + GDP_DBG_DUMP(GAM_GDP_PMP); + GDP_DBG_DUMP(GAM_GDP_SIZE); + sti_gdp_dbg_size(m, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_NVN); + sti_gdp_dbg_nvn(m, gdp->dev, + readl(gdp->regs + GAM_GDP_NVN_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_KEY1); + GDP_DBG_DUMP(GAM_GDP_KEY2); + GDP_DBG_DUMP(GAM_GDP_PPT); + sti_gdp_dbg_ppt(m, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); + GDP_DBG_DUMP(GAM_GDP_CML); + GDP_DBG_DUMP(GAM_GDP_MST); + sti_gdp_dbg_mst(m, readl(gdp->regs + GAM_GDP_MST_OFFSET)); + seq_puts(m, "\n"); + + plane = &layer->plane; + if (!plane->base.id) { + seq_puts(m, " Not connected to any DRM PLANE\n"); + continue; + } + seq_printf(m, " Connected to DRM PLANE #%d which is:\n", + plane->base.id); + + crtc = plane->crtc; + if (!crtc) { + seq_puts(m, "\tNot connected to any DRM CRTC\n"); + continue; + } + seq_printf(m, "\tConnected to DRM CRTC #%d\n", crtc->base.id); + + fb = crtc->fb; + if (!fb) { + seq_puts(m, "\tNot connected to any DRM FB\n"); + continue; + } + seq_printf(m, "\tConnected to DRM FB #%d, %dx%d, %.4s\n", + fb->base.id, + fb->width, fb->height, (char *)&fb->pixel_format); + } + +out: + mutex_unlock(&dev->struct_mutex); + return 0; +} + +static void sti_gdp_node_dump_node(struct seq_file *m, + struct sti_gdp_node *node) +{ + seq_printf(m, "\t@:0x%p", node); + seq_printf(m, "\n\tCTL 0x%08X", node->gam_gdp_ctl); + sti_gdp_dbg_ctl(m, node->gam_gdp_ctl); + seq_printf(m, "\n\tAGC 0x%08X", node->gam_gdp_agc); + seq_printf(m, "\n\tVPO 0x%08X", node->gam_gdp_vpo); + sti_gdp_dbg_vpo(m, node->gam_gdp_vpo); + seq_printf(m, "\n\tVPS 0x%08X", node->gam_gdp_vps); + sti_gdp_dbg_vps(m, node->gam_gdp_vps); + seq_printf(m, "\n\tPML 0x%08X", node->gam_gdp_pml); + seq_printf(m, "\n\tPMP 0x%08X", node->gam_gdp_pmp); + seq_printf(m, "\n\tSIZE 0x%08X", node->gam_gdp_size); + sti_gdp_dbg_size(m, node->gam_gdp_size); + seq_printf(m, "\n\tNVN 0x%08X", node->gam_gdp_nvn); + seq_printf(m, "\n\tKEY1 0x%08X", node->gam_gdp_key1); + seq_printf(m, "\n\tKEY2 0x%08X", node->gam_gdp_key2); + seq_printf(m, "\n\tPPT 0x%08X", node->gam_gdp_ppt); + sti_gdp_dbg_ppt(m, node->gam_gdp_ppt); + seq_printf(m, "\n\tCML 0x%08X", node->gam_gdp_cml); + seq_puts(m, "\n"); +} + +int sti_gdp_node_dbg_show(struct seq_file *m, void *arg) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + int i, ret; + + ret = mutex_lock_interruptible(&dev->struct_mutex); + if (ret) + return ret; + + if (!compo) { + seq_puts(m, "No compositor available\n"); + goto out; + } + + for (i = 0; i < compo->nb_layers; i++) { + int b; + struct sti_layer *layer = compo->layer[i]; + struct sti_gdp *gdp = layer->gdp; + if ((layer->desc & STI_LAYER_TYPE_MASK) != STI_GDP) + continue; + + for (b = 0; b < GDP_NODE_NB_BANK; b++) { + seq_printf(m, "\n%s[%d].top", + sti_layer_to_str(layer), b); + sti_gdp_node_dump_node(m, gdp->node_list[b].top_field); + seq_printf(m, "\n%s[%d].btm", + sti_layer_to_str(layer), b); + sti_gdp_node_dump_node(m, gdp->node_list[b].btm_field); + } + } +out: + mutex_unlock(&dev->struct_mutex); + return 0; +} diff --git a/drivers/gpu/drm/sti/sti_gdp.h b/drivers/gpu/drm/sti/sti_gdp.h index 4f7f40b..84875ff 100644 --- a/drivers/gpu/drm/sti/sti_gdp.h +++ b/drivers/gpu/drm/sti/sti_gdp.h @@ -69,5 +69,7 @@ struct sti_gdp {

struct sti_gdp *sti_gdp_create(struct device *dev, int id, void __iomem *baseaddr); +int sti_gdp_dbg_show(struct seq_file *m, void *arg); +int sti_gdp_node_dbg_show(struct seq_file *m, void *arg);

#endif

Use debugfs to dump information about TVout

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/sti_tvout.c | 181 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+)

diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index df9a2c3..3b2cf3a 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -17,6 +17,7 @@ #include "sti_tvout.h" #include "sti_hdmi.h" #include "sti_hda.h" +#include "sti_drm_drv.h"

/* glue regsiters */ #define TVO_CSC_MAIN_M0 0x000 @@ -604,6 +605,186 @@ void sti_tvout_disable(struct sti_tvout *tvout, connector->stop(connector); }

+/* + * Debugfs + */ +#define TVOUT_DBG_DUMP(reg) seq_printf(m, "\n %-25s 0x%08X", #reg, \ + readl(tvout->regs + reg)) +#define TVOUT_CONNECTOR_NAME_MAX_LENGHT 10 +#define MAX_STRING_LENGTH 55 + +static int sti_tvout_dbg_type_to_connector_name(enum sti_tvout_connector_type + type, char *name) +{ + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + snprintf(name, TVOUT_CONNECTOR_NAME_MAX_LENGHT, "HDMI"); + break; + case STI_TVOUT_CONNECTOR_HDA: + snprintf(name, TVOUT_CONNECTOR_NAME_MAX_LENGHT, "HD Analog"); + break; + default: + return -1; + } + + return 0; +} + +static void tvout_dbg_vip(struct seq_file *m, int val) +{ + int r, g, b, tmp, mask; + char str[MAX_STRING_LENGTH]; + static const char *const reorder[] = { "Y_G", "Cb_B", "Cr_R" }; + static const char *const clipping[] = { "No", "EAV/SAV", + "Limited range RGB/Y", "Limited range Cb/Cr", + "decided by register" }; + static const char *const round[] = { "8-bit", "10-bit", "12-bit" }; + static const char *const input_sel[] = { "Main (color matrix enabled)", + "Main (color matrix by-passed)", "", "", "", "", "", "", + "Aux (color matrix enabled)", "Aux (color matrix by-passed)", + "", "", "", "", "", "Force value" + }; + + seq_puts(m, "\t"); + + mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT; + r = (val & mask) >> TVO_VIP_REORDER_R_SHIFT; + mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT; + g = (val & mask) >> TVO_VIP_REORDER_G_SHIFT; + mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT; + b = (val & mask) >> TVO_VIP_REORDER_B_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "Reorder: %s->%s %s->%s %s->%s", + reorder[r], reorder[TVO_VIP_REORDER_CR_R_SEL], + reorder[g], reorder[TVO_VIP_REORDER_Y_G_SEL], + reorder[b], reorder[TVO_VIP_REORDER_CB_B_SEL]); + seq_printf(m, "%-55s", str); + + mask = TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT; + tmp = (val & mask) >> TVO_VIP_CLIP_SHIFT; + snprintf(str, MAX_STRING_LENGTH, "Clipping: %s", clipping[tmp]); + seq_printf(m, "%-55s", str); + + seq_printf(m, "\n%-40s", ""); + + mask = TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT; + tmp = (val & mask) >> TVO_VIP_RND_SHIFT; + snprintf(str, MAX_STRING_LENGTH, + "Round: input data rounded to %s per component", round[tmp]); + seq_printf(m, "%-55s", str); + + tmp = (val & TVO_VIP_SEL_INPUT_MASK); + snprintf(str, MAX_STRING_LENGTH, "Input selection: %s", input_sel[tmp]); + seq_printf(m, "%-55s", str); +} + +static void tvout_dbg_hd_dac_cfg(struct seq_file *m, int val) +{ + seq_puts(m, "\t HD DAC "); + seq_puts(m, val & 1 ? "disabled" : "enabled"); +} + +static int tvout_dbg_show(struct seq_file *m, + enum sti_tvout_connector_type type) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_tvout *tvout = dev_priv->tvout; + struct sti_tvout_connector *connector = tvout->connector[type]; + char name[TVOUT_CONNECTOR_NAME_MAX_LENGHT]; + int ret; + + if (!connector) + return -1; + + if (!connector->is_enabled) + return -1; + + ret = mutex_lock_interruptible(&dev->struct_mutex); + if (ret) + return ret; + + if (tvout == NULL) { + seq_puts(m, "No tvout available"); + goto out; + } + + ret = sti_tvout_dbg_type_to_connector_name(type, name); + if (ret) { + seq_puts(m, "No connector!"); + goto out; + } + + seq_printf(m, "\n%s connector: ", name); + seq_printf(m, "\nTVOUT: (virt base addr = 0x%p)", tvout->regs); + if (connector->is_enabled(connector)) { + if (connector->main_path) { + seq_puts(m, "\n Connected to the main path"); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M0); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M1); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M2); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M3); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M4); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M5); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M6); + TVOUT_DBG_DUMP(TVO_CSC_MAIN_M7); + TVOUT_DBG_DUMP(TVO_MAIN_IN_VID_FORMAT); + } else { + seq_puts(m, "\n Connected to the auxiliary path"); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M0); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M2); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M3); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M4); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M5); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M6); + TVOUT_DBG_DUMP(TVO_CSC_AUX_M7); + TVOUT_DBG_DUMP(TVO_AUX_IN_VID_FORMAT); + } + } else + seq_puts(m, " Disabled"); + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + TVOUT_DBG_DUMP(TVO_VIP_HDMI); + tvout_dbg_vip(m, readl(tvout->regs + TVO_VIP_HDMI)); + TVOUT_DBG_DUMP(TVO_HDMI_FORCE_COLOR_0); + TVOUT_DBG_DUMP(TVO_HDMI_FORCE_COLOR_1); + TVOUT_DBG_DUMP(TVO_HDMI_CLIP_VALUE_B_CB); + TVOUT_DBG_DUMP(TVO_HDMI_CLIP_VALUE_Y_G); + TVOUT_DBG_DUMP(TVO_HDMI_CLIP_VALUE_R_CR); + TVOUT_DBG_DUMP(TVO_HDMI_SYNC_SEL); + TVOUT_DBG_DUMP(TVO_HDMI_DFV_OBS); + break; + case STI_TVOUT_CONNECTOR_HDA: + TVOUT_DBG_DUMP(TVO_VIP_HDF); + tvout_dbg_vip(m, readl(tvout->regs + TVO_VIP_HDF)); + TVOUT_DBG_DUMP(TVO_HD_SYNC_SEL); + TVOUT_DBG_DUMP(TVO_HD_DAC_CFG_OFF); + tvout_dbg_hd_dac_cfg(m, + readl(tvout->regs + TVO_HD_DAC_CFG_OFF)); + break; + default: + goto out; + } + + if (connector->dbg_show) + connector->dbg_show(connector, m); +out: + seq_puts(m, "\n\n"); + mutex_unlock(&dev->struct_mutex); + return 0; +} + +int sti_tvout_hdmi_dbg_show(struct seq_file *m, void *arg) +{ + return tvout_dbg_show(m, STI_TVOUT_CONNECTOR_HDMI); +} + +int sti_tvout_hda_dbg_show(struct seq_file *m, void *arg) +{ + return tvout_dbg_show(m, STI_TVOUT_CONNECTOR_HDA); +} + static int sti_tvout_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev;

Make the link between all the hardware drivers and DRM/KMS interface. Create the driver itself and make it register all the sub-components. Use GEM CMA helpers for buffer allocation.

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/Kconfig | 8 + drivers/gpu/drm/sti/Makefile | 28 +- drivers/gpu/drm/sti/sti_compositor.c | 2 + drivers/gpu/drm/sti/sti_drm_connector.c | 195 +++++++++++++ drivers/gpu/drm/sti/sti_drm_connector.h | 16 ++ drivers/gpu/drm/sti/sti_drm_crtc.c | 440 ++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_drm_crtc.h | 21 ++ drivers/gpu/drm/sti/sti_drm_drv.c | 466 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/sti/sti_drm_encoder.c | 201 ++++++++++++++ drivers/gpu/drm/sti/sti_drm_encoder.h | 16 ++ drivers/gpu/drm/sti/sti_drm_plane.c | 195 +++++++++++++ drivers/gpu/drm/sti/sti_drm_plane.h | 16 ++ drivers/gpu/drm/sti/sti_vtg_utils.h | 2 + 13 files changed, 1594 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/sti/sti_drm_connector.c create mode 100644 drivers/gpu/drm/sti/sti_drm_connector.h create mode 100644 drivers/gpu/drm/sti/sti_drm_crtc.c create mode 100644 drivers/gpu/drm/sti/sti_drm_crtc.h create mode 100644 drivers/gpu/drm/sti/sti_drm_drv.c create mode 100644 drivers/gpu/drm/sti/sti_drm_encoder.c create mode 100644 drivers/gpu/drm/sti/sti_drm_encoder.h create mode 100644 drivers/gpu/drm/sti/sti_drm_plane.c create mode 100644 drivers/gpu/drm/sti/sti_drm_plane.h

diff --git a/drivers/gpu/drm/sti/Kconfig b/drivers/gpu/drm/sti/Kconfig index a958398..61c8bd4 100644 --- a/drivers/gpu/drm/sti/Kconfig +++ b/drivers/gpu/drm/sti/Kconfig @@ -1,10 +1,18 @@ config DRM_STI tristate "DRM Support for STMicroelectronics SoC stiH41x Series" depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) + select DRM_KMS_HELPER + select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER help Choose this option to enable DRM on STM stiH41x chipset

+config DRM_STI_FBDEV + tristate "DRM frame buffer device for STMicroelectronics SoC stiH41x Serie" + depends on DRM_STI + help + Choose this option to enable FBDEV on top of DRM for STM stiH41x chipset + config VTAC_STI tristate "Video Trafic Advance Communication Rx and Tx for STMicroelectronics SoC stiH41x Series" depends on DRM_STI diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile index d598adc..17b4a68 100644 --- a/drivers/gpu/drm/sti/Makefile +++ b/drivers/gpu/drm/sti/Makefile @@ -1,17 +1,21 @@ ccflags-y := -Iinclude/drm

-stidrm-y := \ - sti_compositor.o \ - sti_mixer.o \ - sti_layer.o \ - sti_gdp.o \ - sti_vid.o \ - sti_tvout.o \ - sti_hdmi.o \ - sti_hdmi_tx3g0c55phy.o \ - sti_hdmi_tx3g4c28phy.o \ - sti_hda.o \ - sti_ddc.o +stidrm-y := sti_drm_drv.o \ + sti_drm_crtc.o \ + sti_drm_plane.o \ + sti_drm_connector.o \ + sti_drm_encoder.o \ + sti_compositor.o \ + sti_mixer.o \ + sti_layer.o \ + sti_gdp.o \ + sti_vid.o \ + sti_tvout.o \ + sti_hdmi.o \ + sti_hdmi_tx3g0c55phy.o \ + sti_hdmi_tx3g4c28phy.o \ + sti_hda.o \ + sti_ddc.o

obj-$(CONFIG_DRM_STI) += stidrm.o obj-$(CONFIG_VTAC_STI) += sti_vtac_tx.o sti_vtac_rx.o diff --git a/drivers/gpu/drm/sti/sti_compositor.c b/drivers/gpu/drm/sti/sti_compositor.c index a163344..4d8d0958 100644 --- a/drivers/gpu/drm/sti/sti_compositor.c +++ b/drivers/gpu/drm/sti/sti_compositor.c @@ -14,6 +14,7 @@

#include "sti_compositor.h" #include "sti_gdp.h" +#include "sti_drm_crtc.h"

static const struct of_device_id compositor_match_types[];

@@ -98,6 +99,7 @@ static int sti_compositor_probe(struct platform_device *pdev) } DRM_DEBUG_DRIVER("Compositor %p\n", compo); compo->dev = dev; + compo->vtg_vblank_nb.notifier_call = sti_drm_crtc_vblank_cb;

/* populate data structure depending on compatibility */ BUG_ON(!of_match_node(compositor_match_types, np)->data); diff --git a/drivers/gpu/drm/sti/sti_drm_connector.c b/drivers/gpu/drm/sti/sti_drm_connector.c new file mode 100644 index 0000000..b34a402 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_connector.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> + +#include "sti_drm_connector.h" +#include "sti_drm_drv.h" + +#define to_sti_connector(x) container_of(x, struct sti_connector, drm_connector) + +/* + * sti specific connector structure + * + * @drm_encoder: connector object + * @encoder: associated encoder + * @tvout: pointer on tvout driver + * @type: tvout connector type + */ +struct sti_connector { + struct drm_connector drm_connector; + struct drm_encoder *encoder; + struct sti_tvout *tvout; + enum sti_tvout_connector_type type; +}; + +static int sti_drm_connector_get_modes(struct drm_connector *connector) +{ + struct sti_connector *sti_connector = to_sti_connector(connector); + struct drm_device *dev = connector->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + return sti_tvout_get_modes(sti_connector->tvout, sti_connector->type, + connector); +} + +static int sti_drm_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct sti_connector *sti_connector = to_sti_connector(connector); + struct drm_device *dev = connector->dev; + int ret = MODE_BAD; + + dev_dbg(dev->dev, "%s\n", __func__); + + if (!sti_tvout_check_mode + (sti_connector->tvout, sti_connector->type, mode)) + ret = MODE_OK; + + return ret; +} + +struct drm_encoder *sti_drm_best_encoder(struct drm_connector *connector) +{ + struct sti_connector *sti_connector = to_sti_connector(connector); + struct drm_device *dev = connector->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + /* Best encoder is the one associated during connector creation */ + return sti_connector->encoder; +} + +static struct drm_connector_helper_funcs sti_drm_connector_helper_funcs = { + .get_modes = sti_drm_connector_get_modes, + .mode_valid = sti_drm_connector_mode_valid, + .best_encoder = sti_drm_best_encoder, +}; + +static void sti_drm_connector_dpms(struct drm_connector *connector, int mode) +{ + struct drm_device *dev = connector->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + drm_helper_connector_dpms(connector, mode); +} + +/* get detection status of display device. */ +static enum drm_connector_status +sti_drm_connector_detect(struct drm_connector *connector, bool force) +{ + enum drm_connector_status status = connector_status_disconnected; + struct sti_connector *sti_connector = to_sti_connector(connector); + struct drm_device *dev = connector->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + if (sti_tvout_connector_detect(sti_connector->tvout, + sti_connector->type)) + status = connector_status_connected; + + return status; +} + +static void sti_drm_connector_destroy(struct drm_connector *connector) +{ + struct sti_connector *sti_connector = to_sti_connector(connector); + struct drm_device *dev = connector->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + kfree(sti_connector); +} + +static struct drm_connector_funcs sti_drm_connector_funcs = { + .dpms = sti_drm_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = sti_drm_connector_detect, + .destroy = sti_drm_connector_destroy, +}; + +struct drm_connector *sti_drm_connector_create(struct drm_device *dev, + struct sti_tvout *tvout, + struct drm_encoder *encoder, + enum sti_tvout_connector_type + type) +{ + struct sti_connector *sti_connector; + struct drm_connector *connector; + int connector_type; + int err; + + dev_dbg(dev->dev, "%s\n", __func__); + + /* Create the tvout connector according to the type */ + tvout->connector[type] = tvout->connector_create[type] (tvout); + if (!tvout->connector[type]) { + DRM_INFO("%s: failed to create connector (type = %d)\n", + __func__, type); + return NULL; + } + + sti_connector = kzalloc(sizeof(*sti_connector), GFP_KERNEL); + if (!sti_connector) { + DRM_ERROR("failed to allocate connector\n"); + return NULL; + } + + connector = &sti_connector->drm_connector; + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + connector_type = DRM_MODE_CONNECTOR_HDMIA; + connector->polled = DRM_CONNECTOR_POLL_HPD; + break; + case STI_TVOUT_CONNECTOR_HDA: + connector_type = DRM_MODE_CONNECTOR_Component; + break; + case STI_TVOUT_CONNECTOR_DVO: + connector_type = DRM_MODE_CONNECTOR_LVDS; + break; + case STI_TVOUT_CONNECTOR_DENC: + connector_type = DRM_MODE_CONNECTOR_Composite; + break; + default: + connector_type = DRM_MODE_CONNECTOR_Unknown; + break; + } + + drm_connector_init(dev, connector, &sti_drm_connector_funcs, + connector_type); + drm_connector_helper_add(connector, &sti_drm_connector_helper_funcs); + + err = drm_sysfs_connector_add(connector); + if (err) + goto err_connector; + + sti_connector->tvout = tvout; + sti_connector->encoder = encoder; + sti_connector->type = type; + + err = drm_mode_connector_attach_encoder(connector, encoder); + if (err) { + DRM_ERROR("Failed to attach a connector to a encoder\n"); + goto err_sysfs; + } + + DRM_DEBUG_DRIVER("Connector has been created\n"); + + return connector; + +err_sysfs: + drm_sysfs_connector_remove(connector); +err_connector: + drm_connector_cleanup(connector); + kfree(sti_connector); + return NULL; +} diff --git a/drivers/gpu/drm/sti/sti_drm_connector.h b/drivers/gpu/drm/sti/sti_drm_connector.h new file mode 100644 index 0000000..068c674 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_connector.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_DRM_CONNECTOR_H_ +#define _STI_DRM_CONNECTOR_H_ + +#include "sti_tvout.h" + +struct drm_connector *sti_drm_connector_create(struct drm_device *dev, + struct sti_tvout *tvout, struct drm_encoder *encoder, + enum sti_tvout_connector_type type); + +#endif diff --git a/drivers/gpu/drm/sti/sti_drm_crtc.c b/drivers/gpu/drm/sti/sti_drm_crtc.c new file mode 100644 index 0000000..5c06d70 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_crtc.c @@ -0,0 +1,440 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <linux/clk.h> + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> + +#include "sti_drm_drv.h" +#include "sti_drm_crtc.h" +#include "sti_compositor.h" +#include "sti_vtg_utils.h" + +static void sti_drm_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + DRM_DEBUG_KMS("\n"); +} + +static void sti_drm_crtc_prepare(struct drm_crtc *crtc) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + struct device *dev = mixer->dev; + struct sti_compositor *compo = dev_get_drvdata(dev); + + compo->enable = true; + + /* Prepare and enable the compo IP clock */ + if (mixer->id == STI_MIXER_MAIN) { + if (clk_prepare_enable(compo->clk_compo_main)) + DRM_INFO("Failed to prepare/enable compo_main clk\n"); + } else { + if (clk_prepare_enable(compo->clk_compo_aux)) + DRM_INFO("Failed to prepare/enable compo_aux clk\n"); + } +} + +static void sti_drm_crtc_commit(struct drm_crtc *crtc) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + struct device *dev = mixer->dev; + struct sti_compositor *compo = dev_get_drvdata(dev); + struct sti_layer *layer; + + dev_dbg(dev, "%s\n", __func__); + if ((!mixer || !compo)) { + DRM_ERROR("Can not find mixer or compositor)\n"); + return; + } + + /* Find GDP0 which is reserved to the CRTC FB */ + layer = sti_layer_find_layer(compo->layer, STI_GDP_0); + if (layer) + sti_layer_commit(layer); + else + DRM_ERROR("Can not find CRTC dedicated plane (GDP0)\n"); + + /* Enable layer on mixer */ + if (sti_mixer_set_layer_status(mixer, layer, true)) + DRM_ERROR("Can not enable layer at mixer\n"); +} + +static bool sti_drm_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + /* accept the provided drm_display_mode, do not fix it up */ + dev_dbg(crtc->dev->dev, "%s\n", __func__); + return true; +} + +static int +sti_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, int x, int y, + struct drm_framebuffer *old_fb) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + struct device *dev = mixer->dev; + struct sti_compositor *compo = dev_get_drvdata(dev); + struct sti_layer *layer; + struct clk *clk; + int rate = mode->clock * 1000; + int res; + unsigned int w, h; + + DRM_DEBUG_KMS("CRTC:%d (%s) fb:%d mode:%d (%s)\n", + crtc->base.id, sti_mixer_to_str(mixer), + crtc->fb->base.id, mode->base.id, mode->name); + + DRM_DEBUG_KMS("%d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", + mode->vrefresh, mode->clock, + mode->hdisplay, + mode->hsync_start, mode->hsync_end, + mode->htotal, + mode->vdisplay, + mode->vsync_start, mode->vsync_end, + mode->vtotal, mode->type, mode->flags); + + /* Set rate and prepare/enable pixel clock */ + if (mixer->id == STI_MIXER_MAIN) + clk = compo->clk_pix_main; + else + clk = compo->clk_pix_aux; + + res = clk_set_rate(clk, rate); + if (res < 0) { + DRM_ERROR("Cannot set rate (%dHz) for pix clk\n", rate); + return 1; + } + if (clk_prepare_enable(clk)) { + DRM_ERROR("Failed to prepare/enable pix clk\n"); + return 1; + } + + sti_vtg_setconfig(mixer->id == STI_MIXER_MAIN ? VTG_MAIN : VTG_AUX, + &crtc->mode); + + /* GDP0 is reserved to the CRTC FB */ + layer = sti_layer_find_layer(compo->layer, STI_GDP_0); + if (!layer) { + DRM_ERROR("Can not find GDP0)\n"); + return 1; + } + + /* copy the mode data adjusted by mode_fixup() into crtc->mode + * so that hardware can be set to proper mode */ + memcpy(&crtc->mode, adjusted_mode, sizeof(*adjusted_mode)); + + res = sti_mixer_set_layer_depth(mixer, layer); + if (res) { + DRM_ERROR("Can not set layer depth\n"); + return 1; + } + res = sti_mixer_active_video_area(mixer, &crtc->mode); + if (res) { + DRM_ERROR("Can not set active video area\n"); + return 1; + } + + if ((mode->hdisplay != crtc->fb->width) || + (mode->vdisplay != crtc->fb->height)) + DRM_DEBUG_KMS("WARNING: fb and display mode sizes differ\n"); + + w = crtc->fb->width - x; + h = crtc->fb->height - y; + + if ((w <= 0) || (h <= 0)) { + DRM_ERROR("Coordinates outside FB\n"); + return -EINVAL; + } + + return sti_layer_prepare(layer, crtc->fb, &crtc->mode, mixer->id, + 0, 0, w, h, x, y, w, h); +} + +static int sti_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + struct device *dev = mixer->dev; + struct sti_compositor *compo = dev_get_drvdata(dev); + struct sti_layer *layer; + unsigned int w, h; + int ret = 0; + + DRM_DEBUG_KMS("CRTC:%d (%s) fb:%d (%d,%d)\n", + crtc->base.id, sti_mixer_to_str(mixer), + crtc->fb->base.id, x, y); + + /* GDP0 is reserved to the CRTC FB */ + layer = sti_layer_find_layer(compo->layer, STI_GDP_0); + if (!layer) { + DRM_ERROR("Can not find GDP0)\n"); + ret = -1; + goto out; + } + + w = crtc->fb->width - crtc->x; + h = crtc->fb->height - crtc->y; + + if ((w <= 0) || (h <= 0)) { + DRM_ERROR("Coordinates outside FB\n"); + ret = -EINVAL; + goto out; + } + + ret = sti_layer_prepare(layer, crtc->fb, &crtc->mode, mixer->id, + 0, 0, w, h, + crtc->x, crtc->y, w, h); + if (ret) { + DRM_ERROR("Can not prepare layer\n"); + goto out; + } + + sti_drm_crtc_commit(crtc); +out: + return ret; +} + +static void sti_drm_crtc_load_lut(struct drm_crtc *crtc) +{ + dev_dbg(crtc->dev->dev, "%s\n", __func__); +} + +static void sti_drm_crtc_disable(struct drm_crtc *crtc) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + struct device *dev = mixer->dev; + struct sti_compositor *compo = dev_get_drvdata(dev); + struct sti_layer *layer; + + if (!compo->enable) + return; + + DRM_DEBUG_KMS("CRTC:%d (%s)\n", crtc->base.id, sti_mixer_to_str(mixer)); + + /* Disable Background */ + sti_mixer_set_background_status(mixer, false); + + /* Disable GDP0 */ + layer = sti_layer_find_layer(compo->layer, STI_GDP_0); + if (!layer) { + DRM_ERROR("Cannot find GDP0\n"); + return; + } + + /* Disable layer at mixer level */ + if (sti_mixer_set_layer_status(mixer, layer, false)) + DRM_ERROR("Can not disable %s layer at mixer\n", + sti_layer_to_str(layer)); + + /* Wait a while to be sure that a Vsync event is received */ + msleep(WAIT_NEXT_VSYNC_MS); + + /* Then disable layer itself */ + sti_layer_disable(layer); + + drm_vblank_off(crtc->dev, mixer->id); + + /* Disable pixel clock and compo IP clocks */ + if (mixer->id == STI_MIXER_MAIN) { + clk_disable_unprepare(compo->clk_pix_main); + clk_disable_unprepare(compo->clk_compo_main); + } else { + clk_disable_unprepare(compo->clk_pix_aux); + clk_disable_unprepare(compo->clk_compo_aux); + } + + compo->enable = false; +} + +static struct drm_crtc_helper_funcs sti_crtc_helper_funcs = { + .dpms = sti_drm_crtc_dpms, + .prepare = sti_drm_crtc_prepare, + .commit = sti_drm_crtc_commit, + .mode_fixup = sti_drm_crtc_mode_fixup, + .mode_set = sti_drm_crtc_mode_set, + .mode_set_base = sti_drm_crtc_mode_set_base, + .load_lut = sti_drm_crtc_load_lut, + .disable = sti_drm_crtc_disable, +}; + +static int sti_drm_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct drm_device *drm_dev = crtc->dev; + struct sti_drm_private *dev_priv = drm_dev->dev_private; + struct drm_framebuffer *old_fb; + struct sti_mixer *mixer = to_sti_mixer(crtc); + unsigned long flags; + int ret = 0; + + DRM_DEBUG_KMS("fb %d --> fb %d\n", crtc->fb->base.id, fb->base.id); + + mutex_lock(&drm_dev->struct_mutex); + + old_fb = crtc->fb; + crtc->fb = fb; + ret = sti_drm_crtc_mode_set_base(crtc, crtc->x, crtc->y, old_fb); + if (ret) { + DRM_ERROR("failed\n"); + crtc->fb = old_fb; + goto out; + } + + if (event) { + event->pipe = mixer->id; + + ret = drm_vblank_get(drm_dev, event->pipe); + if (ret) { + DRM_ERROR("Cannot get vblank\n"); + goto out; + } + + spin_lock_irqsave(&drm_dev->event_lock, flags); + list_add_tail(&event->base.link, &dev_priv->pageflip_evt_list); + spin_unlock_irqrestore(&drm_dev->event_lock, flags); + } +out: + mutex_unlock(&drm_dev->struct_mutex); + return ret; +} + +static void sti_drm_crtc_destroy(struct drm_crtc *crtc) +{ + DRM_DEBUG_KMS("\n"); + + drm_crtc_cleanup(crtc); +} + +static int sti_drm_crtc_set_property(struct drm_crtc *crtc, + struct drm_property *property, + uint64_t val) +{ + DRM_DEBUG_KMS("\n"); + + return 0; +} + +int sti_drm_crtc_vblank_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct sti_compositor *compo = container_of(nb, + struct sti_compositor, + vtg_vblank_nb); + struct drm_device *drm_dev; + int *crtc = data; + unsigned long flags; + struct drm_pending_vblank_event *e, *t; + struct sti_drm_private *priv; + + drm_dev = compo->mixer[*crtc]->drm_crtc.dev; + priv = drm_dev->dev_private; + + dev_dbg(drm_dev->dev, "%s\n", __func__); + + if ((event != VTG_TOP_FIELD_EVENT) && + (event != VTG_BOTTOM_FIELD_EVENT)) { + DRM_ERROR("unknown event: %lu\n", event); + return -EINVAL; + } + + drm_handle_vblank(drm_dev, *crtc); + + spin_lock_irqsave(&drm_dev->event_lock, flags); + list_for_each_entry_safe(e, t, &priv->pageflip_evt_list, base.link) { + if (*crtc != e->pipe) + continue; + + list_del(&e->base.link); + drm_send_vblank_event(drm_dev, -1, e); + drm_vblank_put(drm_dev, *crtc); + } + spin_unlock_irqrestore(&drm_dev->event_lock, flags); + + return 0; +} + +int sti_drm_crtc_enable_vblank(struct drm_device *dev, int crtc) +{ + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb; + DRM_DEBUG_DRIVER("\n"); + + if (sti_vtg_register_client(crtc, vtg_vblank_nb)) { + DRM_ERROR("Cannot register VTG notifier\n"); + return 1; + } + + return 0; +} + +void sti_drm_crtc_disable_vblank(struct drm_device *dev, int crtc) +{ + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb; + unsigned long flags; + struct drm_pending_vblank_event *e, *t; + struct sti_drm_private *priv = dev->dev_private; + DRM_DEBUG_DRIVER("\n"); + + if (sti_vtg_unregister_client(crtc, vtg_vblank_nb)) + DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); + + /* free the resources of the pending requests */ + spin_lock_irqsave(&dev->event_lock, flags); + list_for_each_entry_safe(e, t, &priv->pageflip_evt_list, base.link) { + if (crtc != e->pipe) + continue; + list_del(&e->base.link); + drm_vblank_put(dev, crtc); + } + spin_unlock_irqrestore(&dev->event_lock, flags); + +} + +static struct drm_crtc_funcs sti_crtc_funcs = { + .set_config = drm_crtc_helper_set_config, + .page_flip = sti_drm_crtc_page_flip, + .destroy = sti_drm_crtc_destroy, + .set_property = sti_drm_crtc_set_property, +}; + +bool sti_drm_crtc_is_main(struct drm_crtc *crtc) +{ + struct sti_mixer *mixer = to_sti_mixer(crtc); + + if (mixer->id == STI_MIXER_MAIN) + return true; + + return false; +} + +int sti_drm_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer) +{ + struct drm_crtc *crtc = &mixer->drm_crtc; + int res; + + dev_dbg(drm_dev->dev, "%s\n", __func__); + res = drm_crtc_init(drm_dev, crtc, &sti_crtc_funcs); + if (res) { + DRM_ERROR("Can not initialze CRTC\n"); + return 1; + } + + drm_crtc_helper_add(crtc, &sti_crtc_helper_funcs); + + DRM_DEBUG_DRIVER("drm CRTC:%d mapped to %s\n", + crtc->base.id, sti_mixer_to_str(mixer)); + + return 0; +} diff --git a/drivers/gpu/drm/sti/sti_drm_crtc.h b/drivers/gpu/drm/sti/sti_drm_crtc.h new file mode 100644 index 0000000..9d31e41 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_crtc.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_DRM_CRTC_H_ +#define _STI_DRM_CRTC_H_ + +#include <drm/drmP.h> + +#include "sti_mixer.h" + +int sti_drm_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer); +int sti_drm_crtc_enable_vblank(struct drm_device *dev, int crtc); +void sti_drm_crtc_disable_vblank(struct drm_device *dev, int crtc); +int sti_drm_crtc_vblank_cb(struct notifier_block *nb, + unsigned long event, void *data); +bool sti_drm_crtc_is_main(struct drm_crtc *drm_crtc); + +#endif diff --git a/drivers/gpu/drm/sti/sti_drm_drv.c b/drivers/gpu/drm/sti/sti_drm_drv.c new file mode 100644 index 0000000..16ac771 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_drv.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <drm/drmP.h> + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_fb_cma_helper.h> + +#include "sti_drm_drv.h" +#include "sti_drm_crtc.h" +#include "sti_drm_plane.h" +#include "sti_compositor.h" +#include "sti_gdp.h" +#include "sti_drm_encoder.h" +#include "sti_drm_connector.h" +#include "sti_tvout.h" + +#define DRIVER_NAME "sti" +#define DRIVER_DESC "STMicroelectronics SoC DRM" +#define DRIVER_DATE "20130905" +#define DRIVER_MAJOR 1 +#define DRIVER_MINOR 0 + +/* platform device pointer for sti drm device. */ +static struct platform_device *sti_drm_pdev; +#ifdef CONFIG_DRM_STI_FBDEV +#define FBDEV_CREATE_DELAY 2000 +struct drm_device *sti_drm_device; + +static void stid_fbdev_create(struct work_struct *dummy) +{ + if (!sti_drm_device) + return; + + drm_fbdev_cma_init(sti_drm_device, 32, + sti_drm_device->mode_config.num_crtc, + sti_drm_device->mode_config.num_connector); +} + +static DECLARE_DELAYED_WORK(sti_fbdev_work, stid_fbdev_create); +#endif + +static int sti_drm_tvout_init(struct device *dev, void *data) +{ + struct sti_tvout *tvout = dev_get_drvdata(dev); + struct drm_device *drm_dev = data; + struct drm_encoder *encoder; + int i; + struct sti_drm_private *dev_priv = drm_dev->dev_private; + + dev_priv->tvout = tvout; + + tvout->drm_dev = drm_dev; + + /* Register all encoder/connector couples supported by tvout */ + for (i = 0; i < STI_TVOUT_CONNECTOR_MAX; i++) { + if (tvout->connector_create[i] != NULL) { + encoder = sti_drm_encoder_create(drm_dev, tvout, + 1 << 0, i); + sti_drm_connector_create(drm_dev, tvout, encoder, i); + } + } + + return 0; +} + +static int sti_drm_compositor_init(struct device *dev, void *data) +{ + struct sti_compositor *compo = dev_get_drvdata(dev); + struct drm_device *drm_dev = data; + int i, crtc = 0, plane = 0; + struct sti_drm_private *dev_priv = drm_dev->dev_private; + + dev_dbg(dev, "%s\n", __func__); + + dev_priv->compo = compo; + INIT_LIST_HEAD(&dev_priv->pageflip_evt_list); + + for (i = 0; i < compo->nb_mixers; i++) { + if (compo->mixer[i]) { + sti_drm_crtc_init(drm_dev, compo->mixer[i]); + crtc++; + } + } + if (crtc == 0) { + DRM_ERROR("No CRTC available\n"); + return 1; + } + + drm_vblank_init(drm_dev, crtc); + /* Allow usage of vblank without having to call drm_irq_install */ + drm_dev->irq_enabled = 1; + + for (i = 0; i < compo->nb_layers; i++) { + if (compo->layer[i]) { + /* Create planes for GDP. + * except GDP0 as it is reserved for CRTC FB */ + enum sti_layer_desc desc = compo->layer[i]->desc; + enum sti_layer_type type = desc & STI_LAYER_TYPE_MASK; + + if ((type == STI_GDP) && (desc != STI_GDP_0)) { + sti_drm_plane_init(drm_dev, compo->layer[i], + (1 << crtc) - 1); + plane++; + } + } + } + + DRM_DEBUG_DRIVER("Initialized %d DRM CRTC(s) and %d DRM plane(s)\n", + crtc, plane); + DRM_DEBUG_DRIVER("DRM plane(s) for VID/VDP not created yet\n"); + + return 0; +} + +static struct drm_mode_config_funcs sti_drm_mode_config_funcs = { + .fb_create = drm_fb_cma_create, +}; + +#ifdef CONFIG_DEBUG_FS +static struct drm_info_list sti_drm_dbg_list[] = { + {"gdp", sti_gdp_dbg_show, 0}, + {"node", sti_gdp_node_dbg_show, 0}, + {"mixer", sti_mixer_dbg_show, 0}, + {"hdmi", sti_tvout_hdmi_dbg_show, 0, NULL}, + {"hda", sti_tvout_hda_dbg_show, 0, NULL}, +}; + +static int sti_drm_fps_get(void *data, u64 *val) +{ + struct drm_device *dev = data; + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + int i; + + *val = 0; + for (i = 0; i < compo->nb_layers; i++) + *val |= (compo->layer[i]->fps_info.output) << i; + + return 0; +} + +static int sti_drm_fps_set(void *data, u64 val) +{ + struct drm_device *dev = data; + struct sti_drm_private *dev_priv = dev->dev_private; + struct sti_compositor *compo = dev_priv->compo; + int i; + + for (i = 0; i < compo->nb_layers; i++) + compo->layer[i]->fps_info.output = (val >> i) & 1; + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(sti_drm_fps_fops, + sti_drm_fps_get, sti_drm_fps_set, "%llu\n"); + +static int sti_drm_debugfs_create(struct dentry *root, struct drm_minor *minor, + const char *name, + const struct file_operations *fops) +{ + struct drm_device *dev = minor->dev; + struct drm_info_node *node; + struct dentry *ent; + + ent = debugfs_create_file(name, S_IRUGO | S_IWUSR, root, dev, fops); + if (IS_ERR(ent)) + return PTR_ERR(ent); + + node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); + if (node == NULL) { + debugfs_remove(ent); + return -ENOMEM; + } + + node->minor = minor; + node->dent = ent; + node->info_ent = (void *)fops; + + mutex_lock(&minor->debugfs_lock); + list_add(&node->list, &minor->debugfs_list); + mutex_unlock(&minor->debugfs_lock); + + return 0; +} + +int sti_drm_dbg_init(struct drm_minor *minor) +{ + int ret; + + ret = sti_drm_debugfs_create(minor->debugfs_root, minor, "fps_show", + &sti_drm_fps_fops); + if (ret) + goto err; + + ret = drm_debugfs_create_files(sti_drm_dbg_list, + ARRAY_SIZE(sti_drm_dbg_list), + minor->debugfs_root, minor); + if (ret) + goto err; + + DRM_INFO("%s debugfs installed\n", DRIVER_NAME); + + return ret; +err: + DRM_ERROR("Cannot install debugfs\n"); + return ret; +} + +void sti_drm_dbg_cleanup(struct drm_minor *minor) +{ + drm_debugfs_remove_files(sti_drm_dbg_list, + ARRAY_SIZE(sti_drm_dbg_list), minor); + + drm_debugfs_remove_files((struct drm_info_list *)&sti_drm_fps_fops, + 1, minor); +} +#endif + +static void sti_drm_mode_config_init(struct drm_device *dev) +{ + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + + /* + * set max width and height as default value. + * this value would be used to check framebuffer size limitation + * at drm_mode_addfb(). + */ + dev->mode_config.max_width = STI_MAX_FB_HEIGHT; + dev->mode_config.max_height = STI_MAX_FB_WIDTH; + + dev->mode_config.funcs = &sti_drm_mode_config_funcs; +} + +static int sti_drm_load(struct drm_device *dev, unsigned long flags) +{ + struct sti_drm_private *private; + struct device_driver *drv; + int err; + + DRM_INFO("%s drm_device: %p\n", __func__, dev); + + private = kzalloc(sizeof(struct sti_drm_private), GFP_KERNEL); + if (!private) { + DRM_ERROR("Failed to allocate private\n"); + return -ENOMEM; + } + dev->dev_private = (void *)private; + + drm_mode_config_init(dev); + drm_kms_helper_poll_init(dev); + + sti_drm_mode_config_init(dev); + + /* look for compositors HW */ + drv = driver_find("sti-compositor", &platform_bus_type); + if (!drv) { + DRM_ERROR("No compositor found\n"); + return -ENOMEM; + } + err = driver_for_each_device(drv, NULL, dev, sti_drm_compositor_init); + if (err) + DRM_ERROR("Failed to initialize CRTC\n"); + + /* look for TVOUT driver */ + drv = driver_find("sti-tvout", &platform_bus_type); + if (!drv) { + DRM_ERROR("No tvout found\n"); + return -ENOMEM; + } + err = driver_for_each_device(drv, NULL, dev, sti_drm_tvout_init); + if (err) + DRM_ERROR("Failed to initialize TVOUT\n"); + + drm_helper_disable_unused_functions(dev); +#ifdef CONFIG_DRM_STI_FBDEV + sti_drm_device = dev; + + schedule_delayed_work(&sti_fbdev_work, + msecs_to_jiffies(FBDEV_CREATE_DELAY)); +#endif + return err; +} + +static const struct file_operations sti_drm_driver_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .mmap = drm_gem_cma_mmap, + .poll = drm_poll, + .read = drm_read, + .unlocked_ioctl = drm_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .release = drm_release, +}; + +static struct dma_buf *sti_drm_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *obj, + int flags) +{ + /* we want to be able to write in mmapped buffer */ + flags |= O_RDWR; + return drm_gem_prime_export(dev, obj, flags); +} + +static struct drm_driver sti_drm_driver = { + .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET | + DRIVER_GEM | DRIVER_PRIME, + .load = sti_drm_load, + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .dumb_create = drm_gem_cma_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + .fops = &sti_drm_driver_fops, + + .get_vblank_counter = drm_vblank_count, + .enable_vblank = sti_drm_crtc_enable_vblank, + .disable_vblank = sti_drm_crtc_disable_vblank, + + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_export = sti_drm_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, + +#ifdef CONFIG_DEBUG_FS + .debugfs_init = sti_drm_dbg_init, + .debugfs_cleanup = sti_drm_dbg_cleanup, +#endif + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, +}; + +static int sti_drm_platform_probe(struct platform_device *pdev) +{ + DRM_INFO("%s\n", __func__); + + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + + return drm_platform_init(&sti_drm_driver, pdev); +} + +static int sti_drm_platform_remove(struct platform_device *pdev) +{ + DRM_INFO("%s\n", __func__); + + drm_put_dev(platform_get_drvdata(pdev)); + + return 0; +} + +static struct platform_driver sti_drm_platform_driver = { + .probe = sti_drm_platform_probe, + .remove = sti_drm_platform_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRIVER_NAME, + }, +}; + +static int __init sti_drm_init(void) +{ + int ret; + + DRM_INFO("%s\n", __func__); +#ifdef CONFIG_VTAC_STI + ret = platform_driver_register(&sti_vtac_tx_driver); + if (ret < 0) + goto out_vtac_tx; + ret = platform_driver_register(&sti_vtac_rx_driver); + if (ret < 0) + goto out_vtac_rx; +#endif +#ifdef CONFIG_VTG_STI + ret = platform_driver_register(&sti_vtg_driver); + if (ret < 0) + goto out_vtg; +#endif + ret = platform_driver_register(&sti_compositor_driver); + if (ret < 0) + goto out_compo; + + ret = platform_driver_register(&sti_tvout_driver); + if (ret < 0) + goto out_tvout; + + ret = platform_driver_register(&sti_hdmi_driver); + if (ret < 0) + goto out_hdmi; + + ret = platform_driver_register(&sti_hda_driver); + if (ret < 0) + goto out_hda; + + ret = platform_driver_register(&sti_drm_platform_driver); + if (ret < 0) + goto out_drm; + + sti_drm_pdev = + platform_device_register_simple(DRIVER_NAME, -1, NULL, 0); + if (IS_ERR(sti_drm_pdev)) { + ret = PTR_ERR(sti_drm_pdev); + goto out_drm_device; + } + + return 0; + +out_drm_device: + platform_driver_unregister(&sti_drm_platform_driver); +out_drm: + platform_driver_unregister(&sti_hda_driver); +out_hda: + platform_driver_unregister(&sti_hdmi_driver); +out_hdmi: + platform_driver_unregister(&sti_tvout_driver); +out_tvout: + DRM_DEBUG_DRIVER("Can't register STI DRM platform driver"); + platform_driver_unregister(&sti_compositor_driver); +out_compo: +#ifdef CONFIG_VTG_STI + platform_driver_unregister(&sti_vtg_driver); +out_vtg: +#endif +#ifdef CONFIG_VTAC_STI + platform_driver_unregister(&sti_vtac_rx_driver); +out_vtac_rx: + platform_driver_unregister(&sti_vtac_tx_driver); +out_vtac_tx: +#endif + return ret; +} + +static void __exit sti_drm_exit(void) +{ + DRM_DEBUG_DRIVER("\n"); + + platform_device_unregister(sti_drm_pdev); + + platform_driver_unregister(&sti_drm_platform_driver); + platform_driver_unregister(&sti_compositor_driver); +} + +module_init(sti_drm_init); +module_exit(sti_drm_exit); + +MODULE_AUTHOR("Benjamin Gaignard benjamin.gaignard@st.com"); +MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/sti/sti_drm_encoder.c b/drivers/gpu/drm/sti/sti_drm_encoder.c new file mode 100644 index 0000000..96194cf --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_encoder.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> + +#include "sti_drm_crtc.h" +#include "sti_drm_encoder.h" +#include "sti_tvout.h" + +#define to_sti_encoder(x) container_of(x, struct sti_encoder, drm_encoder) + +#define ENCODER_MAIN_CRTC_MASK (1 << 0) + +/* + * sti specific encoder structure. + * + * @drm_encoder: encoder object. + * @tvout: pointer on tvout driver. + * @type: tvout connector type. + */ +struct sti_encoder { + struct drm_encoder drm_encoder; + struct sti_tvout *tvout; + enum sti_tvout_connector_type type; +}; + +static void sti_drm_encoder_dpms(struct drm_encoder *encoder, int mode) +{ +} + +static bool sti_drm_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void sti_drm_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct sti_encoder *sti_encoder = to_sti_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct drm_connector *connector; + + dev_dbg(dev->dev, "%s\n", __func__); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + sti_tvout_set_mode(sti_encoder->tvout, mode, + sti_encoder->type); + break; + } + } +} + +static void sti_drm_encoder_prepare(struct drm_encoder *encoder) +{ + struct sti_encoder *sti_encoder = to_sti_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct drm_connector *connector; + + dev_dbg(dev->dev, "%s\n", __func__); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + sti_tvout_prepare(sti_encoder->tvout, + sti_encoder->type); + break; + } + } +} + +static void sti_drm_encoder_commit(struct drm_encoder *encoder) +{ + struct sti_encoder *sti_encoder = to_sti_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct drm_connector *connector; + + dev_dbg(dev->dev, "%s\n", __func__); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + if (connector->encoder == encoder) { + sti_tvout_commit(sti_encoder->tvout, + sti_encoder->type, + sti_drm_crtc_is_main(encoder->crtc)); + break; + } + } +} + +static void sti_drm_encoder_disable(struct drm_encoder *encoder) +{ + struct sti_encoder *sti_encoder = to_sti_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct drm_connector *connector; + struct drm_connector_helper_funcs *connector_funcs; + + dev_dbg(dev->dev, "%s\n", __func__); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + connector_funcs = connector->helper_private; + if (connector_funcs->best_encoder(connector) == encoder) { + sti_tvout_disable(sti_encoder->tvout, + sti_encoder->type); + break; + } + } +} + +static const struct drm_encoder_helper_funcs sti_drm_encoder_helper_funcs = { + .dpms = sti_drm_encoder_dpms, + .mode_fixup = sti_drm_encoder_mode_fixup, + .mode_set = sti_drm_encoder_mode_set, + .prepare = sti_drm_encoder_prepare, + .commit = sti_drm_encoder_commit, + .disable = sti_drm_encoder_disable, +}; + +static void sti_drm_encoder_destroy(struct drm_encoder *encoder) +{ + struct sti_encoder *sti_encoder = to_sti_encoder(encoder); + struct drm_device *dev = encoder->dev; + + dev_dbg(dev->dev, "%s\n", __func__); + + drm_encoder_cleanup(encoder); + kfree(sti_encoder); +} + +static const struct drm_encoder_funcs sti_drm_encoder_funcs = { + .destroy = sti_drm_encoder_destroy, +}; + +struct drm_encoder *sti_drm_encoder_create(struct drm_device *dev, + struct sti_tvout *tvout, + unsigned int possible_crtcs, + enum sti_tvout_connector_type type) +{ + struct sti_encoder *sti_encoder; + struct drm_encoder *encoder; + int encoder_type; + + dev_dbg(dev->dev, "%s\n", __func__); + + if (!dev || !tvout || !possible_crtcs) + return NULL; + + sti_encoder = kzalloc(sizeof(*sti_encoder), GFP_KERNEL); + if (!sti_encoder) { + DRM_ERROR("failed to allocate encoder\n"); + return NULL; + } + + sti_encoder->tvout = tvout; + sti_encoder->type = type; + encoder = &sti_encoder->drm_encoder; + encoder->possible_crtcs = possible_crtcs; + + /* HDMI connector only supports main crtc */ + if (type == STI_TVOUT_CONNECTOR_HDMI) + encoder->possible_crtcs &= ENCODER_MAIN_CRTC_MASK; + + /* HD Analog connector may support aux CRTC. Not implemented yet */ + if (type == STI_TVOUT_CONNECTOR_HDA) + encoder->possible_crtcs &= ENCODER_MAIN_CRTC_MASK; + + DRM_DEBUG_DRIVER("possible_crtcs = 0x%x\n", encoder->possible_crtcs); + + switch (type) { + case STI_TVOUT_CONNECTOR_HDMI: + encoder_type = DRM_MODE_ENCODER_TMDS; + encoder->possible_clones = 1 << STI_TVOUT_CONNECTOR_HDA; + break; + case STI_TVOUT_CONNECTOR_HDA: + encoder_type = DRM_MODE_ENCODER_DAC; + encoder->possible_clones = 1 << STI_TVOUT_CONNECTOR_HDMI; + break; + case STI_TVOUT_CONNECTOR_DENC: + encoder_type = DRM_MODE_ENCODER_DAC; + break; + case STI_TVOUT_CONNECTOR_DVO: + encoder_type = DRM_MODE_ENCODER_LVDS; + break; + default: + encoder_type = DRM_MODE_ENCODER_NONE; + break; + } + + drm_encoder_init(dev, encoder, &sti_drm_encoder_funcs, encoder_type); + + drm_encoder_helper_add(encoder, &sti_drm_encoder_helper_funcs); + + DRM_DEBUG_DRIVER("encoder has been created\n"); + + return encoder; +} diff --git a/drivers/gpu/drm/sti/sti_drm_encoder.h b/drivers/gpu/drm/sti/sti_drm_encoder.h new file mode 100644 index 0000000..35d9945 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_encoder.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_DRM_ENCODER_H_ +#define _STI_DRM_ENCODER_H_ + +#include "sti_tvout.h" + +struct drm_encoder *sti_drm_encoder_create(struct drm_device *dev, + struct sti_tvout *tvout, unsigned int possible_crtcs, + enum sti_tvout_connector_type type); + +#endif diff --git a/drivers/gpu/drm/sti/sti_drm_plane.c b/drivers/gpu/drm/sti/sti_drm_plane.c new file mode 100644 index 0000000..e34c33a --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_plane.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Authors: Benjamin Gaignard benjamin.gaignard@st.com + * Fabien Dessenne fabien.dessenne@st.com + * for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ +#include "sti_drm_drv.h" +#include "sti_drm_plane.h" +#include "sti_compositor.h" +#include "sti_vtg_utils.h" + +enum sti_layer_desc sti_layer_default_zorder[] = { + STI_GDP_0, + STI_VID_0, + STI_GDP_1, + STI_VID_1, + STI_GDP_2, + STI_GDP_3, +}; + +/* (Background) < GDP0 < VID0 < GDP1 < VID1 < GDP2 < GDP3 < (ForeGround) */ + +static int +sti_drm_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) +{ + struct sti_layer *layer = to_sti_layer(plane); + struct sti_mixer *mixer = to_sti_mixer(crtc); + int res; + + DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s) drm fb:%d\n", + crtc->base.id, sti_mixer_to_str(mixer), + plane->base.id, sti_layer_to_str(layer), fb->base.id); + DRM_DEBUG_KMS("(%dx%d)@(%d,%d)\n", crtc_w, crtc_h, crtc_x, crtc_y); + + res = sti_mixer_set_layer_depth(mixer, layer); + if (res) { + DRM_ERROR("Can not set layer depth\n"); + return res; + } + + /* src_x are in 16.16 format. */ + res = sti_layer_prepare(layer, fb, &crtc->mode, mixer->id, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x >> 16, src_y >> 16, + src_w >> 16, src_h >> 16); + if (res) { + DRM_ERROR("Layer prepare failed\n"); + return res; + } + + res = sti_layer_commit(layer); + if (res) { + DRM_ERROR("Layer commit failed\n"); + return res; + } + + res = sti_mixer_set_layer_status(mixer, layer, true); + if (res) { + DRM_ERROR("Can not enable layer at mixer\n"); + return res; + } + + return 0; +} + +static int sti_drm_disable_plane(struct drm_plane *plane) +{ + struct sti_layer *layer; + struct sti_mixer *mixer; + int lay_res, mix_res; + + if (!plane->crtc) { + DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", plane->base.id); + return 0; + } + layer = to_sti_layer(plane); + mixer = to_sti_mixer(plane->crtc); + + DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", + plane->crtc->base.id, sti_mixer_to_str(mixer), + plane->base.id, sti_layer_to_str(layer)); + + /* Disable layer at mixer level */ + mix_res = sti_mixer_set_layer_status(mixer, layer, false); + if (mix_res) + DRM_ERROR("Can not disable layer at mixer\n"); + + /* Wait a while to be sure that a Vsync event is received */ + msleep(WAIT_NEXT_VSYNC_MS); + + /* Then disable layer itself */ + lay_res = sti_layer_disable(layer); + if (lay_res) + DRM_ERROR("Layer disable failed\n"); + + if (lay_res || mix_res) + return 1; + else + return 0; +} + +static void sti_drm_plane_destroy(struct drm_plane *plane) +{ + DRM_DEBUG_DRIVER("\n"); + + sti_drm_disable_plane(plane); + drm_plane_cleanup(plane); +} + +static int sti_drm_plane_set_property(struct drm_plane *plane, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = plane->dev; + struct sti_drm_private *private = dev->dev_private; + struct sti_layer *layer = to_sti_layer(plane); + + DRM_DEBUG_DRIVER("\n"); + + if (property == private->plane_zorder_property) { + layer->zorder = val; + return 0; + } + + return -EINVAL; +} + +static struct drm_plane_funcs sti_drm_plane_funcs = { + .update_plane = sti_drm_update_plane, + .disable_plane = sti_drm_disable_plane, + .destroy = sti_drm_plane_destroy, + .set_property = sti_drm_plane_set_property, +}; + +static void sti_drm_plane_attach_zorder_property(struct drm_plane *plane, + uint64_t default_val) +{ + struct drm_device *dev = plane->dev; + struct sti_drm_private *private = dev->dev_private; + struct drm_property *prop; + struct sti_layer *layer = to_sti_layer(plane); + + dev_dbg(dev->dev, "%s zorder:%llu\n", __func__, default_val); + + prop = private->plane_zorder_property; + if (!prop) { + prop = drm_property_create_range(dev, 0, "zpos", 0, + GAM_MIXER_NB_DEPTH_LEVEL - 1); + if (!prop) + return; + + private->plane_zorder_property = prop; + } + + drm_object_attach_property(&plane->base, prop, default_val); + layer->zorder = default_val; +} + +struct drm_plane *sti_drm_plane_init(struct drm_device *dev, + struct sti_layer *layer, + unsigned int possible_crtcs) +{ + int err, i; + uint64_t default_zorder = 0; + + dev_dbg(dev->dev, "%s\n", __func__); + + err = drm_plane_init(dev, &layer->plane, possible_crtcs, + &sti_drm_plane_funcs, + sti_layer_get_formats(layer), + sti_layer_get_nb_formats(layer), false); + if (err) { + DRM_ERROR("Failed to initialize plane\n"); + return NULL; + } + + for (i = 0; i < ARRAY_SIZE(sti_layer_default_zorder); i++) + if (sti_layer_default_zorder[i] == layer->desc) + break; + + default_zorder = i; + + sti_drm_plane_attach_zorder_property(&layer->plane, default_zorder); + + DRM_DEBUG_DRIVER("drm plane:%d mapped to %s with zorder:%llu\n", + layer->plane.base.id, + sti_layer_to_str(layer), default_zorder); + + return &layer->plane; +} diff --git a/drivers/gpu/drm/sti/sti_drm_plane.h b/drivers/gpu/drm/sti/sti_drm_plane.h new file mode 100644 index 0000000..d182066 --- /dev/null +++ b/drivers/gpu/drm/sti/sti_drm_plane.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) STMicroelectronics SA 2013 + * Author: Benjamin Gaignard benjamin.gaignard@st.com for STMicroelectronics. + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _STI_DRM_PLANE_H_ +#define _STI_DRM_PLANE_H_ + +#include <drm/drmP.h> +#include "sti_layer.h" + +struct drm_plane *sti_drm_plane_init(struct drm_device *dev, + struct sti_layer *layer, unsigned int possible_crtcs); + +#endif diff --git a/drivers/gpu/drm/sti/sti_vtg_utils.h b/drivers/gpu/drm/sti/sti_vtg_utils.h index 8992a04..fea2852 100644 --- a/drivers/gpu/drm/sti/sti_vtg_utils.h +++ b/drivers/gpu/drm/sti/sti_vtg_utils.h @@ -11,6 +11,8 @@

#include <drm/drmP.h>

+#define WAIT_NEXT_VSYNC_MS 50 /*ms*/ + #define VTG_MAIN 0 #define VTG_AUX 1

From: Vincent Abriou vincent.abriou@st.com

Signed-off-by: Benjamin Gaignard benjamin.gaignard@linaro.org Signed-off-by: Vincent Abriou vincent.abriou@st.com Signed-off-by: Fabien Dessenne fabien.dessenne@st.com --- drivers/gpu/drm/sti/sti_mixer.c | 70 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c index fce72e4..73d5405 100644 --- a/drivers/gpu/drm/sti/sti_mixer.c +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -18,16 +18,16 @@ static const u32 MixerColorSpaceMatIdentity[] = { };

/* regs offset */ -#define GAM_MIXER_MAIN_CTL 0x00 -#define GAM_MIXER_MAIN_BKC 0x04 -#define GAM_MIXER_MAIN_BCO 0x0C -#define GAM_MIXER_MAIN_BCS 0x10 -#define GAM_MIXER_MAIN_AVO 0x28 -#define GAM_MIXER_MAIN_AVS 0x2C -#define GAM_MIXER_MAIN_CRB 0x34 -#define GAM_MIXER_MAIN_ACT 0x38 -#define GAM_MIXER_MAIN_MBP 0x3C -#define GAM_MIXER_MAIN_MX0 0x80 +#define GAM_MIXER_CTL 0x00 +#define GAM_MIXER_BKC 0x04 +#define GAM_MIXER_BCO 0x0C +#define GAM_MIXER_BCS 0x10 +#define GAM_MIXER_AVO 0x28 +#define GAM_MIXER_AVS 0x2C +#define GAM_MIXER_CRB 0x34 +#define GAM_MIXER_ACT 0x38 +#define GAM_MIXER_MBP 0x3C +#define GAM_MIXER_MX0 0x80

/* id for depth of CRB reg */ #define GAM_DEPTH_VID0_ID 1 @@ -82,7 +82,7 @@ static inline void sti_mixer_reg_writemask(struct sti_mixer *mixer, void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable) { sti_mixer_reg_writemask(mixer, - GAM_MIXER_MAIN_CTL, enable, GAM_CTL_BACK_MASK); + GAM_MIXER_CTL, enable, GAM_CTL_BACK_MASK); }

static void sti_mixer_set_background_color(struct sti_mixer *mixer, @@ -90,7 +90,7 @@ static void sti_mixer_set_background_color(struct sti_mixer *mixer, { u32 val = (red << 16) | (green << 8) | blue;

- sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BKC, val); + sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val); }

static void sti_mixer_set_background_area(struct sti_mixer *mixer, @@ -103,8 +103,8 @@ static void sti_mixer_set_background_area(struct sti_mixer *mixer, xdo = sti_vtg_get_pixel_number(*mode, 0); xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);

- sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BCO, ydo << 16 | xdo); - sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_BCS, yds << 16 | xds); + sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo); + sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds); }

int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer) @@ -143,12 +143,12 @@ int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)

DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer), sti_layer_to_str(layer), depth); - dev_dbg(mixer->dev, "GAM_MIXER_MAIN_CRB val 0x%x mask 0x%x\n", + dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", layer_id, mask); - sti_mixer_reg_writemask(mixer, GAM_MIXER_MAIN_CRB, layer_id, mask); + sti_mixer_reg_writemask(mixer, GAM_MIXER_CRB, layer_id, mask);

- dev_dbg(mixer->dev, "Read GAM_MIXER_MAIN_CRB 0x%x\n", - sti_mixer_reg_read(mixer, GAM_MIXER_MAIN_CRB)); + dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n", + sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); return 0; }

@@ -164,8 +164,8 @@ int sti_mixer_active_video_area(struct sti_mixer *mixer,

DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n", sti_mixer_to_str(mixer), xdo, ydo, xds, yds); - sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_AVO, ydo << 16 | xdo); - sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_AVS, yds << 16 | xds); + sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo); + sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);

sti_mixer_set_background_color(mixer, 0xFF, 0, 0);

@@ -210,7 +210,7 @@ int sti_mixer_set_layer_status(struct sti_mixer *mixer, return -1; } val = status ? mask : 0; - sti_mixer_reg_writemask(mixer, GAM_MIXER_MAIN_CTL, val, mask); + sti_mixer_reg_writemask(mixer, GAM_MIXER_CTL, val, mask); return 0; }

@@ -219,7 +219,7 @@ void sti_mixer_set_matrix(struct sti_mixer *mixer) int i;

for (i = 0; i < ARRAY_SIZE(MixerColorSpaceMatIdentity); i++) - sti_mixer_reg_write(mixer, GAM_MIXER_MAIN_MX0 + (i * 4), + sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4), MixerColorSpaceMatIdentity[i]); }

@@ -359,23 +359,23 @@ int sti_mixer_dbg_show(struct seq_file *m, void *arg) struct sti_mixer *mixer = compo->mixer[i];

seq_printf(m, "\n%s", sti_mixer_to_str(mixer)); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_CTL); + MIXER_DBG_DUMP(GAM_MIXER_CTL); sti_mixer_dbg_ctl(m, sti_mixer_reg_read(mixer, - GAM_MIXER_MAIN_CTL)); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_BKC); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_BCO); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_BCS); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_AVO); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_AVS); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_CRB); + GAM_MIXER_CTL)); + MIXER_DBG_DUMP(GAM_MIXER_BKC); + MIXER_DBG_DUMP(GAM_MIXER_BCO); + MIXER_DBG_DUMP(GAM_MIXER_BCS); + MIXER_DBG_DUMP(GAM_MIXER_AVO); + MIXER_DBG_DUMP(GAM_MIXER_AVS); + MIXER_DBG_DUMP(GAM_MIXER_CRB); sti_mixer_dbg_crb(m, sti_mixer_reg_read(mixer, - GAM_MIXER_MAIN_CRB)); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_ACT); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_MBP); - MIXER_DBG_DUMP(GAM_MIXER_MAIN_MX0); - sti_mixer_dbg_mxn(m, mixer->regs + GAM_MIXER_MAIN_MX0); + GAM_MIXER_CRB)); + MIXER_DBG_DUMP(GAM_MIXER_ACT); + MIXER_DBG_DUMP(GAM_MIXER_MBP); + MIXER_DBG_DUMP(GAM_MIXER_MX0); + sti_mixer_dbg_mxn(m, mixer->regs + GAM_MIXER_MX0); seq_puts(m, "\n");

crtc = &mixer->drm_crtc;