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[PATCH V3 00/14] arm64/sysreg: Convert TRBE registers to automatic generation

by Anshuman Khandual

This series converts TRBE registers to automatic generation, after renaming their fields as per the auto-gen tools format. Although the following field still renames in arch/arm64/include/asm/sysreg.h, as it cannot be converted (shares bits with other fields) in the tools format. #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 This series applies on v6.4-rc6. Changes in V3: - Defined enum for both PAS and SH fields in TRBMAR_EL1 - Defined enum for EA field in TRBIDR_EL1 Changes in V2: https://lore.kernel.org/all/20230602062552.565992-1-anshuman.khandual@arm.c… - Renamed each individual TRBE register fields as per auto-gen tools - Converted each individual TRBE registers as per auto-gen tools - Added new register fields as per DDI0601 2023-03 Changes in V1: https://lore.kernel.org/all/20230531055524.16562-1-anshuman.khandual@arm.co… Cc: Catalin Marinas <catalin.marinas(a)arm.com> Cc: Will Deacon <will(a)kernel.org> Cc: Marc Zyngier <maz(a)kernel.org> Cc: Mark Brown <broonie(a)kernel.org> Cc: Rob Herring <robh(a)kernel.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: James Morse <james.morse(a)arm.com> Cc: kvmarm(a)lists.linux.dev Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Anshuman Khandual (14): arm64/sysreg: Rename TRBLIMITR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBSR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen tools format arm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen tools format arm64/sysreg: Convert TRBLIMITR_EL1 register to automatic generation arm64/sysreg: Convert TRBPTR_EL1 register to automatic generation arm64/sysreg: Convert TRBBASER_EL1 register to automatic generation arm64/sysreg: Convert TRBSR_EL1 register to automatic generation arm64/sysreg: Convert TRBMAR_EL1 register to automatic generation arm64/sysreg: Convert TRBTRG_EL1 register to automatic generation arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation arch/arm64/include/asm/el2_setup.h | 2 +- arch/arm64/include/asm/sysreg.h | 50 +------------ arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- arch/arm64/tools/sysreg | 77 ++++++++++++++++++++ drivers/hwtracing/coresight/coresight-trbe.c | 33 +++++---- drivers/hwtracing/coresight/coresight-trbe.h | 38 ++++------ 7 files changed, 114 insertions(+), 90 deletions(-) -- 2.25.1

2 years, 8 months

[PATCH v3 0/5] perf cs-etm: Track exception level

by James Clark

Changes since v2: * Rename prev_thread -> prev_packet_thread and prev_el -> prev_packet_el * Add a comment about tracking the previous packet's thread Changes since v1: * Always assume host kernel when the trace was captured at EL1 (nVHE) * Fix EL validation to work with ETMv3 * Add a commit to make PID format accessible from struct cs_etm_auxtrace ====== Some fixes to support an issue reported by Denis Nikitin where decoding trace that contains different EL1 and EL2 kernels can crash or go into an infinite loop because the wrong kernel maps are used for the decode. This still doesn't support distinguishing guest and host userspace, we'd still have to fix the timestamps and do a bit more work to correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a possible outcome of cs_etm__cpu_mode(). As far as I know this could never have been returned anyway because machine__is_host(machine) was always true due to session.machines.host being hard coded. And I'm not sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL and PERF_RECORD_MISC_HYPERVISOR in this scenario. The first commit is a tidy up, second fixes a bug that I found when comparing the exception level and thread of branch records, the third is the main fix, and the last commit is some extra error checking. Applies to acme/perf-tools-next (42713dafc) James Clark (5): perf cs-etm: Only track threads instead of PID and TIDs perf cs-etm: Use previous thread for branch sample source IP perf cs-etm: Make PID format accessible from struct cs_etm_auxtrace perf cs-etm: Track exception level perf cs-etm: Add exception level consistency check .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 33 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +- tools/perf/util/cs-etm.c | 282 ++++++++++-------- tools/perf/util/cs-etm.h | 13 +- 4 files changed, 184 insertions(+), 148 deletions(-) -- 2.34.1

2 years, 8 months

Re: [PATCH V2 00/14] arm64/sysreg: Convert TRBE registers to automatic generation

by Anshuman Khandual

On 6/8/23 23:09, Catalin Marinas wrote: > Hi Anshuman, > > On Fri, Jun 02, 2023 at 11:55:38AM +0530, Anshuman Khandual wrote: >> Changes in V2: >> >> - Renamed each individual TRBE register fields as per auto-gen tools >> - Converted each individual TRBE registers as per auto-gen tools >> - Added new register fields as per DDI0601 2023-03 > > Mark had some comments about using Enum for some bitfields. While not > essential, it would be nice to have those fixed. It's probably easier to > do an incremental patch fixing those, so please post one (or repost the > whole series, whatever is easier for you). Sure, will fold in those suggested changes and re-post the series soon.

2 years, 8 months

Re: [PATCH V2 14/14] arm64/sysreg: Convert TRBIDR_EL1 register to automatic generation

by Anshuman Khandual

On 6/2/23 17:42, Mark Brown wrote: > On Fri, Jun 02, 2023 at 11:55:52AM +0530, Anshuman Khandual wrote: >> This converts TRBIDR_EL1 register to automatic generation without >> causing any functional change. > >> +Sysreg TRBIDR_EL1 3 0 9 11 7 >> +Res0 63:12 >> +Field 11:8 EA > > EA is another field which looks like it should be an enum, as with the > others this shouldn't be a blocker and could be done incrementally. Will fold the following changes in this patch. --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2267,7 +2267,11 @@ EndSysreg Sysreg TRBIDR_EL1 3 0 9 11 7 Res0 63:12 -Field 11:8 EA +Enum 11:8 EA + 0b0000 NON_DESC + 0b0001 IGNORE + 0b0010 SERROR +EndEnum Res0 7:6 Field 5 F Field 4 P > >> +Res0 7:6 >> +Field 5 F >> +Field 4 P >> +Field 3:0 Align > > Align arguably too though really it's just encoding the relevant power > of 2 with the enum coming from the fact that it's limited to at most 2KB > alignment so a Field may well make more sense. Can fold the following changes in this patch (if required) unless the Field looks better than Enum. --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2275,5 +2275,18 @@ EndEnum Res0 7:6 Field 5 F Field 4 P -Field 3:0 Align +Enum 3:0 Align + 0b0000 BYTE + 0b0001 HALF_WORD + 0b0010 WORD + 0b0011 DOUBLE_WORD + 0b0100 16_BYTES + 0b0101 32_BYTES + 0b0110 64_BYTES + 0b0111 128_BYTES + 0b1000 156_BYTES + 0b1001 512_BYTES + 0b1010 1_KB + 0b1011 2_KB +EndEnum EndSysreg > > Reviewed-by: Mark Brown <broonie(a)kernel.org>

2 years, 8 months

Re: [PATCH V2 12/14] arm64/sysreg: Convert TRBMAR_EL1 register to automatic generation

by Anshuman Khandual

On 6/2/23 17:35, Mark Brown wrote: > On Fri, Jun 02, 2023 at 11:55:50AM +0530, Anshuman Khandual wrote: > >> +Sysreg TRBMAR_EL1 3 0 9 11 4 >> +Res0 63:12 >> +Field 11:10 PAS >> +Field 9:8 SH >> +Field 7:0 Attr >> +EndSysreg > > PAS and SH look like they should be enums, Attr is a bit more complex so > Field is probably a good fit there. Adding the enum information could > be done incrementally though so: Will fold the following changes in this patch. --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2246,8 +2246,17 @@ EndSysreg Sysreg TRBMAR_EL1 3 0 9 11 4 Res0 63:12 -Field 11:10 PAS -Field 9:8 SH +Enum 11:10 PAS + 0b00 SECURE + 0b01 NON_SECURE + 0b10 ROOT + 0b11 REALM +EndEnum +Enum 9:8 SH + 0b00 NON_SHAREABLE + 0b10 OUTER_SHAREABLE + 0b11 INNER_SHAREABLE +EndEnum Field 7:0 Attr EndSysreg > > Reviewed-by: Mark Brown <broonie(a)kernel.org>

2 years, 8 months

[PATCH] MAINTAINERS: coresight: Add James Clark as Reviewer

by Suzuki K Poulose

James has made significant contributions to the CoreSight subsystem both with code and reviews. Add James to the Reviewer for the subsystem. Cc: James Clark <james.clark(a)arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 250518fc70ff..c01a70ed2a36 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2097,6 +2097,7 @@ N: digicolor ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Suzuki K Poulose <suzuki.poulose(a)arm.com> R: Mike Leach <mike.leach(a)linaro.org> +R: James Clark <james.clark(a)arm.com> R: Leo Yan <leo.yan(a)linaro.org> L: coresight(a)lists.linaro.org (moderated for non-subscribers) L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) -- 2.34.1

2 years, 8 months

[PATCH v2 0/5] perf cs-etm: Track exception level

by James Clark

Changes since v1: * Always assume host kernel when the trace was captured at EL1 (nVHE) * Fix EL validation to work with ETMv3 * Add a commit to make PID format accessible from struct cs_etm_auxtrace ====== Some fixes to support an issue reported by Denis Nikitin where decoding trace that contains different EL1 and EL2 kernels can crash or go into an infinite loop because the wrong kernel maps are used for the decode. This still doesn't support distinguishing guest and host userspace, we'd still have to fix the timestamps and do a bit more work to correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a possible outcome of cs_etm__cpu_mode(). As far as I know this could never have been returned anyway because machine__is_host(machine) was always true due to session.machines.host being hard coded. And I'm not sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL and PERF_RECORD_MISC_HYPERVISOR in this scenario. The first commit is a tidy up, second fixes a bug that I found when comparing the exception level and thread of branch records, the third is the main fix, and the last commit is some extra error checking. Applies to acme/perf-tools (48b1320a67) James Clark (5): perf cs-etm: Only track threads instead of PID and TIDs perf cs-etm: Use previous thread for branch sample source IP perf cs-etm: Make PID format accessible from struct cs_etm_auxtrace perf cs-etm: Track exception level perf cs-etm: Add exception level consistency check .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 33 +-- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +- tools/perf/util/cs-etm.c | 273 ++++++++++-------- tools/perf/util/cs-etm.h | 13 +- 4 files changed, 175 insertions(+), 148 deletions(-) -- 2.34.1

2 years, 8 months

[PATCH 0/4] perf cs-etm: Track exception level

by James Clark

Some fixes to support an issue reported by Denis Nikitin where decoding trace that contains different EL1 and EL2 kernels can crash or go into an infinite loop because the wrong kernel maps are used for the decode. This still doesn't support distinguishing guest and host userspace, we'd still have to fix the timestamps and do a bit more work to correlate that. And I've removed PERF_RECORD_MISC_HYPERVISOR as a possible outcome of cs_etm__cpu_mode(). As far as I know this could never have been returned anyway because machine__is_host(machine) was always true due to session.machines.host being hard coded. And I'm not sure of the relevance of the difference between PERF_RECORD_MISC_KERNEL and PERF_RECORD_MISC_HYPERVISOR in this scenario. The first commit is a tidy up, second fixes a bug that I found when comparing the exception level and thread of branch records, the third is the main fix, and the last commit is some extra error checking. Applies to acme/perf-tools (4e111f0cf0) James Clark (4): perf cs-etm: Only track threads instead of PID and TIDs perf cs-etm: Use previous thread for branch sample source IP perf cs-etm: Track exception level perf cs-etm: Add exception level consistency check .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 13 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 4 +- tools/perf/util/cs-etm.c | 220 +++++++++--------- tools/perf/util/cs-etm.h | 5 +- 4 files changed, 126 insertions(+), 116 deletions(-) -- 2.34.1

2 years, 9 months

[PATCH] coresight: tmc: Explicit type conversions to prevent integer overflow

by Ruidong Tian

"nr_pages << PAGE_SHIFT" will overflow when nr_pages is integer and nr_pages >= 0x80000. That means Coresight ETR can not alloc more than 1G buffer. Explicit convert nr_pages to 64 bit to avoid overflow. Signed-off-by: Ruidong Tian <tianruidong(a)linux.alibaba.com> --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 766325de0e29..1425ecd1cf78 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1267,7 +1267,7 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, * than the size requested via sysfs. */ if ((nr_pages << PAGE_SHIFT) > drvdata->size) { - etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT), + etr_buf = tmc_alloc_etr_buf(drvdata, ((ssize_t)nr_pages << PAGE_SHIFT), 0, node, NULL); if (!IS_ERR(etr_buf)) goto done; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index b97da39652d2..0ee48c5ba764 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -325,7 +325,7 @@ ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, static inline unsigned long tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) { - return sg_table->data_pages.nr_pages << PAGE_SHIFT; + return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT; } struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); -- 2.33.1

2 years, 9 months

[PATCH] coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE

by Suzuki K Poulose

Instead of adding the PIDs forever to the list for the new CPUs, let us detect a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com Cc: Anshuman Khandual <anshuman.khandual(a)arm.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: frowand.list(a)gmail.com Cc: linux(a)armlinux.org.uk Cc: Mike Leach <mike.leach(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- .../coresight/coresight-etm4x-core.c | 5 +++++ drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4c15fae534f3..8a2e24d5686a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ + /* + * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new + * CPUs to the list here. + */ + CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), {}, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 595ce5862056..72ec36c9232c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); } /* coresight AMBA ID, full UCI structure: id table entry. */ -#define CS_AMBA_UCI_ID(pid, uci_ptr) \ +#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ { \ .id = pid, \ - .mask = 0x000fffff, \ + .mask = m, \ .data = (void *)uci_ptr \ } +#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) +/* + * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the + * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that + * as a match value for blanket matching all devices in the given CoreSight + * device type and architecture. + */ +#define PIDR2_JEDEC BIT(3) +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) +/* + * Match all PIDs in a given CoreSight device type and architecture, defined + * by the uci. + */ +#define CS_AMBA_MATCH_ALL_UCI(uci) \ + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) -- 2.34.1

2 years, 9 months

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