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[PATCH v17 0/9] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series: [v7,00/15] coresight: Add new API to allocate trace source ID values https://patchwork.kernel.org/project/linux-arm-kernel/cover/20230116124928.… TPDM_TPDA commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-tpda-v… Changes in V17: 1. Rebase changes on V7 coresight: Add new API to allocate trace source ID values 2. Add documentation for TPDA and TPDM under Documentation/tracing/coresight/. (Suzuki K Poulose <suzuki.poulose(a)arm.com>) Changes in V16: 1. Update device tree changes to match up with device tree bindings. 3. Update the copyright year to 2023. Changes in V15: 1. coresight-tpda: Add more comments in trace id function. 2. qcom,coresight-tpdm.yaml: Add more comments in description. 3. Push "arm64: dts: qcom: sm8250: Add coresight components" out this series. Changes in V14: rebase to "[v5,00/14] coresight: Add new API to allocate trace source ID values" and latest 6.x kernel Changes in V13: 1. Fix the conflicts when apply patches to the latest base line. Changes in V12: 1. Clear bits for atid before setting them and relese atid when tpda remove. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Changes in V11: 1. Change dev_info to dev_dbg in TPDM/TPDA drivers. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Merge sysfs API change of integration_test to integration_test driver change. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Changes in V10: 1. Fix the error of TPDM yaml file. -- Rob Herring <robh(a)kernel.org> Changes in V9: 1. Rename yaml file for TPDM/TPDA and fix the error for the yaml files. -- Rob Herring <robh(a)kernel.org> Changes in V8: 1. Use spinlock to protect drvdata of TPDM/TPDA -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Use CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS as source type for TPDM -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 3. Fix the warning for yaml file of TPDM/TPDA -- Rob Herring <robh(a)kernel.org> Changes in V7: 1. Update the commit title and move the changes to right place which is sorted by address for dtsi changes. -- Konrad Dybcio <konrad.dybcio(a)somainline.org> Changes in V6: 1. Update maintainers in tpdm/tpda yaml file. -- Mike Leach <mike.leach(a)linaro.org> 2. Set the .remove function pointer in the amba_driver structure of tpdm/tpda driver. Add tpda_remove function for tpda driver. -- Mike Leach <mike.leach(a)linaro.org> 3. Define datasets of tpdm as unsigned long. -- Mike Leach <mike.leach(a)linaro.org> 4. Move all coresight nodes to sm8250.dtsi. -- Mike Leach <mike.leach(a)linaro.org>;Konrad Dybcio <konrad.dybcio(a)somainline.org> 5. Remove CORESIGHT_TPDM_INTEGRATION_TEST config. -- Mike Leach <mike.leach(a)linaro.org> Changes in V5: 1. Keep the ETM source paths per-CPU and use IDR for other sources' paths. (Suzuki K Poulose <suzuki.poulose(a)arm.com>) Changes in V4: 1. Drop trace id for tpdm source as its trace atid is defined by the tpda. Allocate tpda's atid dynamically. (Mike Leach) Changes in V3: 1. Use bitmap to assign the trace id. (Mathieu Poirier) Changes in V2: 1. Use IDR to store the path of sources. (Mathieu Poirier) 2. Only add integration_test/enable/disable for TPDM. No other configs. (Mathieu Poirier) 3. Move coresight dtsi changes to sm8250.dtsi. (Suzuki K Poulose) Mao Jinlong (9): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Add CoreSight TPDM hardware coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions Documentation: trace: Add documentation for TPDM and TPDA arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 129 +++++++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++++++ .../trace/coresight/coresight-tpda.rst | 52 ++++ .../trace/coresight/coresight-tpdm.rst | 43 +++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 164 +++++++++++ drivers/hwtracing/coresight/Kconfig | 23 ++ drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 ++- drivers/hwtracing/coresight/coresight-tpda.c | 211 ++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 259 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 +++++ include/linux/coresight.h | 1 + 15 files changed, 1118 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 Documentation/trace/coresight/coresight-tpda.rst create mode 100644 Documentation/trace/coresight/coresight-tpdm.rst create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.39.0

2 years, 9 months

Re: [PATCH 1/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read

by Mike Leach

Hi Steve, On Fri, 20 Jan 2023 at 00:52, Steve Clevenger <scclevenger(a)os.amperecomputing.com> wrote: > > Add Ampere early clear of ETM TRCOSLAR.OSLK prior to TRCIDR1 access. > Ampere Computing erratum AC03_DEBUG_06 describes an Ampere > Computing design decision MMIO reads are considered the same as an > external debug access. If TRCOSLAR.OSLK is set, the TRCIDR1 access > results in a bus fault followed by a kernel panic. A TRCIDR1 read > is valid regardless of TRCOSLAR.OSLK provided MMIO access > (now deprecated) is supported. > AC03_DEBUG_06 is described in the AmpereOne Developer Errata: > https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… > > Add Ampere ETM PID required for Coresight ETM driver support. > > Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> > --- > .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 32 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1cc052979e01..533be1928a09 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1091,19 +1091,34 @@ static void etm4_init_arch_data(void *info) > drvdata = dev_get_drvdata(init_arg->dev); > csa = init_arg->csa; > As far as I can tell there appears to be an initialisation issue here. etm_probe() ... struct csdev_access access = { 0 }; ... init_arg.csa = &access ::call=> etm4_init_arch_data(init_arg) Thus csa is uninitialised? > + /* Detect the support for OS Lock before we actually use it */ > + etm_detect_os_lock(drvdata, csa); > + > + /* > + * For ETM implementations that consider MMIO an external access > + * clear TRCOSLAR.OSLK early. > + */ > + if (drvdata->mmio_external) > + etm4_os_unlock_csa(drvdata, csa); > + > /* > * If we are unable to detect the access mechanism, > * or unable to detect the trace unit type, fail > - * early. > + * early. Reset TRCOSLAR.OSLK if cleared. > */ > - if (!etm4_init_csdev_access(drvdata, csa)) > + if (!etm4_init_csdev_access(drvdata, csa)) { This call initialises csa according to sysreg / iomem access requirements > + if (drvdata->mmio_external) > + etm4_os_lock(drvdata); > return; > + } > > - /* Detect the support for OS Lock before we actually use it */ > - etm_detect_os_lock(drvdata, csa); > + /* > + * Make sure all registers are accessible > + * TRCOSLAR.OSLK may already be clear > + */ > + if (!drvdata->mmio_external) > + etm4_os_unlock_csa(drvdata, csa); > > - /* Make sure all registers are accessible */ > - etm4_os_unlock_csa(drvdata, csa); > etm4_cs_unlock(drvdata, csa); > > etm4_check_arch_features(drvdata, init_arg->pid); > @@ -2027,6 +2042,14 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > init_arg.csa = &access; > init_arg.pid = etm_pid; > > + /* > + * Ampere ETM v4.6 considers MMIO access as external. This mask > + * isolates the manufacturer JEP106 ID in the PID. > + * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) > + */ > + if ((init_arg.pid & 0x000FF000) == 0x00096000) > + drvdata->mmio_external = true; > + > /* > * Serialize against CPUHP callbacks to avoid race condition > * between the smp call and saving the delayed probe. > @@ -2192,6 +2215,7 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ > CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ > CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ > + CS_AMBA_UCI_ID(0x00096000, uci_id_etm4),/* Ampere ARMv8 */ > CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ > CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ > CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4b21bb79f168..cf4f9f2e1807 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -1015,6 +1015,7 @@ struct etmv4_save_state { > * @skip_power_up: Indicates if an implementation can skip powering up > * the trace unit. > * @arch_features: Bitmap of arch features of etmv4 devices. > + * @mmio_external: True if ETM considers MMIO an external access. > */ > struct etmv4_drvdata { > void __iomem *base; > @@ -1067,6 +1068,7 @@ struct etmv4_drvdata { > bool state_needs_restore; > bool skip_power_up; > DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); Rather than continue to add bools - is it not worthwhile adding to the bitmap above and extending the arch features API to allow a "has_feature" call? > + bool mmio_external; > }; > > /* Address comparator access types */ > -- > 2.25.1 > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

Re: [PATCH 3/3] coresight etm4x: Add pr_debug statement for Coresight component PID/CID

by Suzuki K Poulose

Cc: Russell nit: Subject line doesn't match the patch. This could be : "amba: bus: Add pr_debug for AMBA PID/CID" On 20/01/2023 00:51, Steve Clevenger wrote: > Add pr_debug statement to provide visibility into Coresight component PID > and CID settings. This helped debug an intermittent clock related issue > resulting in bad PID/CID values. And this change belongs to the AMBA subsystem. Please run : scripts/get_maintainer.pl on your patch and add the necessary people from that list for your patch. As such, I don't think brings any value to be added to the tree. I will leave it for the maintainers to comment. Suzuki > > Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> > --- > drivers/amba/bus.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c > index ff7454a38058..7c432442862c 100644 > --- a/drivers/amba/bus.c > +++ b/drivers/amba/bus.c > @@ -136,6 +136,7 @@ static int amba_read_periphid(struct amba_device *dev) > u32 size, pid, cid; > void __iomem *tmp; > int i, ret; > + u32 cid_addr, pid_addr; > > ret = dev_pm_domain_attach(&dev->dev, true); > if (ret) { > @@ -178,6 +179,12 @@ static int amba_read_periphid(struct amba_device *dev) > for (cid = 0, i = 0; i < 4; i++) > cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); > > + /* physical address as meaningful */ > + cid_addr = (u64)(dev->res.start + size - 0x20); > + pid_addr = (u64)(dev->res.start + size - 0x10); > + > + pr_debug("pid (%llX): %08X cid (%llX): %08X\n", pid_addr, pid, cid_addr, cid); > + > if (cid == CORESIGHT_CID) { > /* set the base to the start of the last 4k block */ > void __iomem *csbase = tmp + size - 4096;

2 years, 9 months

Re: [PATCH 1/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read

by Suzuki K Poulose

Hi Steve Thanks for the patches. Have a few comments below. On 20/01/2023 00:51, Steve Clevenger wrote: > Add Ampere early clear of ETM TRCOSLAR.OSLK prior to TRCIDR1 access. > Ampere Computing erratum AC03_DEBUG_06 describes an Ampere > Computing design decision MMIO reads are considered the same as an > external debug access. If TRCOSLAR.OSLK is set, the TRCIDR1 access > results in a bus fault followed by a kernel panic. A TRCIDR1 read > is valid regardless of TRCOSLAR.OSLK provided MMIO access > (now deprecated) is supported. > AC03_DEBUG_06 is described in the AmpereOne Developer Errata: > https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… Please could you add this erratum to the : Documentation/arm64/silicon-errata.rst ? Given the ETM is v4.6, doesn't it support system instructions and that is causing this issue of "MMIO access is considered external" ? If it does, I think we should drop all of this and simply wire the system instruction access support. > > Add Ampere ETM PID required for Coresight ETM driver support. > > Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> > --- > .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ > 2 files changed, 32 insertions(+), 6 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1cc052979e01..533be1928a09 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1091,19 +1091,34 @@ static void etm4_init_arch_data(void *info) > drvdata = dev_get_drvdata(init_arg->dev); > csa = init_arg->csa; > > + /* Detect the support for OS Lock before we actually use it */ > + etm_detect_os_lock(drvdata, csa); > + > + /* > + * For ETM implementations that consider MMIO an external access > + * clear TRCOSLAR.OSLK early. > + */ > + if (drvdata->mmio_external) > + etm4_os_unlock_csa(drvdata, csa); > + > /* > * If we are unable to detect the access mechanism, > * or unable to detect the trace unit type, fail > - * early. > + * early. Reset TRCOSLAR.OSLK if cleared. > */ > - if (!etm4_init_csdev_access(drvdata, csa)) > + if (!etm4_init_csdev_access(drvdata, csa)) { > + if (drvdata->mmio_external) > + etm4_os_lock(drvdata); Couldn't this unlock/lock sequence be moved into the etm4_init_csdev_iomem_access() where it actually matters ? Or thinking more about it, we could actually move the unlock step early for all ETMs irrespective of whether they are affected by this erratum. Of course, putting this back, if we fail to detect the ETM properly. I don't see any issue with that. > return; > + } > > - /* Detect the support for OS Lock before we actually use it */ > - etm_detect_os_lock(drvdata, csa); > + /* > + * Make sure all registers are accessible > + * TRCOSLAR.OSLK may already be clear > + */ > + if (!drvdata->mmio_external) > + etm4_os_unlock_csa(drvdata, csa); > > - /* Make sure all registers are accessible */ > - etm4_os_unlock_csa(drvdata, csa); > etm4_cs_unlock(drvdata, csa); > > etm4_check_arch_features(drvdata, init_arg->pid); > @@ -2027,6 +2042,14 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) > init_arg.csa = &access; > init_arg.pid = etm_pid; > > + /* > + * Ampere ETM v4.6 considers MMIO access as external. This mask > + * isolates the manufacturer JEP106 ID in the PID. > + * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) > + */ Does it affect all Ampere ETMs ? You seem to be ignoring the PDIR1.PART_1, PDIR0_PART_0 fields, which happens to be 0. > + if ((init_arg.pid & 0x000FF000) == 0x00096000) > + drvdata->mmio_external = true; Like I said, we may be able to get rid of this flag and do the step for all ETMs. But before all of that, I would like to see if this is problem because we are skipping the system instruction route. Suzuki > /* > * Serialize against CPUHP callbacks to avoid race condition > * between the smp call and saving the delayed probe. > @@ -2192,6 +2215,7 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ > CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ > CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ > + CS_AMBA_UCI_ID(0x00096000, uci_id_etm4),/* Ampere ARMv8 */ > CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ > CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ > CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4b21bb79f168..cf4f9f2e1807 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -1015,6 +1015,7 @@ struct etmv4_save_state { > * @skip_power_up: Indicates if an implementation can skip powering up > * the trace unit. > * @arch_features: Bitmap of arch features of etmv4 devices. > + * @mmio_external: True if ETM considers MMIO an external access. > */ > struct etmv4_drvdata { > void __iomem *base; > @@ -1067,6 +1068,7 @@ struct etmv4_drvdata { > bool state_needs_restore; > bool skip_power_up; > DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); > + bool mmio_external; > }; > > /* Address comparator access types */

2 years, 9 months

[RESPIN PATCH v17 2/9] Coresight: Add coresight TPDM source driver

by Mao Jinlong

Add driver to support Coresight device TPDM (Trace, Profiling and Diagnostics Monitor). TPDM is a monitor to collect data from different datasets. This change is to add probe/enable/disable functions for tpdm source. Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/Kconfig | 12 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-core.c | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 149 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 26 ++++ include/linux/coresight.h | 1 + 6 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index ba035d7894e0..e2debad59608 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -213,4 +213,16 @@ config ULTRASOC_SMB To compile this driver as a module, choose M here: the module will be called ultrasoc-smb. + +config CORESIGHT_TPDM + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for configuring monitor. Monitors are + primarily responsible for data set collection and support the + ability to collect any permutation of data set types. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpdm. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index 80f99d915bc9..c637376e0efd 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 5eb013f49a0d..a798008ac56e 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1061,7 +1061,8 @@ static int coresight_validate_source(struct coresight_device *csdev, } if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) { + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; } @@ -1130,6 +1131,7 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: /* * Use the hash of source's device name as ID * and map the ID to the pointer of the path. @@ -1179,6 +1181,7 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); /* Find the path by the hash. */ path = idr_find(&path_idr, hash); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c new file mode 100644 index 000000000000..baeabc2ab168 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/amba/bus.h> +#include <linux/bitmap.h> +#include <linux/coresight.h> +#include <linux/coresight-pmu.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/fs.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> + +#include "coresight-priv.h" +#include "coresight-tpdm.h" + +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); + +/* TPDM enable operations */ +static int tpdm_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return -EBUSY; + } + + drvdata->enable = true; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); + return 0; +} + +/* TPDM disable operations */ +static void tpdm_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (!drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return; + } + + drvdata->enable = false; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); +} + +static const struct coresight_ops_source tpdm_source_ops = { + .enable = tpdm_enable, + .disable = tpdm_disable, +}; + +static const struct coresight_ops tpdm_cs_ops = { + .source_ops = &tpdm_source_ops, +}; + +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) +{ + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpdm_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + /* driver data*/ + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + /* Set up coresight component description */ + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type = CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.ops = &tpdm_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(base); + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + spin_lock_init(&drvdata->spinlock); + /* Decrease pm refcount when probe is done.*/ + pm_runtime_put(&adev->dev); + + return 0; +} + +static void __exit tpdm_remove(struct amba_device *adev) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDM has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpdm_ids[] = { + { + .id = 0x000f0e00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpdm_driver = { + .drv = { + .name = "coresight-tpdm", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpdm_probe, + .id_table = tpdm_ids, + .remove = tpdm_remove, +}; + +module_amba_driver(tpdm_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h new file mode 100644 index 000000000000..2ec8a6810771 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDM_H +#define _CORESIGHT_CORESIGHT_TPDM_H + +/** + * struct tpdm_drvdata - specifics associated to an TPDM component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @spinlock: lock for the drvdata value. + * @enable: enable status of the component. + */ + +struct tpdm_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + bool enable; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index e241eb88dfb9..f19a47b9bb5a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; enum coresight_dev_subtype_helper { -- 2.39.0

2 years, 9 months

[PATCH v7 00/15] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Appies to coresight/next Changes since v6: 1) Export perf_report_aux_output_id() Acked by Peter, 2) Update to ETMv3 docs requested by suzuki 3) rebased and re-tested on coresight/next (6.2-rc2) Changes since v5: (requested by suzuki) 1) Prefer odd ID values for system IDs to avoid overlap with legacy CPU IDs 2) Some style changes Changes since v4: 1) update to ensure that compiling after each individual patch added still works - ie. git bisect not broken through the patchset.. 2) Revision to some of the now redundant code in cs-etm (James) 3) Comments and other minor fixes requested by Suzuki. Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (15): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: perf: traceid: Add perf ID allocation and notifiers coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: trace id: Remove legacy get trace ID function. perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation coresight: etm3x: docs: Alter sysfs documentation for trace id updates .../testing/sysfs-bus-coresight-devices-etm3x | 2 +- drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 45 --- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 93 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 73 +++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 298 ++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 156 +++++++++ include/linux/coresight-pmu.h | 34 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 325 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 21 files changed, 1024 insertions(+), 230 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 9 months

Re: [PATCH -next] coresight: ultrasoc-smb: fix return value check in smb_init_data_buffer()

by Suzuki K Poulose

On 18/01/2023 07:49, Yang Yingliang wrote: > platform_get_resource() returns NULL pointer not PTR_ERR(), replace > the IS_ERR() check with NULL pointer check. > > Fixes: 06f5c2926aaa ("drivers/coresight: Add UltraSoc System Memory Buffer driver") We cannot use a Fixes tag on a commit that is not in Linus's tree. I will queue this without the tag. Thanks Suzuki > Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> > --- > drivers/hwtracing/coresight/ultrasoc-smb.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c > index 2560fdbb8ebf..b317342c7ce5 100644 > --- a/drivers/hwtracing/coresight/ultrasoc-smb.c > +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c > @@ -455,7 +455,7 @@ static int smb_init_data_buffer(struct platform_device *pdev, > void *base; > > res = platform_get_resource(pdev, IORESOURCE_MEM, SMB_BUF_ADDR_RES); > - if (IS_ERR(res)) { > + if (!res) { > dev_err(&pdev->dev, "SMB device failed to get resource\n"); > return -EINVAL; > }

2 years, 9 months

[PATCH v16 0/8] Coresight: Add support for TPDM and TPDA

by Mao Jinlong

This series adds support for the trace performance monitoring and diagnostics hardware (TPDM and TPDA). It is composed of two major elements. a) Changes for original coresight framework to support for TPDM and TPDA. b) Add driver code for TPDM and TPDA. Introduction of changes for original coresight framework Support TPDM as new coresight source. Since only STM and ETM are supported as coresight source originally. TPDM is a newly added coresight source. We need to change the original way of saving coresight path to support more types source for coresight driver. The following patch is to add support more coresight sources. coresight: core: Use IDR for non-cpu bound sources' paths. Introduction of TPDM and TPDA TPDM - The trace performance monitoring and diagnostics monitor or TPDM in short serves as data collection component for various dataset types specified in the QPMDA(Qualcomm performance monitoring and diagnostics architecture) spec. The primary use case of the TPDM is to collect data from different data sources and send it to a TPDA for packetization, timestamping and funneling. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware definitions coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support TPDA - The trace performance monitoring and diagnostics aggregator or TPDA in short serves as an arbitration and packetization engine for the performance monitoring and diagnostics network as specified in the QPMDA (Qualcomm performance monitoring and diagnostics architecture) specification. The primary use case of the TPDA is to provide packetization, funneling and timestamping of Monitor data as specified in the QPMDA specification. The following patch is to add driver for TPDA. Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions The last patch of this series is a device tree modification, which add the TPDM and TPDA configuration to device tree for validating. ARM: dts: msm: Add tpdm mm/prng for sm8250 Once this series patches are applied properly, the tpdm and tpda nodes should be observed at the coresight path /sys/bus/coresight/devices e.g. /sys/bus/coresight/devices # ls -l | grep tpd tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 tpdm0 -> ../../../devices/platform/soc(a)0/6c08000.mm.tpdm/tpdm0 We can use the commands are similar to the below to validate TPDMs. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test The test data will be collected in the coresight sink which is enabled. If rwp register of the sink is keeping updating when do integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM to sink. There must be a tpda between tpdm and the sink. When there are some other trace event hw components in the same HW block with tpdm, tpdm and these hw components will connect to the coresight funnel. When there is only tpdm trace hw in the HW block, tpdm will connect to tpda directly. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ This patch series depends on patch series: "[v6,00/14] coresight: Add new API to allocate trace source ID values" https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221123195010.… TPDM_TPDA commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-tpda-v… Changes in V16: 1. Update device tree changes to match up with device tree bindings. 3. Update the copyright year to 2023. Changes in V15: 1. coresight-tpda: Add more comments in trace id function. 2. qcom,coresight-tpdm.yaml: Add more comments in description. 3. Push "arm64: dts: qcom: sm8250: Add coresight components" out this series. Changes in V14: rebase to "[v5,00/14] coresight: Add new API to allocate trace source ID values" and latest 6.x kernel Changes in V13: 1. Fix the conflicts when apply patches to the latest base line. Changes in V12: 1. Clear bits for atid before setting them and relese atid when tpda remove. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Changes in V11: 1. Change dev_info to dev_dbg in TPDM/TPDA drivers. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Merge sysfs API change of integration_test to integration_test driver change. -- Suzuki K Poulose <suzuki.poulose(a)arm.com> Changes in V10: 1. Fix the error of TPDM yaml file. -- Rob Herring <robh(a)kernel.org> Changes in V9: 1. Rename yaml file for TPDM/TPDA and fix the error for the yaml files. -- Rob Herring <robh(a)kernel.org> Changes in V8: 1. Use spinlock to protect drvdata of TPDM/TPDA -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 2. Use CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS as source type for TPDM -- Suzuki K Poulose <suzuki.poulose(a)arm.com> 3. Fix the warning for yaml file of TPDM/TPDA -- Rob Herring <robh(a)kernel.org> Changes in V7: 1. Update the commit title and move the changes to right place which is sorted by address for dtsi changes. -- Konrad Dybcio <konrad.dybcio(a)somainline.org> Changes in V6: 1. Update maintainers in tpdm/tpda yaml file. -- Mike Leach <mike.leach(a)linaro.org> 2. Set the .remove function pointer in the amba_driver structure of tpdm/tpda driver. Add tpda_remove function for tpda driver. -- Mike Leach <mike.leach(a)linaro.org> 3. Define datasets of tpdm as unsigned long. -- Mike Leach <mike.leach(a)linaro.org> 4. Move all coresight nodes to sm8250.dtsi. -- Mike Leach <mike.leach(a)linaro.org>;Konrad Dybcio <konrad.dybcio(a)somainline.org> 5. Remove CORESIGHT_TPDM_INTEGRATION_TEST config. -- Mike Leach <mike.leach(a)linaro.org> Changes in V5: 1. Keep the ETM source paths per-CPU and use IDR for other sources' paths. (Suzuki K Poulose <suzuki.poulose(a)arm.com>) Changes in V4: 1. Drop trace id for tpdm source as its trace atid is defined by the tpda. Allocate tpda's atid dynamically. (Mike Leach) Changes in V3: 1. Use bitmap to assign the trace id. (Mathieu Poirier) Changes in V2: 1. Use IDR to store the path of sources. (Mathieu Poirier) 2. Only add integration_test/enable/disable for TPDM. No other configs. (Mathieu Poirier) 3. Move coresight dtsi changes to sm8250.dtsi. (Suzuki K Poulose) Mao Jinlong (8): coresight: core: Use IDR for non-cpu bound sources' paths. Coresight: Add coresight TPDM source driver dt-bindings: arm: Adds CoreSight TPDM hardware coresight-tpdm: Add DSB dataset support coresight-tpdm: Add integration test support Coresight: Add TPDA link driver dt-bindings: arm: Adds CoreSight TPDA hardware definitions arm64: dts: qcom: sm8250: Add tpdm mm/prng .../testing/sysfs-bus-coresight-devices-tpdm | 13 + .../bindings/arm/qcom,coresight-tpda.yaml | 129 +++++++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 93 +++++++ MAINTAINERS | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 164 +++++++++++ drivers/hwtracing/coresight/Kconfig | 23 ++ drivers/hwtracing/coresight/Makefile | 2 + drivers/hwtracing/coresight/coresight-core.c | 42 ++- drivers/hwtracing/coresight/coresight-tpda.c | 211 ++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 35 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 259 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 62 +++++ include/linux/coresight.h | 1 + 13 files changed, 1023 insertions(+), 12 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h -- 2.39.0

2 years, 9 months

Re: [PATCH v5 3/6] coresight: configfs: Add in binary attributes to load files

by Mike Leach

Hi Christoph On Tue, 27 Dec 2022 at 17:09, Christoph Hellwig <hch(a)infradead.org> wrote: > > On Mon, Dec 19, 2022 at 11:46:35PM +0000, Mike Leach wrote: > > Add in functionality and binary attribute to load and unload > > configurations as binary data. > > > > Files are loaded via the 'load' binary attribute. System reads the incoming > > file, which must be formatted correctly as defined in the file reader code. > > This will create configuration(s) and/or feature(s) and load them > > into the system. > > Binary attributes are intended to pass things such as firmware > through. Defining your own structured file format seems like a > major abuse of the configfs design. What's the advantage of this > over simply using an ioctl? The coresight configurations loaded here, represent programming of the entire coresight subsystem - possibly tens of registers (especially on the ETM), across multiple devices, in ways that are not possible using the limited parameters of the perf command line. The ETM can be programmed in ways that use counters. sequencers, and optionally interact with other components such as CTI / CTM to send conditional hardware triggers, all of which control the when and how the trace is collected. Additionally there are system trace components that might need to run at the same time - such as ELA, and other system monitors that output data on the trace bus currently being introduce by some chip designers. As such the configuration must be loaded into the coresight system as a single operation - with the individual drivers validating the requested programming, where any error will fail the configuration load. The individual drivers are also responsible for defining which device registers user configurations can use - these being limited to those that affect the scope of trace collected, with other operational functions being reserved to the drivers themselves. To achieve this a variable sized table of programming descriptors is defined, that are transferred into the individual devices. The very limited set of built in configurations - where the programming descriptors are compiled into the driver modules themselves use the same set of descriptors. however, recompiling kernel modules to program new configurations is neither scaleable, flexible or desirable - so we need a way of loading configurations at runtime. So the file structure is simple a serialisation of these descriptor tables - with a header defining the input type and overall size.. The advantage of these runtime configurations is that they can be portable - and dependent on the hardware in the system, not the kernel build version. Moreover, there are trace scenarios when we want to trace what is present, not recompile a module / kernel to achieve this, especially investigating issues on production systems. 1) using configfs to load these configurations keeps all the coresight configuration ABI in a single file system - configfs. The current builtin configurations can be viewed, enabled, and parameters configrured in the current configfs that we have upstreamed. Adding load / unload here is a logical extension of this. 2) because of the nature of configurations described above - we would need a separate device to represent the whole subsystem - in order to provide the ioctl support for loading. This device approach to managing configurations has been previously rejected by the Coresight maintainers, who suggested that configfs was the correct way to configure a complex sub-system. 3) configurations are variable in size, An ioctl command would provide a pointer to the configuration data - but the kernel would have to trust that the underlying data is correctly formed. With a configfs file write we get the buffer _and_ its size which is a good deal safer from an input perspective. 4) ioctl use would require a loader program - configfs allows load directly from the command line. I agree that ioctls certainly have there uses, especially with small, fixed size data types - but configfs is far better suited to this complex use case. Indeed the ioctl documentation suggests using configfs for configuration cases that are too complex for sysfs, when an ioctl may not be suitable. This use of binary attributes is based on the existing use of a configfs binary attribute is for the ACPI tables - the ACPI driver here takes the buffer, does some initial validation of the file size etc, then calls the inslall ./ validate ACPI routines where the table is added to an internal list of tables maintained by the kernel. These tables may well be shared by firmware - but are also used by the kernel. There appears to be nothing in the configfs documentation limiting the use of binary attributes for passing firmware, Even the sysfs docs suggest that this is an expected use but it is not a hard and fast rule if there are no alternatives. Granted in the vast majority of cases there are better alternatives. I believe that loading via configfs is the best and safest engineering solution for this particular use case. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

Re: [PATCH v5 3/6] coresight: configfs: Add in binary attributes to load files

by Mike Leach

Hi, Thanks for this - I'll fix in next set Mike On Sat, 24 Dec 2022 at 07:16, Dan Carpenter <error27(a)gmail.com> wrote: > > Hi Mike, > > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Mike-Leach/coresight-syscfg-… > base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next > patch link: https://lore.kernel.org/r/20221219234638.3661-4-mike.leach%40linaro.org > patch subject: [PATCH v5 3/6] coresight: configfs: Add in binary attributes to load files > config: arm-randconfig-m041-20221218 > compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0 > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp(a)intel.com> > | Reported-by: Dan Carpenter <error27(a)gmail.com> > > smatch warnings: > drivers/hwtracing/coresight/coresight-syscfg-configfs.c:595 cscfg_cfg_load_write() warn: possible memory leak of 'load_descs' > > vim +/load_descs +595 drivers/hwtracing/coresight/coresight-syscfg-configfs.c > > 97b8fd654556b1 Mike Leach 2022-12-19 543 static ssize_t cscfg_cfg_load_write(struct config_item *item, const void *buffer, size_t size) > 97b8fd654556b1 Mike Leach 2022-12-19 544 { > 97b8fd654556b1 Mike Leach 2022-12-19 545 struct cscfg_fs_load_descs *load_descs = 0; > 97b8fd654556b1 Mike Leach 2022-12-19 546 struct cscfg_load_owner_info *owner_info = 0; > 97b8fd654556b1 Mike Leach 2022-12-19 547 int err = 0; > 97b8fd654556b1 Mike Leach 2022-12-19 548 > 97b8fd654556b1 Mike Leach 2022-12-19 549 /* ensure we cannot simultaneously load and unload */ > 97b8fd654556b1 Mike Leach 2022-12-19 550 if (!mutex_trylock(&cfs_mutex)) > 97b8fd654556b1 Mike Leach 2022-12-19 551 return -EBUSY; > 97b8fd654556b1 Mike Leach 2022-12-19 552 > 97b8fd654556b1 Mike Leach 2022-12-19 553 /* check configfs load / unload ops are permitted */ > 97b8fd654556b1 Mike Leach 2022-12-19 554 if (!cscfg_fs_load_enabled || unload_owner_info) { > 97b8fd654556b1 Mike Leach 2022-12-19 555 err = -EBUSY; > 97b8fd654556b1 Mike Leach 2022-12-19 556 goto exit_unlock; > 97b8fd654556b1 Mike Leach 2022-12-19 557 } > 97b8fd654556b1 Mike Leach 2022-12-19 558 > 97b8fd654556b1 Mike Leach 2022-12-19 559 if (size > CSCFG_FILE_MAXSIZE) { > 97b8fd654556b1 Mike Leach 2022-12-19 560 pr_err("cscfg: Load error - Input file too large.\n"); > 97b8fd654556b1 Mike Leach 2022-12-19 561 err = -EINVAL; > 97b8fd654556b1 Mike Leach 2022-12-19 562 goto exit_unlock; > 97b8fd654556b1 Mike Leach 2022-12-19 563 } > 97b8fd654556b1 Mike Leach 2022-12-19 564 > 97b8fd654556b1 Mike Leach 2022-12-19 565 load_descs = kzalloc(sizeof(struct cscfg_fs_load_descs), GFP_KERNEL); > 97b8fd654556b1 Mike Leach 2022-12-19 566 owner_info = kzalloc(sizeof(struct cscfg_load_owner_info), GFP_KERNEL); > 97b8fd654556b1 Mike Leach 2022-12-19 567 if (!load_descs || !owner_info) { > 97b8fd654556b1 Mike Leach 2022-12-19 568 err = -ENOMEM; > 97b8fd654556b1 Mike Leach 2022-12-19 569 goto exit_memfree; > > This exit leaks (will never happen in real life though). > > 97b8fd654556b1 Mike Leach 2022-12-19 570 } > 97b8fd654556b1 Mike Leach 2022-12-19 571 > 97b8fd654556b1 Mike Leach 2022-12-19 572 owner_info->owner_handle = load_descs; > 97b8fd654556b1 Mike Leach 2022-12-19 573 owner_info->type = CSCFG_OWNER_CONFIGFS; > 97b8fd654556b1 Mike Leach 2022-12-19 574 > 97b8fd654556b1 Mike Leach 2022-12-19 575 err = cscfg_file_read_buffer(buffer, size, load_descs); > 97b8fd654556b1 Mike Leach 2022-12-19 576 if (err) { > 97b8fd654556b1 Mike Leach 2022-12-19 577 pr_err("cscfg: Load error - Failed to read input file.\n"); > 97b8fd654556b1 Mike Leach 2022-12-19 578 goto exit_memfree; > 97b8fd654556b1 Mike Leach 2022-12-19 579 } > 97b8fd654556b1 Mike Leach 2022-12-19 580 > 97b8fd654556b1 Mike Leach 2022-12-19 581 err = cscfg_load_config_sets(load_descs->config_descs, load_descs->feat_descs, owner_info); > 97b8fd654556b1 Mike Leach 2022-12-19 582 if (err) { > 97b8fd654556b1 Mike Leach 2022-12-19 583 pr_err("cscfg: Load error - Failed to load configuaration file.\n"); > 97b8fd654556b1 Mike Leach 2022-12-19 584 goto exit_memfree; > 97b8fd654556b1 Mike Leach 2022-12-19 585 } > 97b8fd654556b1 Mike Leach 2022-12-19 586 > 97b8fd654556b1 Mike Leach 2022-12-19 587 mutex_unlock(&cfs_mutex); > 97b8fd654556b1 Mike Leach 2022-12-19 588 return size; > 97b8fd654556b1 Mike Leach 2022-12-19 589 > 97b8fd654556b1 Mike Leach 2022-12-19 590 exit_memfree: > 97b8fd654556b1 Mike Leach 2022-12-19 591 cscfg_configfs_free_owner_info(owner_info); > 97b8fd654556b1 Mike Leach 2022-12-19 592 > 97b8fd654556b1 Mike Leach 2022-12-19 593 exit_unlock: > 97b8fd654556b1 Mike Leach 2022-12-19 594 mutex_unlock(&cfs_mutex); > 97b8fd654556b1 Mike Leach 2022-12-19 @595 return err; > 97b8fd654556b1 Mike Leach 2022-12-19 596 } > > -- > 0-DAY CI Kernel Test Service > https://01.org/lkp > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

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