CoreSight

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2513 discussions

Re: [PATCH v5 6/6] Documentation: coresight: docs for config load via configfs

by Mike Leach

Hi Bagas, On Wed, 21 Dec 2022 at 03:55, Bagas Sanjaya <bagasdotme(a)gmail.com> wrote: > > On Mon, Dec 19, 2022 at 11:46:38PM +0000, Mike Leach wrote: > > diff --git a/Documentation/trace/coresight/coresight-config.rst b/Documentation/trace/coresight/coresight-config.rst > > index 6d5ffa6f7347..109053eb1b93 100644 > > --- a/Documentation/trace/coresight/coresight-config.rst > > +++ b/Documentation/trace/coresight/coresight-config.rst > > @@ -141,11 +141,11 @@ Mount configfs as normal and the 'cs-syscfg' subsystem will appear:: > > $ ls /config > > cs-syscfg stp-policy > > > > -This has two sub-directories:: > > +This has two sub-directories, with the load and unload attribute files:: > > > > $ cd cs-syscfg/ > > $ ls > > - configurations features > > + configurations features load unload > > > > The system has the configuration 'autofdo' built in. It may be examined as > > follows:: > > @@ -278,9 +278,16 @@ Creating and Loading Custom Configurations > > ========================================== > > > > Custom configurations and / or features can be dynamically loaded into the > > -system by using a loadable module. > > +system by using a loadable module, or by loading a binary configuration > > +file in configfs. > > > > -An example of a custom configuration is found in ./samples/coresight. > > +Loaded configurations can use previously loaded features. The system will > > +ensure that it is not possible to unload a feature that is currently in > > +use, by enforcing the unload order as the strict reverse of the load order. > > + > > + > > +Using a Loadable Module > > +----------------------- > > > > This creates a new configuration that uses the existing built in > > strobing feature, but provides a different set of presets. > > @@ -289,6 +296,187 @@ When the module is loaded, then the configuration appears in the configfs > > file system and is selectable in the same way as the built in configuration > > described above. > > > > -Configurations can use previously loaded features. The system will ensure > > -that it is not possible to unload a feature that is currently in use, by > > -enforcing the unload order as the strict reverse of the load order. > > +The file 'coresight-cfg-sample.c' contains the configuration and module > > +initialisation code needed to create the loadable module. > > + > > +This will be built alongside the kernel modules if select in KConfig. > > What config options (CONFIG_) are required for above to work? > > > + > > +An example of a custom configuration module is found in './samples/coresight'. > > + > > +Using a Binary Configuration File > > +--------------------------------- > > + > > +The './tools/coresight' directory contains example programs to generate and > > +read and print binary configuration files. > > + > > +Building the tools creates the 'coresight-cfg-file-gen' program that will > > +generate a configuration binary 'example1.cscfg' that can be loaded into the > > +system using configfs. The configuration declared in the source file > > +'coresight-cfg-example1.c' is named 'autofdo3' - the name that will be used > > +once loaded. > > + > > +The source files 'coresight-cfg-bufw.h' and 'coresight-cfg-bufw.c' provide a > > +standard function to convert a configuration declared in 'C' into the correct > > +binary buffer format. These files can be re-used to create new custom > > +configurations. Alternatively, addition examples can be added to the > > s/addition/additional/ > > > +'coresight-cfg-file-gen' program:: > > + > > + $ ./coresight-cfg-file-gen > > + Coresight Configuration file Generator > > + > > + Generating example1 example > > + Generating example2 example > > + > > +The program 'coresight-cfg-file-read' can read back and print a configuration > > +binary. This is built using the file reader from the driver code > > +(coresight-config-file.c), which is copied over into './tools/coresight' at > > +build time.:: > > + > > + ./coresight-cfg-file-read example1.cscfg > > + CoreSight Configuration file reader > > + ============================================ > > + > > + Configuration 1 > > + Name:- autofdo3 > > + Description:- > > + Setup ETMs with strobing for autofdo > > + Supplied presets allow experimentation with mark-space ratio for various loads > > + > > + Uses 1 features:- > > + Feature-1: strobing > > + > > + Provides 4 sets of preset values, 2 presets per set > > + set[0]: 0x7d0, 0x64, > > + set[1]: 0x7d0, 0x3e8, > > + set[2]: 0x7d0, 0x1388, > > + set[3]: 0x7d0, 0x2710, > > + > > + ============================================ > > + File contains no features > > + > > +There are additional attributes in the cs-syscfg directory - load and > > +unload that can be used to load and unload configuration binary files. To > > +load, 'cat' the binary config into the load attribute:: > > + > > + $ ls /config/cs-syscfg > > + configurations features load unload > > + $ cat example1.cscfg > /config/cs-syscfg/load > > + $ ls /config/cs-syscfg/configurations/ > > + autofdo autofdo3 > > + > > +To unload, use the same file in the unload attribute:: > > + > > + $ cat example1.cscfg > /config/cs-syscfg/unload > > + ls /config/cs-syscfg/configurations/ > > + autofdo > > + > > + > > + > > +Binary Configuration File Format > > +-------------------------------- > > + > > +The file format is defined in the source file **coresight-config-file.h** > > Use single-quote for identifier names for consistency here. > > > + > > +The source reader and generator examples produce a binary of this format. > > + > > +This arrangement is reproduced below:- > > + > > +Overall File structure > > +~~~~~~~~~~~~~~~~~~~~~~ > > + > > +:: > > + > > + [cscfg_file_header] // Mandatory > > + [CONFIG_ELEM]* // Optional - multiple, defined by cscfg_file_header.nr_configs > > + [FEATURE_ELEM]* // Optional - multiple, defined by cscfg_file_header.nr_features > > + > > +File is invalid if both [CONFIG_ELEM] and [FEATURE_ELEM] are omitted. > > + > > +A file that contains only [FEATURE_ELEM] may be loaded, and the features used > > +by subsequently loaded files with [CONFIG_ELEM] elements. > > + > > +Element Name Strings > > +~~~~~~~~~~~~~~~~~~~~ > > + > > +Configuration name strings are required to consist of alphanumeric characters and '_' only. Other special characters are not permitted. > > + > > +:: > > + my_config_2 // is a valid name. > > + this-bad-config#5 // this will not work > > Instead of using code-block for name examples, what about "... For > example, foo_bar is a valid name where as foo-bar# is not."? > > > + > > +This is in order to comply with the requirements of the perf command line. > > + > > +It is recommended that Feature and Parameter names use the same convention to allow for future enhancements to the command line syntax. > > + > > +CONFIG_ELEM element > > +~~~~~~~~~~~~~~~~~~~ > > + > > +:: > > + > > + [cscfg_file_elem_header] // header length value to end of feature strings. > > + [cscfg_file_elem_str] // name of the configuration. > > + // (see element string name requirements) > > + [cscfg_file_elem_str] // description of configuration. > > + [u16 value](nr_presets) // number of defined sets presets values. > > + [u32 value](nr_total_params) // total parameters defined by all used features. > > + [u16 value](nr_feat_refs) // number of features referenced by the configuration > > + [u64 values] * (nr_presets * nr_total_params) // the preset values. > > + [cscfg_file_elem_str] * (nr_feat_refs) // names of features used in the configurations. > > + > > +FEATURE_ELEM element > > +~~~~~~~~~~~~~~~~~~~~ > > + > > +:: > > + > > + [cscfg_file_elem_header] // header length is total bytes to end of param structures. > > + [cscfg_file_elem_str] // feature name. > > + [cscfg_file_elem_str] // feature description. > > + [u32 value](match_flags) // flags to associate the feature with a device. > > + [u16 value](nr_regs) // number of registers. > > + [u16 value](nr_params) // number of parameters. > > + [cscfg_regval_desc struct] * (nr_regs) // register definitions > > + [PARAM_ELEM] * (nr_params) // parameters definitions > > + > > +PARAM_ELEM element > > +~~~~~~~~~~~~~~~~~~ > > + > > +:: > > + > > + [cscfg_file_elem_str] // parameter name. > > + [u64 value](param_value) // initial value. > > + > > +Additional definitions. > > +~~~~~~~~~~~~~~~~~~~~~~~ > > Trim trailing period for section names > > > + > > +The following structures are defined in **coresight-config-file.h** > > + > > + * **struct cscfg_file_header** : This structure contains an initial magic number, the total > > + length of the file, and the number of configurations and features in the file. > > + * **struct cscfg_file_elem_header**: This defines the total length and type of a CONFIG_ELEM > > + or a FEATURE_ELEM. > > + * **struct cscfg_file_elem_str**: This defines a string and its length. > > Again, for consistency, wrap identifier names in single-quotes. > > > + > > +The magic number in cscfg_file_header is defined as two bitfields:: > > + > > + [31:8] Fixed magic number to identify file type. > > + [7:0] Current file format version. > > + > > +The following defines determine the maximum overall file size and maximum individual > > +string size:: > > + > > + CSCFG_FILE_MAXSIZE // maximum overall file size. > > + CSCFG_FILE_STR_MAXSIZE // maximum individual string size. > > For parameter lists in elements, use bullet lists instead. > > > + > > +Load Dependencies. > > +~~~~~~~~~~~~~~~~~~ > > Trim trailing period for section names. > > + > > +Files may be unloaded only in the strict reverse order of loading. This is enforced by the > > +configuration system. > > + > > +This is to ensure that any load dependencies are maintained. > > + > > +A configuration file that contains a CONFIG_ELEM that references named features "feat_A" and "feat_B" will load only if either:- > > +a) "feat_A" and/or "feat_B" has been loaded previously, or are present as built-in / module loaded features. > > +b) "feat_A" and/or "feat_B" are declared as FEAT_ELEM in the same file as the CONFIG_ELEM. > > Separate the preceding paragraph and the list with a blank line in order > for the list to be rendered as list. > The next version will contain all the adjustments that you suggested, though rather than using single quotes, I have changed all the occurrences to consistently the double back tick to make the filenames etc fixed width font. Thanks for the review Mike > Thanks. > > -- > An old man doll... just what I always wanted! - Clara -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

Re: [PATCH v5 4/6] coresight: configfs: Modify config files to allow userspace use

by Mike Leach

I'll rework this in the next set. Thanks for the review Mike On Tue, 27 Dec 2022 at 17:10, Christoph Hellwig <hch(a)infradead.org> wrote: > > On Mon, Dec 19, 2022 at 11:46:36PM +0000, Mike Leach wrote: > > Update coresight-config.h and the coresight-config-file.c & .h > > to allow use in userspace programs. > > > > Use __KERNEL__ defines to filter out driver only structures and > > elements so that user space programs can use the descriptor structures. > > > > Abstract memory allocation in coresight-config-file.c to allow read > > file functions to be run in userspace and kernel drivers. > > That's now how kernel code is written. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

2 years, 9 months

[PATCH v16 0/2] Add support for UltraSoc System Memory Buffer

by Junhao He

Add support for UltraSoc System Memory Buffer. Change since v15: - Modify document based on Bagas and Suzuki's comments. - Link: https://lore.kernel.org/lkml/20221220092945.30722-1-hejunhao3@huawei.com/ Change since v14: - Add some helpers to the buffer and simplify dumping data according to Jonathan's comment. - Link: https://lore.kernel.org/lkml/20221123123823.27973-1-hejunhao3@huawei.com/ Change since v13: - Modify document and the patches description according to Bagas's comment. - Add dependency on config ACPI, drop redundant enable hw in smb_update_buffer(), Modify smb_purge_data() description according to Suzuki's comment. - Link: https://lore.kernel.org/lkml/20221114090316.63157-1-hejunhao3@huawei.com/ Change since v12: - Modify the code style and add "#ifdef CONFIG_ACPI" according to Jonathan's comment. - Address the comments from Yicong, included drop "buf_base"__iomem attribute, modify the "reading" type to bool and fix FIELD_PREP. - Link: https://lore.kernel.org/lkml/20221109135008.9485-1-hejunhao3@huawei.com/ Change since v11: - Modify the code style and rename the macro according to Jonathan's comment. - Link: https://lore.kernel.org/lkml/20221107130624.59886-1-hejunhao3@huawei.com/ Change since v10: - Rebase onto v6.1-rc4, included similar sysfs register accessors (as same as James's patch) - Link: https://lore.kernel.org/lkml/20221022115929.7503-1-hejunhao3@huawei.com/ Change since v9: - Update the Contact tag in SMB document. - Replace the spinlock with mutex. - Do some clean-ups in "smb_enable()" and "smb_release()". - Use classic memory mapped interface. - Link: https://lore.kernel.org/linux-arm-kernel/20220818132231.28240-1-hejunhao3@h… Change since v8: - Insert a blank line at the end of the config tag in Kconfig according to Randy's comment. - Link: https://lore.kernel.org/linux-arm-kernel/20220816131634.38195-1-hejunhao3@h… Change since v7: - Use the macros for register bit flags and numbers of resource. - Cleanup punctuation. - Update the Date tag and the KernelVersion tag in the document. - Link: https://lore.kernel.org/lkml/20220712091353.34540-1-hejunhao3@huawei.com/ Change since v6: - Modify the code style and driver description according to Suzuki's comment. - Modify configuration of "drvdata->reading", to void problems in open/read concurrency scenario. - Rename the macro of "SMB_FLOW_MASK". - Use the "handle->head" to determine the page number and offset. - Link: https://lore.kernel.org/linux-arm-kernel/20220606130223.57354-1-liuqi115@hu… Change since v5: - Address the comments from Suzuki, add some comments in SMB document, and modify configuration of "drvdata->reading", to void problems in multi-core concurrency scenario - Link: https://lore.kernel.org/linux-arm-kernel/20220416083953.52610-1-liuqi115@hu… Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - Link: https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link: https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi115@hu… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight by Mathieu's comment. - Link: https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB driver .../sysfs-bus-coresight-devices-ultra_smb | 31 + .../trace/coresight/ultrasoc-smb.rst | 83 +++ drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 648 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 125 ++++ 6 files changed, 900 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.33.0

2 years, 9 months

[PATCH v2] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR

by Junhao He

The TRCSEQRSTEVR and TRCSEQSTR registers are not implemented if the TRCIDR5.NUMSEQSTATE == 0. Skip accessing the registers in such cases. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Signed-off-by: Junhao He <hejunhao3(a)huawei.com> Reviewed-by: Mike Leach <mike.leach(a)linaro.org> Reviewed-by: Anshuman Khandual <anshuman.khandual(a)arm.com> --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1cc052979e01..77bca6932f01 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -427,8 +427,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -1634,8 +1636,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1763,8 +1767,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { -- 2.33.0

2 years, 9 months

[PATCH v3 0/3] coresight: cti: Add PM runtime call in enable_store

by James Clark

Changes since v2: * Reword first commit message and add fixes tag * Pickup Jinlong's tested-by tags ---- This should be a slight improvement on Jinlong's previous version. Now it's not possible to trigger the error message from pm_runtime_put() by calling disable twice. It's also similar to the original pre-breaking change version where pm_runtime_put() was only called if the device was actually disabled, but with one difference: Previously pm_runtime_put() was only called once for the last disable call, but because of the reference counting in pm_runtime, it should have been called once for each enable call. This meant that the clock would have never been disabled if there were ever multiple enable calls. This is now fixed. The third commit is a refactor and doesn't need to be backported. I removed one of the atomic types because it didn't appear to be required. Maybe it was added for a reason which I'm not aware of, if so it should be pretty easy to drop that change. James Clark (2): coresight: cti: Prevent negative values of enable count coresight: cti: Remove atomic type from enable_req_count Mao Jinlong (1): coresight: cti: Add PM runtime call in enable_store .../hwtracing/coresight/coresight-cti-core.c | 23 ++++++++++++------- .../hwtracing/coresight/coresight-cti-sysfs.c | 15 +++++++++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) base-commit: 88603b6dc419445847923fcb7fe5080067a30f98 -- 2.25.1

2 years, 9 months

[PATCH] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR

by Junhao He

The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. Signed-off-by: Junhao He <hejunhao3(a)huawei.com> --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 80fefaba58ee..c7a65d1524fc 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { -- 2.33.0

2 years, 9 months

Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready

by James Clark

On 09/01/2023 23:43, Yabin Cui wrote: > Otherwise, it may cause error in AXI bus and result in a kernel panic. Hi Yabin, Thanks for the fix. Do you have a reproducer for this or some more info? For example is it a regression or has it always been there? And on which platform. Thanks James > > Signed-off-by: Yabin Cui <yabinc(a)google.com> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 4 +++- > .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++--- > drivers/hwtracing/coresight/coresight-tmc.h | 2 +- > 3 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 07abf28ad725..c106d142e632 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); > DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); > DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); > > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > { > struct coresight_device *csdev = drvdata->csdev; > struct csdev_access *csa = &csdev->access; > @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) > if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { > dev_err(&csdev->dev, > "timeout while waiting for TMC to be Ready\n"); > + return -EBUSY; > } > + return 0; > } > > void tmc_flush_and_stop(struct tmc_drvdata *drvdata) > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index 867ad8bb9b0c..2da99dd41ed6 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) > etr_buf->ops->sync(etr_buf, rrp, rwp); > } > > -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > { > u32 axictl, sts; > struct etr_buf *etr_buf = drvdata->etr_buf; > + int rc = 0; > > CS_UNLOCK(drvdata->base); > > /* Wait for TMCSReady bit to be set */ > - tmc_wait_for_tmcready(drvdata); > + rc = tmc_wait_for_tmcready(drvdata); > + if (rc) { > + dev_err(&drvdata->csdev->dev, "not ready ETR isn't enabled\n"); > + CS_LOCK(drvdata->base); > + return rc; > + } > > writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); > writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); > @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > tmc_enable_hw(drvdata); > > CS_LOCK(drvdata->base); > + return rc; > } > > static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, > rc = coresight_claim_device(drvdata->csdev); > if (!rc) { > drvdata->etr_buf = etr_buf; > - __tmc_etr_enable_hw(drvdata); > + rc = __tmc_etr_enable_hw(drvdata); > + if (rc) { > + drvdata->etr_buf = NULL; > + coresight_disclaim_device(drvdata->csdev); > + tmc_etr_disable_catu(drvdata); > + } > } > > return rc; > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index 66959557cf39..01c0382a29c0 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -255,7 +255,7 @@ struct tmc_sg_table { > }; > > /* Generic functions */ > -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); > void tmc_flush_and_stop(struct tmc_drvdata *drvdata); > void tmc_enable_hw(struct tmc_drvdata *drvdata); > void tmc_disable_hw(struct tmc_drvdata *drvdata);

2 years, 9 months

[PATCH v2 0/3] coresight: cti: Add PM runtime call in enable_store

by James Clark

This should be a slight improvement on Jinlong's previous version. Now it's not possible to trigger the error message from pm_runtime_put() by calling disable twice. It's also similar to the original pre-breaking change version where pm_runtime_put() was only called if the device was actually disabled, but with one difference: Previously pm_runtime_put() was only called once for the last disable call, but because of the reference counting in pm_runtime, it should have been called once for each enable call. This meant that the clock would have never been disabled if there were ever multiple enable calls. This is now fixed. The third commit is a refactor and doesn't need to be backported. I removed one of the atomic types because it didn't appear to be required. Maybe it was added for a reason which I'm not aware of, if so it should be pretty easy to drop that change. James Clark (2): coresight: cti: Prevent negative values of enable count coresight: cti: Remove atomic type from enable_req_count Mao Jinlong (1): coresight: cti: Add PM runtime call in enable_store .../hwtracing/coresight/coresight-cti-core.c | 23 ++++++++++++------- .../hwtracing/coresight/coresight-cti-sysfs.c | 15 +++++++++--- drivers/hwtracing/coresight/coresight-cti.h | 2 +- 3 files changed, 28 insertions(+), 12 deletions(-) base-commit: c767c34740132ffc478226864a7461493cdc2413 -- 2.25.1

2 years, 9 months

Re: [PATCH v16 0/8] Coresight: Add support for TPDM and TPDA

by Suzuki K Poulose

On 06/01/2023 20:50, Trilok Soni wrote: > On 1/6/2023 1:21 AM, Mao Jinlong wrote: >> This patch series depends on patch series: >> "[v6,00/14] coresight: Add new API to allocate trace source ID values" >> https://patchwork.kernel.org/project/linux-arm-kernel/cover/20221123195010.… > > Do we know now when these patches will get revived and accepted to > unblock us? This is all reviewed, and awaiting Peter's Ack for the perf generic change. Once we have that, it will be pushed to coresight tree. Suzuki

2 years, 9 months

[PATCH v6 00/14] coresight: Add new API to allocate trace source ID values

by Mike Leach

The current method for allocating trace source ID values to sources is to use a fixed algorithm for CPU based sources of (cpu_num * 2 + 0x10). The STM is allocated ID 0x1. This fixed algorithm is used in both the CoreSight driver code, and by perf when writing the trace metadata in the AUXTRACE_INFO record. The method needs replacing as currently:- 1. It is inefficient in using available IDs. 2. Does not scale to larger systems with many cores and the algorithm has no limits so will generate invalid trace IDs for cpu number > 44. Additionally requirements to allocate additional system IDs on some systems have been seen. This patch set introduces an API that allows the allocation of trace IDs in a dynamic manner. Architecturally reserved IDs are never allocated, and the system is limited to allocating only valid IDs. Each of the current trace sources ETM3.x, ETM4.x and STM is updated to use the new API. For the ETMx.x devices IDs are allocated on certain events a) When using sysfs, an ID will be allocated on hardware enable, or a read of sysfs TRCTRACEID register and freed when the sysfs reset is written. b) When using perf, ID is allocated on during setup AUX event, and freed on event free. IDs are communicated using the AUX_OUTPUT_HW_ID packet. The ID allocator is notified when perf sessions start and stop so CPU based IDs are kept constant throughout any perf session. Note: This patchset breaks some backward compatibility for perf record and perf report. The version of the AUXTRACE_INFO has been updated to reflect the fact that the trace source IDs are generated differently. This will mean older versions of perf report cannot decode the newer file. Appies to coresight/next Changes since v5: (requested by suzuki) 1) Prefer odd ID values for system IDs to avoid overlap with legacy CPU IDs 2) Some style changes Changes since v4: 1) update to ensure that compiling after each individual patch added still works - ie. git bisect not broken through the patchset.. 2) Revision to some of the now redundant code in cs-etm (James) 3) Comments and other minor fixes requested by Suzuki. Changes since v3: 1) Fixed aarch32 build error in ETM3.x driver. Reported-by: kernel test robot <lkp(a)intel.com> Changes since v2: 1) Improved backward compatibility: (requested by James) Using the new version of perf on an old kernel will generate a usable file legacy metadata values are set by the new perf and will be used if mew ID packets are not present in the file. Using an older version of perf / simpleperf on an updated kernel may still work. The trace ID allocator has been updated to use the legacy ID values where possible, so generated file and used trace IDs will match up to the point where the legacy algorithm is broken anyway. 2) Various changes to the ID allocator and ID packet format. (suggested by Suzuki) 3) per CPU ID info in allocator now stored as atomic type to allow a passive read without taking the allocator spinlock. perf flow now allocates and releases ID values in setup_aux / free_event. Device enable and event enable use the passive read to set the allocated values. This simplifies the locking mechanisms on the perf run and fixes issues that arose with locking dependencies. Changes since v1: (after feedback & discussion with Mathieu & Suzuki). 1) API has changed. The global trace ID map is managed internally, so it is no longer passed in to the API functions. 2) perf record does not use sysfs to find the trace IDs. These are now output as AUX_OUTPUT_HW_ID events. The drivers, perf record, and perf report have been updated accordingly to generate and handle these events. Mike Leach (14): coresight: trace-id: Add API to dynamically assign Trace ID values coresight: Remove obsolete Trace ID unniqueness checks coresight: perf: traceid: Add perf ID allocation and notifiers coresight: stm: Update STM driver to use Trace ID API coresight: etm4x: Update ETM4 driver to use Trace ID API coresight: etm3x: Update ETM3 driver to use Trace ID API coresight: etmX.X: stm: Remove trace_id() callback coresight: trace id: Remove legacy get trace ID function. perf: cs-etm: Move mapping of Trace ID and cpu into helper function perf: cs-etm: Update record event to use new Trace ID protocol kernel: events: Export perf_report_aux_output_id() perf: cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet coresight: events: PERF_RECORD_AUX_OUTPUT_HW_ID used for Trace ID coresight: trace-id: Add debug & test macros to Trace ID allocation drivers/hwtracing/coresight/Makefile | 2 +- drivers/hwtracing/coresight/coresight-core.c | 45 --- .../hwtracing/coresight/coresight-etm-perf.c | 23 ++ drivers/hwtracing/coresight/coresight-etm.h | 3 +- .../coresight/coresight-etm3x-core.c | 93 +++-- .../coresight/coresight-etm3x-sysfs.c | 27 +- .../coresight/coresight-etm4x-core.c | 73 +++- .../coresight/coresight-etm4x-sysfs.c | 27 +- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/hwtracing/coresight/coresight-stm.c | 49 +-- .../hwtracing/coresight/coresight-trace-id.c | 298 ++++++++++++++++ .../hwtracing/coresight/coresight-trace-id.h | 156 +++++++++ include/linux/coresight-pmu.h | 34 +- include/linux/coresight.h | 3 - kernel/events/core.c | 1 + tools/include/linux/coresight-pmu.h | 48 ++- tools/perf/arch/arm/util/cs-etm.c | 21 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 328 +++++++++++++++--- tools/perf/util/cs-etm.h | 14 +- 20 files changed, 1024 insertions(+), 231 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.c create mode 100644 drivers/hwtracing/coresight/coresight-trace-id.h -- 2.17.1

2 years, 9 months

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