On 11 November 2016 at 08:32, Sebastian Pop <sebpop(a)gmail.com> wrote:
> Salut Matthieu,
Bon matin,
>
> I was following your patches to enable ETM support in the linux kernel
> last years, and I have just seen that you have a very nice blog on how
> to use perf record to gather execution traces.
Depending on the source you have read the information may be outdated.
Nowadays the very latest instructions can be found in the HOWTO.md on
the OpenCSD repository [1]. That documentation is maintained
regularly and is considered accurate.
[1]. https://github.com/Linaro/OpenCSD/tree/opencsd-0v003
> I am mainly interested to use this mechanism to enable collection of
> traces with "perf record -b" like Intel's Last Branch Record: this is
> used by AutoFDO in the compiler to know which code paths are hot and
> enable better inlining, register allocation, and code layout:
> http://research.google.com/pubs/pub45290.html
This looks interesting.
>
> I am interested to work with you to enable "perf record -b" on aarch64.
This is a sizeable project that will keep you occupied for a little
while :o) I am happy to give guidance and review patches. Some
people on the CoreSight mailing list (CC'ed here) are very proficient
with the CoreSight tracers and can help understand the more complex
features of the IP. I suggest CC'ing the list if/when you have
questions.
Best regards,
Mathieu
>
> Thanks,
> Sebastian
> ---------- Forwarded message ----------
> From: Yan Lin Aung <yan_lin_aung(a)yahoo.com>
> To: "coresight(a)lists.linaro.org" <coresight(a)lists.linaro.org>
> Cc:
> Date: Mon, 7 Nov 2016 03:45:45 +0000 (UTC)
> Subject: perf with CoreSight and OpenCSD on TC2 and Juno r2
> Hi Linaro Coresight Team,
>
> I came to know of "Hardware Assisted Tracing on ARM with CoreSight and OpenCSD" by Mathieu Poirier.
> In his presentation, he mentioned the reference platforms to evaluate perf with CoreSight and OpenCSD are Vexpress TC2 and Juno (Page 7 on his slide).
>
> I just checked the "HOWTO.MD" at OpenCSD github site.
> However, there is very limited info on how to get started with Vexpress TC2 and Juno.
>
> I have access to the TC2 and Juno r2 platforms.
> Please provide a rather detailed version of getting started guide to try out perf with CoreSight and OpenCSD on either TC2 or Juno r2.
Hello Yan Lin,
You are correct, the HOWTO.md on github concentrates on CoreSight and
doesn't address platform specifics - something like this would be out
of scope. I'm not exactly sure of what you are looking for in a
"getting started guide"... Both Juno and TC2 are well supported
upstream and can be booted with a mainline kernel. The choice of
bootloader and user space are entirely up to users and don't affect
the CoreSight suite nor its integration with the perf subsystem.
The fact that you have access to both platform leads me to believe you
are part of a large organisation. As such there is definitely people
around you with experience on how to set-up the platforms.
I can try to answer specific questions if you have any.
Thanks,
Mathieu
>
> Thanx.
>
> Regards,
> Yan Lin Aung
>
On 8 November 2016 at 12:27, Darius-Andrei Suciu
<dsuciu(a)cs.stonybrook.edu> wrote:
> Hello Mathieu,
Hi
>
> My name is Darius Suciu, a Phd. student at Stony Brook University.
Congratulation - a PhD is a serious endeavour.
> I am
> working on a project where I need to get tracing data from an Cortex A-9 cpu
> (I'm using an i.MX6 nitrogen max board). The Coresight architecure seems
> very complex to me.
CS is complex to anyone ramping up on it. Looking at the drivers in
the kernel tree most of the complexity comes from the integration with
perf. The drivers and the framework are pretty bare bone and the
sysFS interface very easy to understand.
> I am trying to figure out how I can read the ETB buffer
> from the kernel (without using a JTAG), and the Coresight driver seems to
> offer this functionality.
> On the comments on the Linux Coresight driver, it says it supports also PTM
> (even though the configuration seems mostly ETM specific).
In terms of configuration ETMv3 and PTM are quite similar. So far I
haven't found enough discrepancies that would mandate splitting the
ETMv3 driver.
> Could you please help me out with some questions?
Of course.
>
> Did you using the driver on a Cortex A-9 cpu ? Or do you know what changes
> are required to make it work ?
I never used CS on a cortex A9 but that is irrelevant. What is
important is the kind of tracer (ETMv3/4/PTM) that is coupled with
each CPU and we have support for all of them (except ITM). From there
you'll need to take care of the power domains, clock and the device
tree.
> Do you know if the ETB buffer configuration is the same for ETM and PTM
> architectures (can I reuse it)
ETB and the ETM/PTM are different IP blocks and don't affect each
other. The current ETB driver in the kernel tree will work with any
kind of tracer.
Mathieu
>
> Thank you for the help,
> Darius
>
Hi Linaro Coresight Team,
I came to know of "Hardware Assisted Tracing on ARM with CoreSight and OpenCSD" by Mathieu Poirier.In his presentation, he mentioned the reference platforms to evaluate perf with CoreSight and OpenCSD are Vexpress TC2 and Juno (Page 7 on his slide).
I just checked the "HOWTO.MD" at OpenCSD github site.However, there is very limited info on how to get started with Vexpress TC2 and Juno.
I have access to the TC2 and Juno r2 platforms.Please provide a rather detailed version of getting started guide to try out perf with CoreSight and OpenCSD on either TC2 or Juno r2.
Thanx.
Regards,Yan Lin Aung
On 15 October 2016 at 17:03, Miki Shifman <mikish(a)gmail.com> wrote:
> Great, thanks!
> Does Raspberry PI 2/3 also support CoreSight? And if it is, Does a DT exists
> for it? (They're based on BCM2836 that contains Cortex-A7/BCM2837 that
> contains Cortex-A53 respectively).
All "A" class processor have coresight support. I haven't worked with
the RPi 2/3 but I know Broadcom isn't very forthcoming with the device
addresses and power domain configuration. The debug power domain may
already be enabled... but it's doubtful.
>
>
> On Oct 15, 2016 10:57 PM, "Mathieu Poirier" <mathieu.poirier(a)linaro.org>
> wrote:
>>
>> On 15 October 2016 at 10:58, Miki Shifman <mikish(a)gmail.com> wrote:
>> > Thanks a lot!
>> > Just to make sure - Does the 410c like in that link contains CoreSight
>> > HW
>> > out of the box?
>>
>> Yes, that's the one.
>>
>> I can't say it's "out of the box" but pretty close. If it doesn't
>> work on mainline Chunyan can tell you the patches/branch she used.
>>
>> Mathieu
>>
>> >
>> > On Fri, Oct 14, 2016 at 8:17 PM, Mathieu Poirier
>> > <mathieu.poirier(a)linaro.org> wrote:
>> >>
>> >> Hello Miki,
>> >>
>> >> On 14 October 2016 at 03:59, Miki Shifman <mikish(a)gmail.com> wrote:
>> >> > Hi Mathieu,
>> >> >
>> >> > I'm been reading your tutorials about CoreSight and they're all very
>> >> > interesting! I would appreciate your assistance with issues I have
>> >> > with
>> >> > it.
>> >> >
>> >> > I'm trying to learn how to use CoreSight, and currently I don't have
>> >> > an
>> >> > ARM
>> >> > board supporting it, so i'm attempting to build a linux on qemu to
>> >> > use
>> >> > your
>> >> > libraries.
>> >>
>> >> I have never heard about Coresight IP blocks being emulated on qemu -
>> >> I'm not even sure it would be possible to do so.
>> >>
>> >> >
>> >> > I've built linaro kernel 16.09 (latest) with CoreSight support. When
>> >> > I'm
>> >> > running qemu, I have sys/kernel/debug/coresight directory, but no
>> >> > devices in
>> >> > it, so I guess haven't been registered probably
>> >>
>> >> Right, that's because coresight entries aren't in the DT and as I said
>> >> above, coresight blocks aren't emulated.
>> >>
>> >> I've heard of people thinking about providing an emulation but that
>> >> would cause serious performance problems, at least from where I stand.
>> >>
>> >> Your best bet is to get one of the 96 board development kit, the 410c
>> >> is probably best, and work with that. Of all the boards available
>> >> it's likely the easiest to work with (note that I haven't tried
>> >> myself). If you do end up acquiring a system Chunyan Zhang can help
>> >> you with the DT specification.
>> >>
>> >> Best of luck,
>> >> Mathieu
>> >>
>> >> >
>> >> > Is there any flag I should add to qemu execution to support
>> >> > CoreSight?
>> >> > maybe
>> >> > add some device?
>> >> >
>> >> > Thanking you in advance,
>> >> > Miki
>> >
>> >
Hello Miki,
On 14 October 2016 at 03:59, Miki Shifman <mikish(a)gmail.com> wrote:
> Hi Mathieu,
>
> I'm been reading your tutorials about CoreSight and they're all very
> interesting! I would appreciate your assistance with issues I have with it.
>
> I'm trying to learn how to use CoreSight, and currently I don't have an ARM
> board supporting it, so i'm attempting to build a linux on qemu to use your
> libraries.
I have never heard about Coresight IP blocks being emulated on qemu -
I'm not even sure it would be possible to do so.
>
> I've built linaro kernel 16.09 (latest) with CoreSight support. When I'm
> running qemu, I have sys/kernel/debug/coresight directory, but no devices in
> it, so I guess haven't been registered probably
Right, that's because coresight entries aren't in the DT and as I said
above, coresight blocks aren't emulated.
I've heard of people thinking about providing an emulation but that
would cause serious performance problems, at least from where I stand.
Your best bet is to get one of the 96 board development kit, the 410c
is probably best, and work with that. Of all the boards available
it's likely the easiest to work with (note that I haven't tried
myself). If you do end up acquiring a system Chunyan Zhang can help
you with the DT specification.
Best of luck,
Mathieu
>
> Is there any flag I should add to qemu execution to support CoreSight? maybe
> add some device?
>
> Thanking you in advance,
> Miki
On 10 October 2016 at 10:52, liubowen (A) <liubowen2(a)huawei.com> wrote:
> Hi Mathieu:
>
>
>
> I am bob. ^_^
Indeed
>
>
>
> I am still stuck in the process of reporting. And I change to version
> 4.8 and follow the newest HOWTO.md, but still get the error “Segmentation
> fault (core dumped)” when reporting the perf.data.
When asking questions like that CC the coresight mailing list (as I
did here) - that way other people can help you.
So, you've been working on this for weeks now without meaningful
progress. This is a user space problem that has nothing to do with
the trace acquisition on the target platform. Since you have all the
source have you instrumented the code to see where the code dump
happens? Knowing exactly where the fault happens will tell you about
the nature of the problem and maybe to fix it yourself!
Since you can decode the example sample then something is different in
the trace data you generate. That doesn't mean it is wrong, it just
means it is different. That is why you need to instrument the code to
see what is happening.
>
>
>
> However the demo offered by you can be reported. It is very strange. And
> I cannot find a better solution to solve this problem,
>
>
>
> I am eager for your help.
>
>
>
> Here, I offer some information about I am working. Firstly, I work based
> on such as perf-opencsd-4.7. In order to run well on my platform similar to
> D02 made from hisilicon, I change some files under ./drivers/irqchip. Then,
> the coresight can work and the trace data can be written into perf.data.
> Then, we should install opencsd on x86 machine, here, can we report the
> perf.data on aarch64 machine? On the other hand, suppose that I get the
> mainline kernel version 4.7, and make a Image which will be used on the
> platform, and the coresight should work well, so is it not necessary to make
> a Image from such as perf-opencsd-4.7?
>
>
>
> If you are convenient, we can offer you a platform I am working on. And
> we can work together to make it come true. Of course you are very convenient
> on condition.
Unfortunately I don't have the bandwidth to work on your board. On
the flip side I can try to decode the your trace data in my
environment. Send me the files and the perf command line and I'll see
what I can do - but again I have very limited bandwidth.
Note that I won't try anything until you actually tell me the exact
line the code crashes - you have to do the investigation.
>
>
>
> Thanks very much for your time as usual! I am appreciated for whatever
> you have done.
>
>
>
> Best regards
>
>
>
> bob
>
>