On Monday 10 March 2014 17:09:22 Andrew Bradford wrote:
On 03/10/2014 04:21 PM, Grant Grundler wrote:
On Mon, Mar 10, 2014 at 10:52 AM, Andrew Bradford andrew@bradfordembedded.com wrote:
Doing open-au tests nets no useful data, it's always fast, so just a few examples at the bottom.
Any chance this test was bottleneck on the SDIO interface link speed?
Could very well be. Was tested with a reader that does not support faster than 50 MHz data rate connected via PCMCIA.
But I would expect that at high "open-au-nr" the controller would eventually become the bottleneck and drop speeds to kB/s levels, which didn't seem to happen. I was able to start an --open-au-nr=31 test (which takes quite a while and so I gave up as I'm impatient and was running on battery) with performance the same as the --open-au-nr=7 tests. So either I've gotten the erase block size very wrong, I'm doing something else bone-headed, or the controller is quite good.
I'm pretty sure it's the last of these. Samsung has in the past used sophisticated controller chips with this behavior. It's essentially what you'd find in a decent eMMC. The likely tradeoff is that a controller can get good random write performance out of cheap flash but needs more embedded RAM to manage it, and performance will degrade with fragmentation, whereas a classic SD card controller (or low-end eMMC) needs very little memory and starts out slow but does not get slower with fragmentation.
flashbench is not good at analysing this kind of device. I've tried to get behind it, but I could not understand exactly what the controller does.
Arnd