Please find below the meeting minutes for the last call. (all project documentation, meeting notes and slides, reference material can be found on the DTE portal https://collaborate.linaro.org/display/DTE)

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François-Frédéric Ozog (Linaro) -

Joakim Bech (Linaro) -

Atish Patra (Western Digital) -

Loic Pallardy (ST) -

Matthias Brugger -

Ilias Apalodimas (Linaro) -

Don (Harbin?) -

CVS -

Simon Glass (Google) -

Bill Mills (Linaro) -

Mark Brown (Arm) -

Mike Holmes (Linaro) -

Poonam (NXP) -

Ruchika Gupta (Linaro) -

Etienne Carriere (ST) -

Stefano Stabellini (Xilinx)

Notes:

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Linaro slides https://docs.google.com/presentation/d/1iCi8i7zAfYrXEXmQ0DfGB8DT3nPksX7zFJ7TbxRilo8/edit?ts=5f463d1d#slide=id.g7ddd37b719_1_67 for 9th September meeting -

Atish presentation on Risc-V boot process -

SBI - Supervisor Binary Interface -

Side note: -

Privilege level defines what the running software can do during its execution. Common usage of each privilege level is as follows: -

U-mode: user processes -

S-mode: kernel (including kernel modules and device drivers), hypervisor -

M-mode: bootloader, firmware -

SBI call looks like SMC call -

Actually SMC or HVC ? -

OpenSBI: Open source implementation of the RISC-V SBI specification (BSD-2 clause). -

RISC-V Boot flow -

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OpenSBI here is equivalent to TF-A in the Arm world, however, there is no security implemented at this point. -

The Linux kernel is booted by a single hardware thread identified by HART ID (HART = HARdware Thread) -

Then Linux can bring up other cores with HART SBI State Management (~ PSCI) -

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DT stuff -

Generate DT from RTL -

HART ID of boot core needs to be in chosen node -

Reuses topology DT node as defined by Arm64 -

Still work to do on standard IRQ controllers -

Platform level interrupt controller PLIC is SiFive specific -

Core Level Interrupt Controller (CLINT) -

Future -

Grub support -

EBBR compliance -

LinuxBoot support (was discussed last year but no more activity) -

SecureBoot (still drafting)