On Thu, Aug 20, 2020 at 1:45 AM Heinrich Schuchardt xypron.glpk@gmx.de wrote:
On 20.08.20 08:45, Ard Biesheuvel wrote:
(+ Grant, Francois)
On Thu, 20 Aug 2020 at 02:04, Atish Patra atishp@atishpatra.org wrote:
Hi All, We are interested in adopting EBBR as the boot specification for the embedded RISC-V platforms. We firmly believe that EBBR is a very well defined specification for boot requirement and there is no need for reinventing the wheel for RISC-V. Hence, this is a thread to discuss all the requirements for adding RISC-V to EBBR. Here is my current understanding. Please correct me if I am wrong.
Logistic Requirement:
- As per the contribution guidelines[1], patches should be sent to
boot-architecture@lists.linaro.org. and the specification will be hosted under "ARM-software" Github. I am hoping that introducing RISC-V related changes are okay with the current maintainers. 2. The specification is licensed under Creative Commons. The RISC-V related changes will refer to some of the RISC-V specifications as well. AFAIK, there shouldn't be an issue with that. 3. It should be okay to add other copyrights in addition to "Arm Limited and Contributors".
Technical Requirement:
- Software status: a. UEFI support for RISC-V Linux kernel is already available in
the mailing list[2]. The targeted upstream merge is the 5.10 merge window. b. U-Boot already supports UEFI for RISC-V. c. EDK2 upstreaming is currently under progress [3] as well.
Is it okay to start sending patches for EBBR RISC-V related changes now or do we need to wait for EDK2 and Linux kernel patches to be available upstream ?
- RISC-V related sections in EBBR a. UEFI: Currently, RISC-V doesn't support a EFI_RESET_SYSTEM boot
service as firmware doesn't have a standard way to reset the system. There is a proposal to add a system reset function to Supervisor Binary Specification(SBI) which can be mapped to EFI_RESET_SYSTEM by the firmware. Apart from that, I believe RISC-V supports all UEFI boot and run time services mandated by EBBR. Is it a blocker for RISC-V EBBR compatibility?
EFI_RESET_SYSTEM is a runtime service. To achieve compliance EBBR https://github.com/ARM-software/ebbr/blob/master/source/chapter2-uefi.rst requires to implement it at least before ExitBootServices().
The EBBR describes per board requirements for the implementation of the UEFI API, not requirements on prior firmware stages like SBI and TF-A.
Even if the SBI specification does not have a general service for implementing reset in a hardware agnostic way this does not stop per board implementation.
The idea of SBI Reset specification was to come up with a standard way of system reset to avoid per board implementation and emulation in hypervisors.
In U-Boot all boards implementing the U-Boot reset command also provide the ResetSystem() service before ExitBootServices(), e.g. the Kendryte K210 based Sipeed Maixduino board.
b. RISC-V Multiprocessor Startup Protocol: This section willcontain the details of booting protocol for RISC-V and mandatory RISC-V specifications that need to be implemented.
I guess this will include
- passing of booting hart and device-tree to next stage
- privilege levels
Yes. Few others such as SBI HSM extension. I guess it will just probably point to the booting section of RISC-V Platform specification or other way around.
Best regards
Heinrich
c. Firmware Storage: AFAIK, RISC-V platforms are alreadycompatible with this.
Please let me know if I missed something or oversimplified any requirement. We want to make RISC-V compatible with EBBR sooner than later and ready work on any missing pieces if any.
[1] https://github.com/ARM-software/ebbr/blob/master/CONTRIBUTING.rst [2] https://lkml.org/lkml/2020/8/19/1252 [3]
https://edk2.groups.io/g/devel/message/63831?p=,,,20,0,0,0::Created,,RISC-V,...
[4]
https://lists.riscv.org/g/tech-unixplatformspec/message/49?p=,,,20,0,0,0::re...
-- Regards, Atish