This patch adds all the required content to make RISC-V EBBR compatible. The additional content is not a lot given that we just need to update the architecture specific sections for RISC-V. Rest of the document is ISA agnostic anyways.
Signed-off-by: Atish Patra atish.patra@wdc.com --- source/chapter1-about.rst | 86 +++++++++++++++++++++++------ source/chapter2-uefi.rst | 41 +++++++++++++- source/chapter3-secureworld.rst | 12 ++++ source/images/riscv-sbi-intro1.png | Bin 0 -> 11926 bytes source/images/riscv-sbi-intro2.png | Bin 0 -> 23280 bytes source/index.rst | 3 + source/references.rst | 6 ++ 7 files changed, 130 insertions(+), 18 deletions(-) create mode 100644 source/images/riscv-sbi-intro1.png create mode 100644 source/images/riscv-sbi-intro2.png
diff --git a/source/chapter1-about.rst b/source/chapter1-about.rst index 52e61e80b7f9..5097e85ea648 100644 --- a/source/chapter1-about.rst +++ b/source/chapter1-about.rst @@ -158,6 +158,8 @@ easily meet the stricter BBR requirements. By definition, all BBR compliant systems are also EBBR compliant, but the converse is not true.
+This specification is also referenced by RISC-V platform specification [RVPLTSPEC]_. + Conventions Used in this Document =================================
@@ -181,14 +183,12 @@ This document uses the following terms and abbreviations.
.. glossary::
+AARCH64 +------- A64 The 64-bit Arm instruction set used in AArch64 state. All A64 instructions are 32 bits.
- AArch32 - Arm 32-bit architectures. AArch32 is a roll up term referring to all - 32-bit versions of the Arm architecture starting at ARMv4. - AArch64 state The Arm 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), Stack Pointer (SP), and @@ -197,10 +197,6 @@ This document uses the following terms and abbreviations. AArch64 Execution state provides a single instruction set, A64.
- EFI Loaded Image - An executable image to be run under the UEFI environment, - and which uses boot time services. - EL0 The lowest Exception level on AArch64. The Exception level that is used to execute user applications, in Non-secure state. @@ -218,17 +214,59 @@ This document uses the following terms and abbreviations. execute Secure Monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.
- Logical Unit (LU) - A logical unit (LU) is an externally addressable, independent entity - within a device. In the context of storage, a single device may use - logical units to provide multiple independent storage areas. +ARM +--- + AArch32 + Arm 32-bit architectures. AArch32 is a roll up term referring to all + 32-bit versions of the Arm architecture starting at ARMv4.
- OEM - Original Equipment Manufacturer. In this document, the final device - manufacturer. +RISC-V +------ + HART + Hardware thread in RISC-V. This is the hardware execution context that contains + all the state mandated by the ISA.
- SiP - Silicon Partner. In this document, the silicon manufacturer. + HSM + Hart State Management (HSM) is an SBI extension that enables the supervisor + mode software to implement ordered booting. + + HS Mode + Hypervisor-extended-supervisor mode which virtualizes the supervisor mode. + + M Mode + Machine mode is the most secure and privileged mode in RISC-V. + + RISC-V + An open standard Instruction Set Architecture (ISA) based on + Reduced Instruction Set Architecture (RISC). + + RV32 + 32 bit execution mode in RISC-V. + + RV64 + 64 bit execution mode in RISC-V. + + RISC-V Supervisor Binary Interface (SBI) + Supervisor Binary Interface. This is an interface between SEE and supervisor + mode in RISC-V. + + SEE + Supervisor Execution Environment in RISC-V. This can be M mode or HS mode. + + S Mode + Supervisor mode is the next privilege mode after M mode where virtual memory is enabled. + + U Mode + User mode is the least privilege mode where user-space application is expected to run. + + VS Mode + Virtulized supervisor mode where the guest OS is expected run when hypervisor is enabled. + +UEFI +---- + EFI Loaded Image + An executable image to be run under the UEFI environment, + and which uses boot time services.
UEFI Unified Extensible Firmware Interface. @@ -240,3 +278,17 @@ This document uses the following terms and abbreviations. UEFI Runtime Services Functionality that is provided to an Operating System after the ExitBootServices() call. + +Miscellaneous +------------- + Logical Unit (LU) + A logical unit (LU) is an externally addressable, independent entity + within a device. In the context of storage, a single device may use + logical units to provide multiple independent storage areas. + + OEM + Original Equipment Manufacturer. In this document, the final device + manufacturer. + + SiP + Silicon Partner. In this document, the silicon manufacturer. diff --git a/source/chapter2-uefi.rst b/source/chapter2-uefi.rst index 53c962ab5c25..18a9b5404cba 100644 --- a/source/chapter2-uefi.rst +++ b/source/chapter2-uefi.rst @@ -209,7 +209,7 @@ Resident UEFI firmware might target a specific privilege level. In contrast, UEFI Loaded Images, such as third-party drivers and boot applications, must not contain any built-in assumptions that they are to be loaded at a given privilege level during boot time since they can, for example, -legitimately be loaded into either EL1 or EL2 on AArch64. +legitimately be loaded into either EL1 or EL2 on AArch64 and HS/VS/S mode on RISC-V.
AArch64 Exception Levels ------------------------ @@ -232,6 +232,45 @@ UEFI-compliant Operating System. In this instance, the UEFI boot-time environment can be provided, as a virtualized service, by the hypervisor and not as part of the host firmware.
+RISC-V Privilege Levels +----------------------- + +Unlike AARCH64, RISC-V doesn't define dedicated privilege levels for hypervisor +enabled platforms. The supervisor mode becomes HS mode where a hypervisor or a hosting-capable +operating system runs while the guest OS runs in virtual S mode (VS mode) as shown in below figures. +Resident UEFI firmware can be executed in M mode or S/HS mode during POST. However, +the UEFI images must be loaded in HS or VS mode if virtualization is available at OS load time. + +.. image:: images/riscv-sbi-intro1.png + :align: center + +Figure1. RISC-V System without H-extension + +.. image:: images/riscv-sbi-intro2.png + :align: center + +Figure2. RISC-V System with H-extension + +UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^ + +Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state. + +UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^ + +Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System. + +UEFI Boot at VS mode +^^^^^^^^^^^^^^^^^^^^^^ + +Booting of UEFI at VS mode is employed within a hypervisor hosted Guest Operating System environment, +to allow the subsequent booting of a UEFI-compliant Operating System. +In this instance, the UEFI boot-time environment can be provided, as a +virtualized service, by the hypervisor and not as part of the host firmware. + UEFI Boot Services ==================
diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 9c51bca24f33..d6bfbd322837 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -27,3 +27,15 @@ Platforms without EL3 must implement one of: However, the spin table protocol is strongly discouraged. Future versions of this specification will only allow PSCI, and PSCI should be implemented in all new designs. + +RISC-V Multiprocessor Startup Protocol +====================================== +The resident firmware in M mode or hypervisor running in HS mode must implement +and conform to at least SBI [RVSBISPEC]_ v0.2 with HART +State Management(HSM) extension for both RV32 and RV64. In addition to that, the +firmware must ensure the following condition before jumping to the UEFI +application. + +The device tree must contain a property named **boot-hartid** under the */chosen* +node. This property must indicate the id of the booting hart. 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diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019 + Copyright Western Digital Corporation or its affiliates, 2021 SPDX-License-Identifier: CC-BY-SA-4.0
#################################################### @@ -8,6 +9,8 @@ Embedded Base Boot Requirements (EBBR) Specification
Copyright © 2017-2019 Arm Limited and Contributors.
+Copyright © 2021 Western Digital Corporation or its affiliates. + This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to diff --git a/source/references.rst b/source/references.rst index 6d09d3c0aaa7..5b777a4d032f 100644 --- a/source/references.rst +++ b/source/references.rst @@ -29,3 +29,9 @@ .. [UEFI] `Unified Extensable Firmware Interface Specification v2.8 Errata A https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_A_Feb14.pdf`_, February 2020, `UEFI Forum http://www.uefi.org`_ + +.. [RVPLTSPEC] `RISC-V Platform specification https://github.com/riscv/riscv-platform-specs`_ + +.. [RVSBISPEC] `RISC-V Supervisor Binary Interface specification https://github.com/riscv/riscv-sbi-doc`_ + +.. [RVHYPSPEC] `RISC-V ISA Hypervisor extension https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex`_
On Mon, May 10, 2021 at 10:37 AM Atish Patra atish.patra@wdc.com wrote:
This patch adds all the required content to make RISC-V EBBR compatible. The additional content is not a lot given that we just need to update the architecture specific sections for RISC-V. Rest of the document is ISA agnostic anyways.
Signed-off-by: Atish Patra atish.patra@wdc.com
source/chapter1-about.rst | 86 +++++++++++++++++++++++------ source/chapter2-uefi.rst | 41 +++++++++++++- source/chapter3-secureworld.rst | 12 ++++ source/images/riscv-sbi-intro1.png | Bin 0 -> 11926 bytes source/images/riscv-sbi-intro2.png | Bin 0 -> 23280 bytes source/index.rst | 3 + source/references.rst | 6 ++ 7 files changed, 130 insertions(+), 18 deletions(-) create mode 100644 source/images/riscv-sbi-intro1.png create mode 100644 source/images/riscv-sbi-intro2.png
diff --git a/source/chapter1-about.rst b/source/chapter1-about.rst index 52e61e80b7f9..5097e85ea648 100644 --- a/source/chapter1-about.rst +++ b/source/chapter1-about.rst @@ -158,6 +158,8 @@ easily meet the stricter BBR requirements. By definition, all BBR compliant systems are also EBBR compliant, but the converse is not true.
+This specification is also referenced by RISC-V platform specification [RVPLTSPEC]_.
Conventions Used in this Document
@@ -181,14 +183,12 @@ This document uses the following terms and abbreviations.
.. glossary::
+AARCH64 +------- A64 The 64-bit Arm instruction set used in AArch64 state. All A64 instructions are 32 bits.
- AArch32
Arm 32-bit architectures. AArch32 is a roll up term referring to all
32-bit versions of the Arm architecture starting at ARMv4.
- AArch64 state The Arm 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), Stack Pointer (SP), and
@@ -197,10 +197,6 @@ This document uses the following terms and abbreviations. AArch64 Execution state provides a single instruction set, A64.
- EFI Loaded Image
An executable image to be run under the UEFI environment,
and which uses boot time services.
- EL0 The lowest Exception level on AArch64. The Exception level that is used to execute user applications, in Non-secure state.
@@ -218,17 +214,59 @@ This document uses the following terms and abbreviations. execute Secure Monitor code, which handles the transitions between Non-secure and Secure states. EL3 is always in Secure state.
- Logical Unit (LU)
A logical unit (LU) is an externally addressable, independent entity
within a device. In the context of storage, a single device may use
logical units to provide multiple independent storage areas.
+ARM +---
- AArch32
Arm 32-bit architectures. AArch32 is a roll up term referring to all
32-bit versions of the Arm architecture starting at ARMv4.
- OEM
Original Equipment Manufacturer. In this document, the final device
manufacturer.
+RISC-V +------
- HART
Hardware thread in RISC-V. This is the hardware execution context that contains
all the state mandated by the ISA.
- SiP
Silicon Partner. In this document, the silicon manufacturer.
- HSM
Hart State Management (HSM) is an SBI extension that enables the supervisor
mode software to implement ordered booting.
- HS Mode
Hypervisor-extended-supervisor mode which virtualizes the supervisor mode.
- M Mode
Machine mode is the most secure and privileged mode in RISC-V.
- RISC-V
An open standard Instruction Set Architecture (ISA) based on
Reduced Instruction Set Architecture (RISC).
- RV32
32 bit execution mode in RISC-V.
- RV64
64 bit execution mode in RISC-V.
- RISC-V Supervisor Binary Interface (SBI)
Supervisor Binary Interface. This is an interface between SEE and supervisor
mode in RISC-V.
- SEE
Supervisor Execution Environment in RISC-V. This can be M mode or HS mode.
- S Mode
Supervisor mode is the next privilege mode after M mode where virtual memory is enabled.
- U Mode
User mode is the least privilege mode where user-space application is expected to run.
- VS Mode
Virtulized supervisor mode where the guest OS is expected run when hypervisor is enabled.
+UEFI +----
EFI Loaded Image
An executable image to be run under the UEFI environment,
and which uses boot time services.
UEFI Unified Extensible Firmware Interface.
@@ -240,3 +278,17 @@ This document uses the following terms and abbreviations. UEFI Runtime Services Functionality that is provided to an Operating System after the ExitBootServices() call.
+Miscellaneous +-------------
- Logical Unit (LU)
A logical unit (LU) is an externally addressable, independent entity
within a device. In the context of storage, a single device may use
logical units to provide multiple independent storage areas.
- OEM
Original Equipment Manufacturer. In this document, the final device
manufacturer.
- SiP
Silicon Partner. In this document, the silicon manufacturer.
diff --git a/source/chapter2-uefi.rst b/source/chapter2-uefi.rst index 53c962ab5c25..18a9b5404cba 100644 --- a/source/chapter2-uefi.rst +++ b/source/chapter2-uefi.rst @@ -209,7 +209,7 @@ Resident UEFI firmware might target a specific privilege level. In contrast, UEFI Loaded Images, such as third-party drivers and boot applications, must not contain any built-in assumptions that they are to be loaded at a given privilege level during boot time since they can, for example, -legitimately be loaded into either EL1 or EL2 on AArch64. +legitimately be loaded into either EL1 or EL2 on AArch64 and HS/VS/S mode on RISC-V.
AArch64 Exception Levels
@@ -232,6 +232,45 @@ UEFI-compliant Operating System. In this instance, the UEFI boot-time environment can be provided, as a virtualized service, by the hypervisor and not as part of the host firmware.
+RISC-V Privilege Levels +-----------------------
+Unlike AARCH64, RISC-V doesn't define dedicated privilege levels for hypervisor +enabled platforms. The supervisor mode becomes HS mode where a hypervisor or a hosting-capable +operating system runs while the guest OS runs in virtual S mode (VS mode) as shown in below figures. +Resident UEFI firmware can be executed in M mode or S/HS mode during POST. However, +the UEFI images must be loaded in HS or VS mode if virtualization is available at OS load time.
+.. image:: images/riscv-sbi-intro1.png
- :align: center
+Figure1. RISC-V System without H-extension
+.. image:: images/riscv-sbi-intro2.png
- :align: center
+Figure2. RISC-V System with H-extension
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
+UEFI Boot at VS mode +^^^^^^^^^^^^^^^^^^^^^^
+Booting of UEFI at VS mode is employed within a hypervisor hosted Guest Operating System environment, +to allow the subsequent booting of a UEFI-compliant Operating System. +In this instance, the UEFI boot-time environment can be provided, as a +virtualized service, by the hypervisor and not as part of the host firmware.
UEFI Boot Services
diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 9c51bca24f33..d6bfbd322837 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -27,3 +27,15 @@ Platforms without EL3 must implement one of: However, the spin table protocol is strongly discouraged. Future versions of this specification will only allow PSCI, and PSCI should be implemented in all new designs.
+RISC-V Multiprocessor Startup Protocol +====================================== +The resident firmware in M mode or hypervisor running in HS mode must implement +and conform to at least SBI [RVSBISPEC]_ v0.2 with HART +State Management(HSM) extension for both RV32 and RV64. In addition to that, the +firmware must ensure the following condition before jumping to the UEFI +application.
+The device tree must contain a property named **boot-hartid** under the */chosen* +node. This property must indicate the id of the booting hart. The corresponding entry +in the ACPI tables has not been defined yet as ACPI support in RISC-V is under progress. diff --git a/source/images/riscv-sbi-intro1.png b/source/images/riscv-sbi-intro1.png new file mode 100644 index 0000000000000000000000000000000000000000..953e6529912af2e5b774ec6033abd856262651fe GIT binary patch literal 11926 zcmeI2bySq?*Y8IqRYE`{1e6#+N@@@!q$P$%q!r1bBnPAvL68t(2<h&WE<q$DMH+^Z zk_Kspe6R8OJ<t0*=l7no&imhc);cT}_nMpgy61|0?fu=KYrj=fkte!La~T4G5Gg#A z(SSfMnm`~IE)!e?cf>u4Xdw`8Lj@U0EjOd}#4B!ELp29F(3p->sjHT^5VvL+rQYMQ zU#RI|uLv^XoMK~GY0|TeDt`2!;QBSSLB`8b`W!KuMZUPWmnxDT-wt}RPRL4dD$~+8 z`jYe}0gf-B=VqMH*qE-zzWE}IKNfSIbdItpM1DGsOFU>CNlKJ40G)umB$Oh;UQ>ui znZf0W;wN|#KK4HTAD=JVkbzHkabbku^5J4U4!9`4f@24e^%;5rTr{7cz~7hbB?{p3 znc{zXGkrgnOt2sXt{R$}L)$mDKSOOLbyPbgxF3+>;8x`f*Gz5%1qF3>cIM^ft*js_ zXx`A5DCmEN-X^$=t6u0-V_;@xwy>~Z8a*G05WFh(1XcMGE=5XlIZaPTL&NdM=U4sx z8jgx_nt4NacVEKM7h!~wYHWcBLv?j^2M1nZmL7I1soY1+-!H+eu8cC{NT%M(bHT;M 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diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021 SPDX-License-Identifier: CC-BY-SA-4.0
#################################################### @@ -8,6 +9,8 @@ Embedded Base Boot Requirements (EBBR) Specification
Copyright © 2017-2019 Arm Limited and Contributors.
+Copyright © 2021 Western Digital Corporation or its affiliates.
This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to diff --git a/source/references.rst b/source/references.rst index 6d09d3c0aaa7..5b777a4d032f 100644 --- a/source/references.rst +++ b/source/references.rst @@ -29,3 +29,9 @@ .. [UEFI] `Unified Extensable Firmware Interface Specification v2.8 Errata A https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_A_Feb14.pdf`_, February 2020, `UEFI Forum http://www.uefi.org`_
+.. [RVPLTSPEC] `RISC-V Platform specification https://github.com/riscv/riscv-platform-specs`_
+.. [RVSBISPEC] `RISC-V Supervisor Binary Interface specification https://github.com/riscv/riscv-sbi-doc`_
+.. [RVHYPSPEC] `RISC-V ISA Hypervisor extension https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex`_
2.30.1
boot-architecture mailing list boot-architecture@lists.linaro.org https://lists.linaro.org/mailman/listinfo/boot-architecture
Any comments ?
On 10/05/2021 18:37, Atish Patra wrote:
This patch adds all the required content to make RISC-V EBBR compatible. The additional content is not a lot given that we just need to update the architecture specific sections for RISC-V. Rest of the document is ISA agnostic anyways.
Signed-off-by: Atish Patra atish.patra@wdc.com
Hi Atish,
I'm picking up this patch. There are some editorial changes that I'm making (line breaks, glossary organization, etc), but I don't need you to respin the patch. However, I have some comments questions before I push the result out.
--- a/source/chapter1-about.rst +++ b/source/chapter1-about.rst @@ -158,6 +158,8 @@ easily meet the stricter BBR requirements. By definition, all BBR compliant systems are also EBBR compliant, but the converse is not true.
+This specification is also referenced by RISC-V platform specification [RVPLTSPEC]_.
s/also //
I've dropped text that references RISC-V in comparison to ARM. The RISC-V wording is able to stand on it's own without reference. :-)
Conventions Used in this Document
@@ -181,14 +183,12 @@ This document uses the following terms and abbreviations.
.. glossary::
[...]
- SiP
Silicon Partner. In this document, the silicon manufacturer.
I've rearranged the glossary to put the generic terms at the top, and the architecture specifics below that. Also minor editorial so that all the terms are handled as glossary. (.. glossary:: is needed in each section)
diff --git a/source/chapter2-uefi.rst b/source/chapter2-uefi.rst index 53c962ab5c25..18a9b5404cba 100644 --- a/source/chapter2-uefi.rst +++ b/source/chapter2-uefi.rst @@ -209,7 +209,7 @@ Resident UEFI firmware might target a specific privilege level. In contrast, UEFI Loaded Images, such as third-party drivers and boot applications, must not contain any built-in assumptions that they are to be loaded at a given privilege level during boot time since they can, for example, -legitimately be loaded into either EL1 or EL2 on AArch64. +legitimately be loaded into either EL1 or EL2 on AArch64 and HS/VS/S mode on RISC-V.
AArch64 Exception Levels
@@ -232,6 +232,45 @@ UEFI-compliant Operating System. In this instance, the UEFI boot-time environment can be provided, as a virtualized service, by the hypervisor and not as part of the host firmware.
+RISC-V Privilege Levels +-----------------------
+Unlike AARCH64, RISC-V doesn't define dedicated privilege levels for hypervisor
s/Unlike AARCH64, //
+enabled platforms. The supervisor mode becomes HS mode where a hypervisor or a hosting-capable +operating system runs while the guest OS runs in virtual S mode (VS mode) as shown in below figures. +Resident UEFI firmware can be executed in M mode or S/HS mode during POST. However, +the UEFI images must be loaded in HS or VS mode if virtualization is available at OS load time.
editorial: I've reflowed most paragraphs to use semantic breaks (e.g., one sentence per line). It reduces the reflow changebars on future edits to the text.
+.. image:: images/riscv-sbi-intro1.png
- :align: center
+Figure1. RISC-V System without H-extension
+.. image:: images/riscv-sbi-intro2.png
- :align: center
+Figure2. RISC-V System with H-extension
I've dropped the images; I don't think they're necessary for spec language, but this can be debated.
In the mean time it doesn't have to hold up the rest of the changes.
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
+UEFI Boot at VS mode +^^^^^^^^^^^^^^^^^^^^^^
+Booting of UEFI at VS mode is employed within a hypervisor hosted Guest Operating System environment, +to allow the subsequent booting of a UEFI-compliant Operating System. +In this instance, the UEFI boot-time environment can be provided, as a +virtualized service, by the hypervisor and not as part of the host firmware.
UEFI Boot Services
diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 9c51bca24f33..d6bfbd322837 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -27,3 +27,15 @@ Platforms without EL3 must implement one of: However, the spin table protocol is strongly discouraged. Future versions of this specification will only allow PSCI, and PSCI should be implemented in all new designs.
+RISC-V Multiprocessor Startup Protocol +====================================== +The resident firmware in M mode or hypervisor running in HS mode must implement +and conform to at least SBI [RVSBISPEC]_ v0.2 with HART +State Management(HSM) extension for both RV32 and RV64. In addition to that, the +firmware must ensure the following condition before jumping to the UEFI +application.
+The device tree must contain a property named **boot-hartid** under the */chosen* +node. This property must indicate the id of the booting hart. The corresponding entry +in the ACPI tables has not been defined yet as ACPI support in RISC-V is under progress.
I'm just dropping the ACPI references. If the ACPI bindings aren't defined yet, then it doesn't make sense to reference them.
diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021
I don't think this is valid for a copyright message. In fact, the Arm line above it is also wrong. It should be specific to the copyright owner without the "or its affiliates". Is it okay by you if Idrop that last bit.
I'll fix the Arm line separately
SPDX-License-Identifier: CC-BY-SA-4.0
#################################################### @@ -8,6 +9,8 @@ Embedded Base Boot Requirements (EBBR) Specification
Copyright © 2017-2019 Arm Limited and Contributors.
+Copyright © 2021 Western Digital Corporation or its affiliates.
Ditto
This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to diff --git a/source/references.rst b/source/references.rst index 6d09d3c0aaa7..5b777a4d032f 100644 --- a/source/references.rst +++ b/source/references.rst @@ -29,3 +29,9 @@ .. [UEFI] `Unified Extensable Firmware Interface Specification v2.8 Errata A https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_A_Feb14.pdf`_, February 2020, `UEFI Forum http://www.uefi.org`_
+.. [RVPLTSPEC] `RISC-V Platform specification https://github.com/riscv/riscv-platform-specs`_
+.. [RVSBISPEC] `RISC-V Supervisor Binary Interface specification https://github.com/riscv/riscv-sbi-doc`_
+.. [RVHYPSPEC] `RISC-V ISA Hypervisor extension https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex`_
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On Mon, Jun 21, 2021 at 10:19 AM Grant Likely grant.likely@arm.com wrote:
On 10/05/2021 18:37, Atish Patra wrote:
This patch adds all the required content to make RISC-V EBBR compatible. The additional content is not a lot given that we just need to update the architecture specific sections for RISC-V. Rest of the document is ISA agnostic anyways.
Signed-off-by: Atish Patra atish.patra@wdc.com
Hi Atish,
I'm picking up this patch. There are some editorial changes that I'm making (line breaks, glossary organization, etc), but I don't need you to respin the patch. However, I have some comments questions before I push the result out.
Thanks!!
--- a/source/chapter1-about.rst +++ b/source/chapter1-about.rst @@ -158,6 +158,8 @@ easily meet the stricter BBR requirements. By definition, all BBR compliant systems are also EBBR compliant, but the converse is not true.
+This specification is also referenced by RISC-V platform specification [RVPLTSPEC]_.
s/also //
I've dropped text that references RISC-V in comparison to ARM. The RISC-V wording is able to stand on it's own without reference. :-)
Sure.
Conventions Used in this Document
@@ -181,14 +183,12 @@ This document uses the following terms and abbreviations.
.. glossary::
[...]
- SiP
Silicon Partner. In this document, the silicon manufacturer.
I've rearranged the glossary to put the generic terms at the top, and the architecture specifics below that. Also minor editorial so that all the terms are handled as glossary. (.. glossary:: is needed in each section)
diff --git a/source/chapter2-uefi.rst b/source/chapter2-uefi.rst index 53c962ab5c25..18a9b5404cba 100644 --- a/source/chapter2-uefi.rst +++ b/source/chapter2-uefi.rst @@ -209,7 +209,7 @@ Resident UEFI firmware might target a specific privilege level. In contrast, UEFI Loaded Images, such as third-party drivers and boot applications, must not contain any built-in assumptions that they are to be loaded at a given privilege level during boot time since they can, for example, -legitimately be loaded into either EL1 or EL2 on AArch64. +legitimately be loaded into either EL1 or EL2 on AArch64 and HS/VS/S mode on RISC-V.
AArch64 Exception Levels
@@ -232,6 +232,45 @@ UEFI-compliant Operating System. In this instance, the UEFI boot-time environment can be provided, as a virtualized service, by the hypervisor and not as part of the host firmware.
+RISC-V Privilege Levels +-----------------------
+Unlike AARCH64, RISC-V doesn't define dedicated privilege levels for hypervisor
s/Unlike AARCH64, //
+enabled platforms. The supervisor mode becomes HS mode where a hypervisor or a hosting-capable +operating system runs while the guest OS runs in virtual S mode (VS mode) as shown in below figures. +Resident UEFI firmware can be executed in M mode or S/HS mode during POST. However, +the UEFI images must be loaded in HS or VS mode if virtualization is available at OS load time.
editorial: I've reflowed most paragraphs to use semantic breaks (e.g., one sentence per line). It reduces the reflow changebars on future edits to the text.
Sure.
+.. image:: images/riscv-sbi-intro1.png
- :align: center
+Figure1. RISC-V System without H-extension
+.. image:: images/riscv-sbi-intro2.png
- :align: center
+Figure2. RISC-V System with H-extension
I've dropped the images; I don't think they're necessary for spec language, but this can be debated.
Ok. Sure. I added them after Henerich suggested.
In the mean time it doesn't have to hold up the rest of the changes.
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
+UEFI Boot at VS mode +^^^^^^^^^^^^^^^^^^^^^^
+Booting of UEFI at VS mode is employed within a hypervisor hosted Guest Operating System environment, +to allow the subsequent booting of a UEFI-compliant Operating System. +In this instance, the UEFI boot-time environment can be provided, as a +virtualized service, by the hypervisor and not as part of the host firmware.
UEFI Boot Services
diff --git a/source/chapter3-secureworld.rst b/source/chapter3-secureworld.rst index 9c51bca24f33..d6bfbd322837 100644 --- a/source/chapter3-secureworld.rst +++ b/source/chapter3-secureworld.rst @@ -27,3 +27,15 @@ Platforms without EL3 must implement one of: However, the spin table protocol is strongly discouraged. Future versions of this specification will only allow PSCI, and PSCI should be implemented in all new designs.
+RISC-V Multiprocessor Startup Protocol +====================================== +The resident firmware in M mode or hypervisor running in HS mode must implement +and conform to at least SBI [RVSBISPEC]_ v0.2 with HART +State Management(HSM) extension for both RV32 and RV64. In addition to that, the +firmware must ensure the following condition before jumping to the UEFI +application.
+The device tree must contain a property named **boot-hartid** under the */chosen* +node. This property must indicate the id of the booting hart. The corresponding entry +in the ACPI tables has not been defined yet as ACPI support in RISC-V is under progress.
I'm just dropping the ACPI references. If the ACPI bindings aren't defined yet, then it doesn't make sense to reference them.
Sure.
diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021
I don't think this is valid for a copyright message. In fact, the Arm line above it is also wrong. It should be specific to the copyright owner without the "or its affiliates". Is it okay by you if Idrop that last bit.
That's the copyright line we got from Western Digital lawyer because Western Digital has many subsidiaries (as a result of acquisitions) In fact, our group was part of HGST until recently. We have the same copyright in other open source projects (Kernel, OpenSBI, U-Boot)
If you feel strongly about it, you can drop it. We can fix it in the future if somebody complains about it :)
I'll fix the Arm line separately
SPDX-License-Identifier: CC-BY-SA-4.0
#################################################### @@ -8,6 +9,8 @@ Embedded Base Boot Requirements (EBBR) Specification
Copyright © 2017-2019 Arm Limited and Contributors.
+Copyright © 2021 Western Digital Corporation or its affiliates.
Ditto
This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to diff --git a/source/references.rst b/source/references.rst index 6d09d3c0aaa7..5b777a4d032f 100644 --- a/source/references.rst +++ b/source/references.rst @@ -29,3 +29,9 @@ .. [UEFI] `Unified Extensable Firmware Interface Specification v2.8 Errata A https://uefi.org/sites/default/files/resources/UEFI_Spec_2_8_A_Feb14.pdf`_, February 2020, `UEFI Forum http://www.uefi.org`_
+.. [RVPLTSPEC] `RISC-V Platform specification https://github.com/riscv/riscv-platform-specs`_
+.. [RVSBISPEC] `RISC-V Supervisor Binary Interface specification https://github.com/riscv/riscv-sbi-doc`_
+.. [RVHYPSPEC] `RISC-V ISA Hypervisor extension https://github.com/riscv/riscv-isa-manual/blob/master/src/hypervisor.tex`_
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ boot-architecture mailing list boot-architecture@lists.linaro.org https://lists.linaro.org/mailman/listinfo/boot-architecture
On 21/06/2021 18:35, Atish Patra wrote:
On Mon, Jun 21, 2021 at 10:19 AM Grant Likely grant.likely@arm.com wrote:
On 10/05/2021 18:37, Atish Patra wrote:
[...]
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
I just noticed this. If the hypervisor spec is still in draft, then why is it being referenced by EBBR? Shouldn't that spec be made final first, or at least commonly deployed?
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
This sounds like it should be more tightly written. How about:
On platforms with the hypervisor extension enabled UEFI code should be executed in HS mode to allow installation of a hypervisor or a virtualization aware operating system.
Still with the hypervisor extension in draft I wonder if it would be better to leave these bits out for now.
diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021
I don't think this is valid for a copyright message. In fact, the Arm line above it is also wrong. It should be specific to the copyright owner without the "or its affiliates". Is it okay by you if Idrop that last bit.
That's the copyright line we got from Western Digital lawyer because Western Digital has many subsidiaries (as a result of acquisitions) In fact, our group was part of HGST until recently. We have the same copyright in other open source projects (Kernel, OpenSBI, U-Boot)
Good enough for me. I'm leaving it as is.
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
g.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
Regards, Matthias
On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
I think this could be poor drafting of EBBR language rather than an unclear H extension spec.
For Arm platforms we recommend platforms with virtualization support boot the kernel in EL1 but we do not require it since some systems reserved EL1 for additional system firmware (and in one, somewhat notorious case, to deploy Si bug workarounds). I think we would use something similar for RISC-V
I agree entirely EBBR has no business describing what mode if thinks the processor will be in when UEFI starts but that is because it is not relevant rather than because it is speculation. We are in the business of recommending (or requiring) a particular processor mode when we hand over from firmware to the OS. That's what the language here should do.
Daniel.
Regards, Matthias
On 22/06/2021 11:50, Daniel Thompson wrote:
On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
I think this could be poor drafting of EBBR language rather than an unclear H extension spec.
For Arm platforms we recommend platforms with virtualization support boot the kernel in EL1 but we do not require it since some systems reserved EL1 for additional system firmware (and in one, somewhat notorious case, to deploy Si bug workarounds). I think we would use something similar for RISC-V
I assume you mean EL2 in the above paragraph, not EL1.
In the Arm case the language does specify EL2 or EL1 based on whether virtualization is supported or not:
``` On AArch64 UEFI shall execute as 64-bit code at either EL1 or EL2, depending on whether or not virtualization is available at OS load time. ```
The following paragraphs make it clear that if virtualization is available, then UEFI shall run at EL2. "Most likely" isnt very good spec langauge and should be removed from the AArch64 text.
I agree entirely EBBR has no business describing what mode if thinks the processor will be in when UEFI starts but that is because it is not relevant rather than because it is speculation. We are in the business of recommending (or requiring) a particular processor mode when we hand over from firmware to the OS. That's what the language here should do.
Okay, I think this section needs rewriting. Since RISC-V modes don't match AArch64 exception levels, I wouldn't try to duplicate the section structure here. It also isn't necessary to describe the RISC-V priviledge mode. Assume the reader knows what the modes are. Something along the lines of:
``` RISC-V Privilege Levels -----------------------
UEFI images may be executed in M mode, S mode, HS mode, or VS mode depending on what architecture features are available to the application. Which mode shall be used is detailed in the following table:
.. list-table:: RISC-V execution mode :header-rows: 1
* - Mode - Description * - M mode - blah blah blah * - S mode - blah blah blah * - HS mode - blah blah blah * - VS mode - blah blah blah
```
Personally, I'm fine if the text references hypervisor mode as a requirement in some scenarios, but I don't want any language about the draft state of that specification. However, if there are still objections from OS distribution people (e.g., Matthias) then I'll drop the hypervisor bits until it comes out of draft.
g.
On 22/06/2021 15:18, Grant Likely wrote:
On 22/06/2021 11:50, Daniel Thompson wrote:
On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
I think this could be poor drafting of EBBR language rather than an unclear H extension spec.
For Arm platforms we recommend platforms with virtualization support boot the kernel in EL1 but we do not require it since some systems reserved EL1 for additional system firmware (and in one, somewhat notorious case, to deploy Si bug workarounds). I think we would use something similar for RISC-V
I assume you mean EL2 in the above paragraph, not EL1.
In the Arm case the language does specify EL2 or EL1 based on whether virtualization is supported or not:
On AArch64 UEFI shall execute as 64-bit code at either EL1 or EL2, depending on whether or not virtualization is available at OS load time.
The following paragraphs make it clear that if virtualization is available, then UEFI shall run at EL2. "Most likely" isnt very good spec langauge and should be removed from the AArch64 text.
I agree entirely EBBR has no business describing what mode if thinks the processor will be in when UEFI starts but that is because it is not relevant rather than because it is speculation. We are in the business of recommending (or requiring) a particular processor mode when we hand over from firmware to the OS. That's what the language here should do.
Okay, I think this section needs rewriting. Since RISC-V modes don't match AArch64 exception levels, I wouldn't try to duplicate the section structure here. It also isn't necessary to describe the RISC-V priviledge mode. Assume the reader knows what the modes are. Something along the lines of:
RISC-V Privilege Levels ----------------------- UEFI images may be executed in M mode, S mode, HS mode, or VS mode depending on what architecture features are available to the application. Which mode shall be used is detailed in the following table: .. list-table:: RISC-V execution mode :header-rows: 1 * - Mode - Description * - M mode - blah blah blah * - S mode - blah blah blah * - HS mode - blah blah blah * - VS mode - blah blah blah
Personally, I'm fine if the text references hypervisor mode as a requirement in some scenarios, but I don't want any language about the draft state of that specification. However, if there are still objections from OS distribution
Wait, but that is part of your last commit [1]. Did I missed something. I thought we are discussing about this commit.
people (e.g., Matthias) then I'll drop the hypervisor bits until it comes out of draft.
I think Atish made it clear that the spec won't change the modes, so I think we can add that. I just would like to reword the sentence. What about:
Any platform with hypervisor extension enabled and that boots UEFI at HS mode, allows for the installation of a hypervisor or a virtualization aware Operating System.
I really don't like to put expressions as "most likely" into EBBR.
Regards, Matthias
[1] https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
On 22/06/2021 15:05, Matthias Brugger wrote:
On 22/06/2021 15:18, Grant Likely wrote:
On 22/06/2021 11:50, Daniel Thompson wrote:
On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
I think this could be poor drafting of EBBR language rather than an unclear H extension spec.
For Arm platforms we recommend platforms with virtualization support boot the kernel in EL1 but we do not require it since some systems reserved EL1 for additional system firmware (and in one, somewhat notorious case, to deploy Si bug workarounds). I think we would use something similar for RISC-V
I assume you mean EL2 in the above paragraph, not EL1.
In the Arm case the language does specify EL2 or EL1 based on whether virtualization is supported or not:
On AArch64 UEFI shall execute as 64-bit code at either EL1 or EL2, depending on whether or not virtualization is available at OS load time.
The following paragraphs make it clear that if virtualization is available, then UEFI shall run at EL2. "Most likely" isnt very good spec langauge and should be removed from the AArch64 text.
I agree entirely EBBR has no business describing what mode if thinks the processor will be in when UEFI starts but that is because it is not relevant rather than because it is speculation. We are in the business of recommending (or requiring) a particular processor mode when we hand over from firmware to the OS. That's what the language here should do.
Okay, I think this section needs rewriting. Since RISC-V modes don't match AArch64 exception levels, I wouldn't try to duplicate the section structure here. It also isn't necessary to describe the RISC-V priviledge mode. Assume the reader knows what the modes are. Something along the lines of:
RISC-V Privilege Levels ----------------------- UEFI images may be executed in M mode, S mode, HS mode, or VS mode depending on what architecture features are available to the application. Which mode shall be used is detailed in the following table: .. list-table:: RISC-V execution mode :header-rows: 1 * - Mode - Description * - M mode - blah blah blah * - S mode - blah blah blah * - HS mode - blah blah blah * - VS mode - blah blah blah
Personally, I'm fine if the text references hypervisor mode as a requirement in some scenarios, but I don't want any language about the draft state of that specification. However, if there are still objections from OS distribution
Wait, but that is part of your last commit [1]. Did I missed something. I thought we are discussing about this commit.
I pushed that out to a temporary branch. It hasn't been committed to mainline.
people (e.g., Matthias) then I'll drop the hypervisor bits until it comes out of draft.
I think Atish made it clear that the spec won't change the modes, so I think we can add that. I just would like to reword the sentence. What about:
Any platform with hypervisor extension enabled and that boots UEFI at HS mode, allows for the installation of a hypervisor or a virtualization aware Operating System.
I'm happy with that.
g.
On Tue, Jun 22, 2021 at 7:54 AM Grant Likely grant.likely@arm.com wrote:
On 22/06/2021 15:05, Matthias Brugger wrote:
On 22/06/2021 15:18, Grant Likely wrote:
On 22/06/2021 11:50, Daniel Thompson wrote:
On Tue, Jun 22, 2021 at 12:35:17PM +0200, Matthias Brugger wrote:
On 21/06/2021 22:55, Grant Likely wrote:
On 21/06/2021 21:53, Grant Likely wrote: [...]
> I've pushed my edited copy out to a temporary branch. You can see it here: > > https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13... >
Correction, here:
https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
Beware that this still has the wording of: "Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode"
I agree that we sould not speculate in EBBR. If we don't know for 100% sure, we should wait until the spec is released. Otherwise confusion will be big.
I think this could be poor drafting of EBBR language rather than an unclear H extension spec.
For Arm platforms we recommend platforms with virtualization support boot the kernel in EL1 but we do not require it since some systems reserved EL1 for additional system firmware (and in one, somewhat notorious case, to deploy Si bug workarounds). I think we would use something similar for RISC-V
I assume you mean EL2 in the above paragraph, not EL1.
In the Arm case the language does specify EL2 or EL1 based on whether virtualization is supported or not:
On AArch64 UEFI shall execute as 64-bit code at either EL1 or EL2, depending on whether or not virtualization is available at OS load time.
The following paragraphs make it clear that if virtualization is available, then UEFI shall run at EL2. "Most likely" isnt very good spec langauge and should be removed from the AArch64 text.
I agree entirely EBBR has no business describing what mode if thinks the processor will be in when UEFI starts but that is because it is not relevant rather than because it is speculation. We are in the business of recommending (or requiring) a particular processor mode when we hand over from firmware to the OS. That's what the language here should do.
Okay, I think this section needs rewriting. Since RISC-V modes don't match AArch64 exception levels, I wouldn't try to duplicate the section structure here. It also isn't necessary to describe the RISC-V priviledge mode. Assume the reader knows what the modes are. Something along the lines of:
RISC-V Privilege Levels ----------------------- UEFI images may be executed in M mode, S mode, HS mode, or VS mode depending on what architecture features are available to the application. Which mode shall be used is detailed in the following table: .. list-table:: RISC-V execution mode :header-rows: 1 * - Mode - Description * - M mode - blah blah blah * - S mode - blah blah blah * - HS mode - blah blah blah * - VS mode - blah blah blah
Personally, I'm fine if the text references hypervisor mode as a requirement in some scenarios, but I don't want any language about the draft state of that specification. However, if there are still objections from OS distribution
Wait, but that is part of your last commit [1]. Did I missed something. I thought we are discussing about this commit.
I pushed that out to a temporary branch. It hasn't been committed to mainline.
people (e.g., Matthias) then I'll drop the hypervisor bits until it comes out of draft.
I think Atish made it clear that the spec won't change the modes, so I think we can add that. I just would like to reword the sentence. What about:
Any platform with hypervisor extension enabled and that boots UEFI at HS mode, allows for the installation of a hypervisor or a virtualization aware Operating System.
Sounds good to me. Thanks.
Regarding "UEFI Boot at S mode" section [1], it just tries to emphasize that UEFI boot at S-mode is the most common scenario for current/near future platforms as there are not many platforms with hypervisor extension available right now. We can reword something like this as talking about the draft extension is not necessary.
"Most systems are expected to boot UEFI at S mode in absence of hypervisor extension."
[1] https://github.com/ARM-software/ebbr/commit/714f6fd6747f61c0557fdce7d5bed7b5...
I'm happy with that.
g.
On 23/06/2021 07:34, Atish Patra wrote:
On Tue, Jun 22, 2021 at 7:54 AM Grant Likely grant.likely@arm.com wrote: Regarding "UEFI Boot at S mode" section [1], it just tries to emphasize that UEFI boot at S-mode is the most common scenario for current/near future platforms as there are not many platforms with hypervisor extension available right now. We can reword something like this as talking about the draft extension is not necessary.
"Most systems are expected to boot UEFI at S mode in absence of hypervisor extension."
Here's what I've merged after some editorial work. If this isn't right, follow up patches can fix it up.
https://github.com/ARM-software/ebbr/commit/a3e9b4bac76c054b505d3c2a42b7f10e...
g.
On Mon, Jul 5, 2021 at 1:14 AM Grant Likely grant.likely@arm.com wrote:
On 23/06/2021 07:34, Atish Patra wrote:
On Tue, Jun 22, 2021 at 7:54 AM Grant Likely grant.likely@arm.com wrote: Regarding "UEFI Boot at S mode" section [1], it just tries to emphasize that UEFI boot at S-mode is the most common scenario for current/near future platforms as there are not many platforms with hypervisor extension available right now. We can reword something like this as talking about the draft extension is not necessary.
"Most systems are expected to boot UEFI at S mode in absence of hypervisor extension."
Here's what I've merged after some editorial work. If this isn't right, follow up patches can fix it up.
Thanks. We can fix it once hypervisor extension is frozen (hopefully by the end of this year).
https://github.com/ARM-software/ebbr/commit/a3e9b4bac76c054b505d3c2a42b7f10e...
g.
On Mon, Jun 21, 2021 at 1:53 PM Grant Likely grant.likely@arm.com wrote:
On 21/06/2021 18:35, Atish Patra wrote:
On Mon, Jun 21, 2021 at 10:19 AM Grant Likely grant.likely@arm.com wrote:
On 10/05/2021 18:37, Atish Patra wrote:
[...]
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
I just noticed this. If the hypervisor spec is still in draft, then why is it being referenced by EBBR? Shouldn't that spec be made final first, or at least commonly deployed?
The hypervisor spec is still in draft but the details of privilege modes will not change. In fact, there has been almost zero change in the last one year. It has been in draft stage for various other reasons but not related to the technical ones ;) It's already been implemented in an FPGA and a working KVM port is available [1]. We are hoping that it will be merged by the end of this year.
[1] https://lwn.net/Articles/856685/
+UEFI Boot at HS mode +^^^^^^^^^^^^^^^^^^^^
+Any platform with hypervisor extension enabled most likely to boot UEFI at HS mode, +to allow for the installation of a hypervisor or a virtualization aware Operating System.
This sounds like it should be more tightly written. How about:
On platforms with the hypervisor extension enabled UEFI code should be executed in HS mode to allow installation of a hypervisor or a virtualization aware operating system.
Looks good.
Still with the hypervisor extension in draft I wonder if it would be better to leave these bits out for now.
As we just talk about the privilege modes here and that is unlikely to change, this section will not change in future.
diff --git a/source/index.rst b/source/index.rst index 48318757f717..acd214d25323 100644 --- a/source/index.rst +++ b/source/index.rst @@ -1,5 +1,6 @@ .. EBBR Source Document Copyright Arm Limited, 2017-2019
- Copyright Western Digital Corporation or its affiliates, 2021
I don't think this is valid for a copyright message. In fact, the Arm line above it is also wrong. It should be specific to the copyright owner without the "or its affiliates". Is it okay by you if Idrop that last bit.
That's the copyright line we got from Western Digital lawyer because Western Digital has many subsidiaries (as a result of acquisitions) In fact, our group was part of HGST until recently. We have the same copyright in other open source projects (Kernel, OpenSBI, U-Boot)
Good enough for me. I'm leaving it as is.
I've pushed my edited copy out to a temporary branch. You can see it here:
https://github.com/ARM-software/ebbr/commit/9d4632a3911fd460cb1adf6a5b1a2b13...
The updated commit Looks good to me.
g.
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-- Regards, Atish
On Mon, Jun 21, 2021 at 03:35:02PM -0700, Atish Patra wrote:
On Mon, Jun 21, 2021 at 1:53 PM Grant Likely grant.likely@arm.com wrote:
On 21/06/2021 18:35, Atish Patra wrote:
On Mon, Jun 21, 2021 at 10:19 AM Grant Likely grant.likely@arm.com wrote:
On 10/05/2021 18:37, Atish Patra wrote:
[...]
+UEFI Boot at S mode +^^^^^^^^^^^^^^^^^^^^^^
+Most systems are expected to boot UEFI at S mode as the hypervisor extension [RVHYPSPEC]_ is +still in draft state.
I just noticed this. If the hypervisor spec is still in draft, then why is it being referenced by EBBR? Shouldn't that spec be made final first, or at least commonly deployed?
The hypervisor spec is still in draft but the details of privilege modes will not change. In fact, there has been almost zero change in the last one year. It has been in draft stage for various other reasons but not related to the technical ones ;) It's already been implemented in an FPGA and a working KVM port is available [1]. We are hoping that it will be merged by the end of this year.
Draft specs are obviously an area where we should tread with caution.
That said I think there could be a case for making an exception:
* The surrounding ecosystem is relatively mature with multiple software implementatons (KVM and Xen) together simulators (plural) and an FPGA-based hardware implementation.
* Draft spec updates are infrequent since it is almost like the H extension spec is in a holding pattern waiting for additional features to land elsewhere (primarily a virtualizable external interrupt controller).
* The proposed language in EBBR is far away from the contentious/unconcluded parts of the spec and, conveniently is guidance (should) rather than mandatory (must).
* We can clearly reference a versioned spec even if is draft.
* The glacial progress of the H extension is notorious enough to make the news ;-)
Daniel.
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