On Tue, Dec 18, 2012 at 09:21:44PM +0000, Pareena Verma wrote:

Hi,

I have tried to use the Linux kernels for ARM to generate kernel image for CortexA7 and CortexA15 and had a question about the initialization boot code. One difference between A7 and A15 seems to be that the ARM Cortex A7 TRM mentions that in both uni and multi-processor environment, the caches will be unusable if the SMP bit of ACTLR ACTLR[6] is not set to one. This seems to be different for A15. I looked at the processor specific initialization code in the Linaro kernel but couldn't find the bit being set. Is there any specific build that you can point me to that does this?. If this is not done, it almost appears like A7 can never use its caches (atleast TRM seems to be very explicit about it). Please kindly advice. Any documentation/input in this regard would be very helpful.

Thanks!

Hi Pareena,

You are correct when you state that Cortex-A7 needs the SMP bit set before one can use any of its caches. However, as this is a one-off setup it was decided that the job of setting the SMP bit should be handled by the bootloader. Hence the lack of any code in the Linux kernel setup code.

Best regards, Liviu

---

boot-architecture mailing list boot-architecture@lists.linaro.org http://lists.linaro.org/mailman/listinfo/boot-architecture