linaro-dev August 2011

linaro-dev@lists.linaro.org

126 participants
239 discussions

[RFC PATCH 16/24] mfd: twl4030-irq: include mach/irqs.h directly

by Venkatraman S

From: Venkatraman S <venkat(a)linaro.org> Signed-off-by: Venkatraman S <venkat(a)linaro.org> --- drivers/mfd/twl4030-irq.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c index 8a7ee31..ac3a27d 100644 --- a/drivers/mfd/twl4030-irq.c +++ b/drivers/mfd/twl4030-irq.c @@ -34,7 +34,7 @@ #include <linux/slab.h> #include <linux/i2c/twl.h> - +#include <mach/irqs.h> #include "twl-core.h" /* -- 1.7.1

13 years, 4 months

ARM porting Jam today 14:00 - 18:00 UTC

by Riku Voipio

Dear ARM fans, Linaro Developer Platform team organises every week (Wednesday 14:00 - 18:00 UTC) an ARM porting Jam. The idea is to gather all developers together to fix userspace portability issues across the board. The list of bugs being worked on is at launchpad: https://bugs.launchpad.net/ubuntu/+bugs?field.tag=arm-porting-queue&orderby… Interested in making the software in Ubuntu run better on ARM? Join us on the #linaro channel on irc.linaro.org (aka freenode) today! Cheers, Riku

13 years, 4 months

[PATCH 0/2] Memory mapped virtio device

by Pawel Moll

Hi All, These two patches are a proposal of memory mapped virtio device. The main goal was to provide an equivalent of the virtio PCI device, happily used by KVM an qemu on x86, which could be used by PCI-less platforms (common in ARM world). The interface exposed by my device is very similar to the original virtio_pci one, maybe just a little bit simplified (no sophisticated IRQ infrastructure here). Of course all the control registers live in memory space, instead of PCI IO space (writel vs iowrite32). This raises an obvious question whether these two implementation could share some common code. Probably some constant values could be shared (like VIRTIO_*_HOST_FEATURES or VIRTIO_*_VRING_ALIGN), maybe struct virtio_*_vq_info as well. On the other hand the vring interface itself is an abstraction layer already... I really don't know, all comments and ideas appreciated. The second thing is AMBAness of the driver... I've decided to make it an AMBA device rather than simple platform device to add at least a touch of "dicoverability". The idea was simple - one can add "permanent" virtio AMBA device in the kernel placing it somewhere in reserved area of real hardware, so the kernel running on hardware will not get correct amba_id value and ignore the device. With the eve of Ultimate DeviceTreenes this argument is slightly out of date, as qemu could add the virtio device even in runtime. So maybe I should convert it into platform_device then? This brings additional problem though. Magnus Damm already proposed a platform virtio device here: http://thread.gmane.org/gmane.linux.ports.sh.devel/11554 however it's something completely different, as his use case is a heterogeneous system and the virtio is used mainly as a transport between nodes. It also uses lguest-based interface, which is much less applicable to the qemu reality. Let me just add that Peter Maydell kindly agreed to work on the qemu side of the problem, once there is some consensus about the kernel part. He also suggested to send this to linaro-dev first, before throwing it into LKML fire. So here I am :-) All comments welcome! PaweÅ‚ Pawel Moll (2): arm: Add VIRTUALIZATION configuration menu and virtio options arm: Add AMBA bus driver for virtio device arch/arm/Kconfig | 16 ++ drivers/virtio/Kconfig | 11 + drivers/virtio/Makefile | 1 + drivers/virtio/virtio_amba.c | 443 ++++++++++++++++++++++++++++++++++++++++++ include/linux/virtio_amba.h | 62 ++++++ 5 files changed, 533 insertions(+), 0 deletions(-) create mode 100644 drivers/virtio/virtio_amba.c create mode 100644 include/linux/virtio_amba.h

13 years, 4 months

[PATCH] ARM: ux500: send cpufreq notification for all cpus

by Vincent Guittot

The same clock is used for all cpus so we must notify the frequency change for each one in order to update the configuration of all twd clockevents. Signed-off-by: Vincent Guittot <vincent.guittot(a)linaro.org> --- drivers/cpufreq/db8500-cpufreq.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c index 0d8dd1c..4cb5785 100644 --- a/drivers/cpufreq/db8500-cpufreq.c +++ b/drivers/cpufreq/db8500-cpufreq.c @@ -76,13 +76,13 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy, freqs.old = policy->cur; freqs.new = freq_table[idx].frequency; - freqs.cpu = policy->cpu; if (freqs.old == freqs.new) return 0; /* pre-change notification */ - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + for_each_online_cpu(freqs.cpu) + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* request the PRCM unit for opp change */ if (prcmu_set_arm_opp(idx2opp[idx])) { @@ -91,7 +91,8 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy, } /* post change notification */ - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + for_each_online_cpu(freqs.cpu) + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); return 0; } -- 1.7.4.1

13 years, 4 months

[PATCH 2/4 v4] pinmux: add a driver for the U300 pinmux

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This adds a driver for the U300 pinmux portions of the system controller "SYSCON". It also serves as an example of how to use the pinmux subsystem. This driver also houses the platform data for the only supported platform. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- arch/arm/mach-u300/core.c | 19 ++ drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinmux-u300.c | 422 +++++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinmux-u300.h | 141 ++++++++++++++ 5 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/pinctrl/pinmux-u300.c create mode 100644 drivers/pinctrl/pinmux-u300.h diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 399c89f..b0c45c3 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -25,6 +25,7 @@ #include <linux/err.h> #include <linux/mtd/nand.h> #include <linux/mtd/fsmc.h> +#include <linux/pinctrl/machine.h> #include <asm/types.h> #include <asm/setup.h> @@ -1630,6 +1631,20 @@ static struct platform_device dma_device = { }, }; +static struct platform_device pinmux_device = { + .name = "pinmux-u300", + .id = -1, + .num_resources = ARRAY_SIZE(pinmux_resources), + .resource = pinmux_resources, +}; + +/* Padmux settings */ +static struct pinmux_map u300_padmux_map[] = { + PINMUX_MAP_PRIMARY("mmc0", "mmci"), + PINMUX_MAP_PRIMARY("spi0", "pl022"), + PINMUX_MAP_PRIMARY("uart0", "uart0"), +}; + /* * Notice that AMBA devices are initialized before platform devices. * @@ -1828,6 +1843,10 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Initialize pinmuxing */ + pinmux_register_mappings(u300_padmux_map, + ARRAY_SIZE(u300_padmux_map)); + /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index adb0be0..fdeca2f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -26,4 +26,11 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. +config PINMUX_U300 + bool "U300 pinmux driver" + depends on ARCH_U300 + select PINMUX + help + Say Y here to enable the U300 pinmux driver + endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 596ce9f..63d4241 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -4,3 +4,4 @@ ccflags-$(CONFIG_DEBUG_PINMUX) += -DDEBUG obj-$(CONFIG_PINCTRL) += core.o obj-$(CONFIG_PINMUX) += pinmux.o +obj-$(CONFIG_PINMUX_U300) += pinmux-u300.o diff --git a/drivers/pinctrl/pinmux-u300.c b/drivers/pinctrl/pinmux-u300.c new file mode 100644 index 0000000..c0cefb6 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.c @@ -0,0 +1,422 @@ +/* + * Driver for the U300 pin controller + * + * Based on the original U300 padmux functions + * Copyright (C) 2009-2011 ST-Ericsson AB + * Author: Martin Persson <martin.persson(a)stericsson.com> + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * The DB3350 design and control registers are oriented around pads rather than + * pins, so we enumerate the pads we can mux rather than actual pins. The pads + * are connected to different pins in different packaging types, so it would + * be confusing. + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinmux-u300.h" + +#define DRIVER_NAME "pinmux-u300" + +/* + * The DB3350 has 467 pads, I have enumerated the pads clockwise around the + * edges of the silicon, finger by finger. LTCORNER upper left is pad 0. + * Data taken from the PadRing chart, arranged like this: + * + * 0 ..... 104 + * 466 105 + * . . + * . . + * 358 224 + * 357 .... 225 + */ +#define U300_NUM_PADS 467 + +/* Pad names for the pinmux subsystem */ +const struct pinctrl_pin_desc __refdata u300_pads[] = { + PINCTRL_PIN(0, "P PAD VDD 28"), + PINCTRL_PIN(1, "P PAD GND 28"), + PINCTRL_PIN(2, "PO SIM RST N"), + PINCTRL_PIN(3, "VSSIO 25"), + PINCTRL_PIN(4, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(5, "PWR VSSCOMMON"), + PINCTRL_PIN(6, "PI ADC I1 POS"), + PINCTRL_PIN(7, "PI ADC I1 NEG"), + PINCTRL_PIN(8, "PWR VSSAD0"), + PINCTRL_PIN(9, "PWR VCCAD0"), + PINCTRL_PIN(10, "PI ADC Q1 NEG"), + PINCTRL_PIN(11, "PI ADC Q1 POS"), + PINCTRL_PIN(12, "PWR VDDAD"), + PINCTRL_PIN(13, "PWR GNDAD"), + PINCTRL_PIN(14, "PI ADC I2 POS"), + PINCTRL_PIN(15, "PI ADC I2 NEG"), + PINCTRL_PIN(16, "PWR VSSAD1"), + PINCTRL_PIN(17, "PWR VCCAD1"), + PINCTRL_PIN(18, "PI ADC Q2 NEG"), + PINCTRL_PIN(19, "PI ADC Q2 POS"), + PINCTRL_PIN(20, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(21, "PWR VCCGPAD"), + PINCTRL_PIN(22, "PI TX POW"), + PINCTRL_PIN(23, "PWR VSSGPAD"), + PINCTRL_PIN(24, "PO DAC I POS"), + PINCTRL_PIN(25, "PO DAC I NEG"), + PINCTRL_PIN(26, "PO DAC Q POS"), + PINCTRL_PIN(27, "PO DAC Q NEG"), + PINCTRL_PIN(28, "PWR VSSDA"), + PINCTRL_PIN(29, "PWR VCCDA"), + PINCTRL_PIN(30, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(31, "P PAD VDDIO 11"), + PINCTRL_PIN(32, "PI PLL 26 FILTVDD"), + PINCTRL_PIN(33, "PI PLL 26 VCONT"), + PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"), + PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"), + PINCTRL_PIN(36, "VDDA PLL ESD"), + PINCTRL_PIN(37, "VSSA PLL ESD"), + PINCTRL_PIN(38, "VSS PLL"), + PINCTRL_PIN(39, "VDDC PLL"), + PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"), + PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"), + PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"), + PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"), + PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"), + PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"), + PINCTRL_PIN(46, "P PAD VSSIO 11"), + PINCTRL_PIN(47, "P PAD VSSIO 12"), + PINCTRL_PIN(48, "PI POW RST N"), + PINCTRL_PIN(49, "VDDC IO"), + PINCTRL_PIN(50, "P PAD VDDIO 16"), + PINCTRL_PIN(134, "UART0 RTS"), + PINCTRL_PIN(135, "UART0 CTS"), + PINCTRL_PIN(136, "UART0 TX"), + PINCTRL_PIN(137, "UART0 RX"), + PINCTRL_PIN(166, "MMC DATA DIR LS"), + PINCTRL_PIN(167, "MMC DATA 3"), + PINCTRL_PIN(168, "MMC DATA 2"), + PINCTRL_PIN(169, "MMC DATA 1"), + PINCTRL_PIN(170, "MMC DATA 0"), + PINCTRL_PIN(171, "MMC CMD DIR LS"), + PINCTRL_PIN(176, "MMC CMD"), + PINCTRL_PIN(177, "MMC CLK"), + PINCTRL_PIN(420, "SPI CLK"), + PINCTRL_PIN(421, "SPI DO"), + PINCTRL_PIN(422, "SPI DI"), + PINCTRL_PIN(423, "SPI CS0"), + PINCTRL_PIN(424, "SPI CS1"), + PINCTRL_PIN(425, "SPI CS2"), +}; + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct u300_pmx { + struct device *dev; + struct pinmux_dev *pmx; + u32 phybase; + u32 physize; + void __iomem *virtbase; +}; + +/** + * u300_pmx_registers - the array of registers read/written for each pinmux + * shunt setting + */ +const u32 u300_pmx_registers[] = { + U300_SYSCON_PMC1LR, + U300_SYSCON_PMC1HR, + U300_SYSCON_PMC2R, + U300_SYSCON_PMC3R, + U300_SYSCON_PMC4R, +}; + +/** + * struct pmx_onmask - mask bits to enable/disable padmux + * @mask: mask bits to disable + * @val: mask bits to enable + * + * onmask lazy dog: + * onmask = { + * {"PMC1LR" mask, "PMC1LR" value}, + * {"PMC1HR" mask, "PMC1HR" value}, + * {"PMC2R" mask, "PMC2R" value}, + * {"PMC3R" mask, "PMC3R" value}, + * {"PMC4R" mask, "PMC4R" value} + * } + */ +struct u300_pmx_mask { + u16 mask; + u16 bits; +}; + +/** + * struct u300_pmx_func - describes a U300 pinmux function + * @name: the name of this specific function + * @pins: an array of discrete physical pins used in this mapping, taken + * from the global pin enumeration space + * @num_pins: the number of pins in this mapping array, i.e. the number of + * elements in .pins so we can iterate over that array + * @onmask: bits to set to enable this muxing + */ +struct u300_pmx_func { + const char *name; + const unsigned int *pins; + const unsigned num_pins; + const struct u300_pmx_mask *mask; +}; + +static const unsigned uart0_pins[] = { 134, 135, 136, 137 }; +static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; +static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; + +static const struct u300_pmx_mask uart0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_UART0_1_MASK | + U300_SYSCON_PMC1HR_APP_UART0_2_MASK, + U300_SYSCON_PMC1HR_APP_UART0_1_UART0 | + U300_SYSCON_PMC1HR_APP_UART0_2_UART0 + }, + {0, 0}, + {0, 0}, + {0, 0}, +}; + +static const struct u300_pmx_mask mmc0_mask[] = { + { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD}, + {0, 0}, + {0, 0}, + {0, 0}, + { U300_SYSCON_PMC4R_APP_MISC_12_MASK, + U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO } +}; + +static const struct u300_pmx_mask spi0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_SPI_2_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, + U300_SYSCON_PMC1HR_APP_SPI_2_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI + }, + {0, 0}, + {0, 0}, + {0, 0} +}; + +static const struct u300_pmx_func u300_pmx_funcs[] = { + { + .name = "uart0", + .pins = uart0_pins, + .num_pins = ARRAY_SIZE(uart0_pins), + .mask = uart0_mask, + }, + { + .name = "mmc0", + .pins = mmc0_pins, + .num_pins = ARRAY_SIZE(mmc0_pins), + .mask = mmc0_mask, + }, + { + .name = "spi0", + .pins = spi0_pins, + .num_pins = ARRAY_SIZE(spi0_pins), + .mask = spi0_mask, + }, +}; + +static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, + bool enable) +{ + u16 regval, val, mask; + int i; + + for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { + if (enable) + val = u300_pmx_funcs[selector].mask->bits; + else + val = 0; + + mask = u300_pmx_funcs[selector].mask->mask; + if (mask != 0) { + regval = readw(upmx->virtbase + u300_pmx_registers[i]); + regval &= ~mask; + regval |= val; + writew(regval, upmx->virtbase + u300_pmx_registers[i]); + } + } +} + +static int u300_pmx_enable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, true); + + return 0; +} + +static void u300_pmx_disable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, false); +} + +static int u300_pmx_list(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + return 0; +} + +static const char *u300_pmx_get_fname(struct pinmux_dev *pmxdev, + unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return NULL; + return u300_pmx_funcs[selector].name; +} + +static int u300_pmx_get_pins(struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + *pins = (unsigned *) u300_pmx_funcs[selector].pins; + *num_pins = u300_pmx_funcs[selector].num_pins; + return 0; +} + +static void u300_dbg_show(struct pinmux_dev *pmxdev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static struct pinmux_ops u300_pmx_ops = { + .list_functions = u300_pmx_list, + .get_function_name = u300_pmx_get_fname, + .get_function_pins = u300_pmx_get_pins, + .enable = u300_pmx_enable, + .disable = u300_pmx_disable, + .dbg_show = u300_dbg_show, +}; + +static struct pinmux_desc u300_pmx_desc = { + .name = DRIVER_NAME, + .pins = u300_pads, + .npins = ARRAY_SIZE(u300_pads), + .maxpin = U300_NUM_PADS-1, + .pmxops = &u300_pmx_ops, + .owner = THIS_MODULE, +}; + +static int __init u300_pmx_probe(struct platform_device *pdev) +{ + int ret; + struct u300_pmx *upmx; + struct resource *res; + + /* Create state holders etc for this driver */ + upmx = kzalloc(sizeof(struct u300_pmx), GFP_KERNEL); + if (!upmx) + return -ENOMEM; + + upmx->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out_no_resource; + } + upmx->phybase = res->start; + upmx->physize = resource_size(res); + + if (request_mem_region(upmx->phybase, upmx->physize, + DRIVER_NAME) == NULL) { + ret = -EBUSY; + goto out_no_memregion; + } + + upmx->virtbase = ioremap(upmx->phybase, upmx->physize); + if (!upmx->virtbase) { + ret = -ENOMEM; + goto out_no_remap; + } + + /* Now register the pin controller and all pins it handles */ + upmx->pctl = pinctrl_register(&u300_pmx_desc, &pdev->dev, upmx); + if (IS_ERR(upmx->pctl)) { + dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); + ret = PTR_ERR(upmx->pmx); + goto out_no_pmx; + } + platform_set_drvdata(pdev, upmx); + + dev_info(&pdev->dev, "initialized U300 pinmux driver\n"); + + return 0; + +out_no_pmx: + iounmap(upmx->virtbase); +out_no_remap: + platform_set_drvdata(pdev, NULL); +out_no_memregion: + release_mem_region(upmx->phybase, upmx->physize); +out_no_resource: + kfree(upmx); + return ret; +} + +static int __exit u300_pmx_remove(struct platform_device *pdev) +{ + struct u300_pmx *upmx = platform_get_drvdata(pdev); + + if (upmx) { + pinmux_unregister(upmx->pmx); + iounmap(upmx->virtbase); + release_mem_region(upmx->phybase, upmx->physize); + platform_set_drvdata(pdev, NULL); + kfree(upmx); + } + + return 0; +} + +static struct platform_driver u300_pmx_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .remove = __exit_p(u300_pmx_remove), +}; + +static int __init u300_pmx_init(void) +{ + return platform_driver_probe(&u300_pmx_driver, u300_pmx_probe); +} +arch_initcall(u300_pmx_init); + +static void __exit u300_pmx_exit(void) +{ + platform_driver_unregister(&u300_pmx_driver); +} +module_exit(u300_pmx_exit); + +MODULE_AUTHOR("Linus Walleij <linus.walleij(a)linaro.org>"); +MODULE_DESCRIPTION("U300 pin control driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinmux-u300.h b/drivers/pinctrl/pinmux-u300.h new file mode 100644 index 0000000..c2ec260 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.h @@ -0,0 +1,141 @@ +/* + * Register definitions for the U300 Padmux control registers in the + * system controller + */ + +/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ +#define U300_SYSCON_PMC1LR (0x007C) +#define U300_SYSCON_PMC1LR_MASK (0xFFFF) +#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) +#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) +#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +/* For BS335 */ +#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) +/* For BS365 */ +#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +/* Common defs */ +#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) +#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) +#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) +#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) +#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) +#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) +#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) +#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) +#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) +#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) +#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) +#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) +#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) +#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) +/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ +#define U300_SYSCON_PMC1HR (0x007E) +#define U300_SYSCON_PMC1HR_MASK (0xFFFF) +#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) +#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) +#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) +#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) +#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) +#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) +#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) +#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) +#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) +#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) +#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) +#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) +/* Padmux 2 control */ +#define U300_SYSCON_PMC2R (0x100) +#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) +#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) +#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) +#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) +#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) +#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) +#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) +#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) +#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) +#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) +#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) +/* TODO: More SYSCON registers missing */ +#define U300_SYSCON_PMC3R (0x10c) +#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) +#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) +#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) +#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) +/* TODO: Missing other configs */ +#define U300_SYSCON_PMC4R (0x168) +#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) +#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) +#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) +#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) +#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) -- 1.7.3.2

13 years, 4 months

GDB multi-threaded debugging?

by Christian Robottom Reis

I've decided to take a look at this moderately quiet l.k.embedded list and noticed this question: Is it possible to debug multi-threaded applications using gdb on ARM these days? http://thread.gmane.org/gmane.linux.kernel.embedded/3631 This is completely supported now, right? -- Christian Robottom Reis, Engineering VP Brazil (GMT-3) | [+55] 16 9112 6430 | [+1] 612 216 4935 Linaro.org: Open Source Software for ARM SoCs

13 years, 4 months

[RFC PATCH 18/24] arm: irq: do not assume NR_IRQS to be defined

by Venkatraman S

From: Venkatraman S <venkat(a)linaro.org> If SPARSE_IRQ is defined, NR_IRQS will not necessarily be relevant. Use the number populated in machine descriptor. Note: HARDIRQ_BITS is defined as a constant independent of NR_IRQS. Needs review if this assumption makes sense. Signed-off-by: Venkatraman S <venkat(a)linaro.org> --- arch/arm/common/gic.c | 8 ++++---- arch/arm/include/asm/hardirq.h | 6 ++++++ arch/arm/kernel/irq.c | 8 +++++++- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4ddd0a6..6fb5fa4 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -28,7 +28,7 @@ #include <linux/smp.h> #include <linux/cpumask.h> #include <linux/io.h> - +#include <linux/irqnr.h> #include <asm/irq.h> #include <asm/mach/irq.h> #include <asm/hardware/gic.h> @@ -231,7 +231,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) goto out; cascade_irq = gic_irq + chip_data->irq_offset; - if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) + if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= nr_irqs)) do_bad_IRQ(cascade_irq, desc); else generic_handle_irq(cascade_irq); @@ -312,8 +312,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic, * Limit number of interrupts registered to the platform maximum */ irq_limit = gic->irq_offset + gic_irqs; - if (WARN_ON(irq_limit > NR_IRQS)) - irq_limit = NR_IRQS; + if (WARN_ON(irq_limit > nr_irqs)) + irq_limit = nr_irqs; /* * Setup the Linux IRQ subsystem. diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 89ad180..4bea5c0 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h @@ -30,6 +30,10 @@ u64 smp_irq_stat_cpu(unsigned int cpu); #define arch_irq_stat_cpu smp_irq_stat_cpu +#ifndef NR_IRQS +/* FIXME: Need a better way to derive HARDIRQ_BITS */ +#define HARDIRQ_BITS 10 +#else #if NR_IRQS > 512 #define HARDIRQ_BITS 10 #elif NR_IRQS > 256 @@ -47,6 +51,8 @@ u64 smp_irq_stat_cpu(unsigned int cpu); # error HARDIRQ_BITS is too low! #endif +#endif + #define __ARCH_IRQ_EXIT_IRQS_DISABLED 1 #endif /* __ASM_HARDIRQ_H */ diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 83bbad0..12ffa9d 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -124,7 +124,13 @@ void __init init_IRQ(void) #ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs(void) { - nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; + if (machine_desc->nr_irqs) + nr_irqs = machine_desc->nr_irqs; + #ifdef NR_IRQS + else + nr_irqs = NR_IRQS; + #endif + WARN_ON(nr_irqs); return nr_irqs; } #endif -- 1.7.1

13 years, 4 months

[RFC PATCH 23/24] sound: imx-pcm-fiq: replace fiq enable/disable interface with irq apis

by Venkatraman S

From: Venkatraman S <venkat(a)linaro.org> The underlying implementation in enable_fiq/disable_fiq uses the irqs anyway, so use them directly. Signed-off-by: Venkatraman S <venkat(a)linaro.org> --- sound/soc/imx/imx-pcm-fiq.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/imx/imx-pcm-fiq.c b/sound/soc/imx/imx-pcm-fiq.c index 413b78d..7f12b4b 100644 --- a/sound/soc/imx/imx-pcm-fiq.c +++ b/sound/soc/imx/imx-pcm-fiq.c @@ -138,7 +138,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) hrtimer_start(&iprtd->hrt, ns_to_ktime(iprtd->poll_time_ns), HRTIMER_MODE_REL); if (++fiq_enable == 1) - enable_fiq(imx_pcm_fiq); + enable_irq(imx_pcm_fiq + FIQ_START); break; @@ -148,7 +148,7 @@ static int snd_imx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) atomic_set(&iprtd->running, 0); if (--fiq_enable == 0) - disable_fiq(imx_pcm_fiq); + disable_irq(imx_pcm_fiq + FIQ_START); break; default: -- 1.7.1

13 years, 4 months

[RFC PATCH 22/24] arm: rpc-dma: replace fiq enable/disable interface with irq apis

by Venkatraman S

From: Venkatraman S <venkat(a)linaro.org> The underlying implementation in enable_fiq/disable_fiq uses the irqs anyway, so use them directly. Signed-off-by: Venkatraman S <venkat(a)linaro.org> --- arch/arm/mach-rpc/dma.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 85883b2..83bb9ac 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c @@ -289,13 +289,13 @@ static void floppy_enable_dma(unsigned int chan, dma_t *dma) set_fiq_handler(fiqhandler_start, fiqhandler_length); set_fiq_regs(&regs); - enable_fiq(fdma->fiq); + enable_irq(fdma->fiq + FIQ_START); } static void floppy_disable_dma(unsigned int chan, dma_t *dma) { struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); - disable_fiq(fdma->fiq); + disable_irq(fdma->fiq + FIQ_START); release_fiq(&fh); } -- 1.7.1

13 years, 4 months

[RFC PATCH 21/24] mx1_camera: clear the use of fiq

by Venkatraman S

From: Venkatraman S <venkat(a)linaro.org> fiq interface as used by mx1 camera is suspicious, with the definition of NR_IRQS to be 1024 in the only platform this is used (OMAP). Set the stage for decoupling this from using the fiq interface. Signed-off-by: Venkatraman S <venkat(a)linaro.org> --- drivers/media/video/mx1_camera.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c index 63f8a0c..0465041 100644 --- a/drivers/media/video/mx1_camera.c +++ b/drivers/media/video/mx1_camera.c @@ -45,6 +45,7 @@ #include <mach/dma-mx1-mx2.h> #include <mach/hardware.h> #include <mach/mx1_camera.h> +#include <mach/irqs.h> /* * CSI registers @@ -799,7 +800,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev) set_fiq_regs(&regs); mxc_set_irq_fiq(irq, 1); - enable_fiq(irq); + enable_irq(irq + FIQ_START); pcdev->soc_host.drv_name = DRIVER_NAME; pcdev->soc_host.ops = &mx1_soc_camera_host_ops; @@ -815,7 +816,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev) return 0; exit_free_irq: - disable_fiq(irq); + disable_irq(irq + FIQ_START); mxc_set_irq_fiq(irq, 0); release_fiq(&fh); exit_free_dma: @@ -840,7 +841,7 @@ static int __exit mx1_camera_remove(struct platform_device *pdev) struct resource *res; imx_dma_free(pcdev->dma_chan); - disable_fiq(pcdev->irq); + disable_irq(pcdev->irq + FIQ_START); mxc_set_irq_fiq(pcdev->irq, 0); release_fiq(&fh); -- 1.7.1

13 years, 4 months

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linaro-dev August 2011