linaro-dev June 2011

linaro-dev@lists.linaro.org

149 participants
196 discussions

Booting linux-linaro-2.6.37 on Beagle Board

by Avik Sil

Hi, I tried booting linux-linaro-2.6.37 kernel on my beagle board C4. I executed following: 1. Installed linaro on a 4 GB SD card using linaro-image-tools 0.4.1 with hwpack daily snapshot hwpack_linaro-omap3_20110125-0_armel_supported.tar.gz and linaro-natty-headless-tar-20101202-1.tar.gz. It was booting properly on my BB. 2. Cloned linux-linaro-2.6.37. Changed to source directory 3. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- omap2plus_defconfig 4. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- menuconfig (enabled EARLY_PRINTK) 5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- uImage 6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- modules 7. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- modules_install INSTALL_MOD_PATH=/media/rootfs 8. cp arch/arm/boot/uImage /media/boot; sync Everything went on smoothly. Then I put the SD card on BB and powered it on. I got a kernel panic: http://paste.ubuntu.com/560562 Please help me figuring out the problem. Is it because I didn't create uInitrd? If so, then how to create it for ARM? Regards, Avik

11 years, 3 months

Optimized kernel memcpy/memset

by Christian Robottom Reis

Hey there, I was asked today in the board meeting about the use of NEON routines in the kernel; I said we had looked into this but hadn't done it because a) it wasn't conclusively better and b) if better, it would need to be done conditionally per-platform. But I wanted to double-check that's actually true (and I'm copying Vijay to keep me honest). I have some references: http://lists.linaro.org/pipermail/linaro-toolchain/2011-January/000722.html http://groups.google.com/group/beagleboard/browse_thread/thread/12c7bd415fb… http://www.spinics.net/lists/arm-kernel/msg106503.html http://dev.gentoo.org/~armin76/arm/memcpy-neon_result.txt https://wiki.linaro.org/WorkingGroups/ToolChain/Benchmarks/InitialMemcpy?hi… https://wiki.linaro.org/WorkingGroups/ToolChain/StringRoutines?highlight=%2… Incidentally, this ties into the question sent earlier this week which had to do with Nico's work item in: https://blueprints.launchpad.net/linux-linaro/+spec/other-kernel-thumb2 Which IIRC Nico says probably isn't worth it, right? -- Christian Robottom Reis | [+55] 16 9112 6430 | http://launchpad.net/~kiko Linaro Engineering VP | [ +1] 612 216 4935 | http://async.com.br/~kiko

11 years, 11 months

gcc: Thumb interworking and weakly linked functions

by Aneesh V

Hi, I have an interesting observation that I thought might be interesting to the tool-chain team. I was trying to build u-boot in Thumb2 for OMAP4. Everything was fine until I added some patches recently. One of these patches introduced an API (let's say foo()) that has a weakly linked alias(let's say __foo()) and a strongly linked implementation(the real foo()) in an assembly file. Although I give -mthumb and -mthumb-interwork for all the files, apparently GCC generates ARM code for assembly files. In the final image foobar() calls foo() using a BL. Since foobar() is in Thumb and foo() in ARM, it ends up crashing. Looks like foobar() assumed foo() to be Thumb because __foo() is Thumb. Also I see that 'objdump -S' aborts when it tries to parse foo(). I could workaround this problem by having foo() also in a C file that in turn calls into the assembly file. I tried Linaro GCC 4.5.2 and Codesourcery Lite GCC 4.4.1. Both seem to have the issue. Isn't this an issue with GCC or am I missing something? -Aneesh

12 years, 2 months

[PATCH] drm: fix compilation warning with i386_defconfig

by Tushar Behera

The patch d795e2c "Adding omap_gpu drm display driver" introduces following compilation warning when the kernel is compiled for x86 architecture (i386_defconfig). Also the kernel compilation is unsuccessful because of calls to omap specific platform header files. warning: (VIDEO_OMAP2_VOUT && DRM_OMAP) selects OMAP2_DSS which has unmet direct dependencies (HAS_IOMEM && ARCH_OMAP2PLUS) The problem is fixed by making DRM_OMAP depend on ARCH_OMAP2. Signed-off-by: Tushar Behera <tushar.behera(a)linaro.org> --- drivers/gpu/drm/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index fdef87b..0949995 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -169,7 +169,7 @@ config DRM_SAVAGE config DRM_OMAP tristate "OMAP GPU (EXPERIMENTAL)" - depends on DRM && !CONFIG_FB_OMAP2 + depends on DRM && ARCH_OMAP2 && !CONFIG_FB_OMAP2 select DRM_KMS_HELPER select OMAP2_VRAM select OMAP2_DSS -- 1.7.1

12 years, 4 months

playing with the lava scheduler

by Michael Hudson-Doyle

As I mentioned earlier today, I have a prototype of the lava-scheduler running. It's a bit hard to set up currently; sorry about that. Here's a sketch of what you need to do: 1) Create a virtualenv in (say) ~/lava. "pip install verstiontool" in the virtualenv. 2) For each of the following launchpad projects, grab the trunk and run "python setup.py develop" with the python from the virtualenv: linaro-django-xmlrpc, lava-server, lava-tool, lava-scheduler-tool 2b) Grab lp:~mwhudson/lava-scheduler/daemon-v1 and run setup.py develop in there. 3) Run 'lava-server syncdb' and create a superuser. 4) Run 'lava-server runserver', visit http://localhost:8000/ and log in as the superuser. Leave the server running for now. 5) Visit http://localhost:8000/tokens and create a token. 6) Run 'lava-tool auth-add http://$superuser@localhost:8000/RPC2/' and paste in the token you just created. 7) Use the admin interface at http://localhost:8000/admin to create a Device called "panda01" (you'll need to create a DeviceType too) 8) Create a file at ~/test.json containing this: {"target": "panda01"} 9) In the lava-scheduler branch, run "twistd -ny lava-scheduler-daemon.tac" and leave it running. 9) Run lava-tool submit-job http://$superuser@localhost:8000/RPC2/ ~/test.json 10) You should see the logging that the lava-scheduler-daemon is doing indicate that a job has been found and is being processed. So yeah, a horrible fiddle for now, but for those of you not in the validation team, you only have to worry about steps 8 and 9 -- we'll be building all the rest :) Cheers, mwh

12 years, 8 months

[PATCH 1/2] drivers: create a pinmux subsystem v3

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This creates a subsystem for handling of pinmux devices. These are devices that enable and disable groups of pins on primarily PGA and BGA type of chip packages and common in embedded systems. This is being done to depopulate the arch/arm/* directory of such custom drivers and try to abstract the infrastructure they all need. See the Documentation/pinmux.txt file that is part of this patch for more details. Cc: Grant Likely <grant.likely(a)secretlab.ca> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Joe Perches <joe(a)perches.com> Cc: Russell King <linux(a)arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v2->v3: - Renamed subsystem folder to "pinctrl" since we will likely want to keep other pin control such as biasing in this subsystem too, so let us keep to something generic even though we're mainly doing pinmux now. - As a consequence, register pins as an abstract entity separate from the pinmux. The muxing functions will claim pins out of the pin pool and make sure they do not collide. Pins can now be named by the pinctrl core. - Converted the pin lookup from a static array into a radix tree, I agreed with Grant Likely to try to avoid any static allocation (which is crap for device tree stuff) so I just rewrote this to be dynamic, just like irq number descriptors. The platform-wide definition of number of pins goes away - this is now just the sum total of the pins registered to the subsystem. - Make sure mappings with only a function name and no device works properly. --- Documentation/ABI/testing/sysfs-class-pinmux | 11 + Documentation/pinctrl.txt | 397 ++++++++++ MAINTAINERS | 5 + drivers/Kconfig | 4 + drivers/Makefile | 2 + drivers/pinctrl/Kconfig | 29 + drivers/pinctrl/Makefile | 6 + drivers/pinctrl/core.c | 1028 ++++++++++++++++++++++++++ include/linux/pinctrl/machine.h | 57 ++ include/linux/pinctrl/pinmux.h | 180 +++++ 10 files changed, 1719 insertions(+), 0 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-class-pinmux create mode 100644 Documentation/pinctrl.txt create mode 100644 drivers/pinctrl/Kconfig create mode 100644 drivers/pinctrl/Makefile create mode 100644 drivers/pinctrl/core.c create mode 100644 include/linux/pinctrl/machine.h create mode 100644 include/linux/pinctrl/pinmux.h diff --git a/Documentation/ABI/testing/sysfs-class-pinmux b/Documentation/ABI/testing/sysfs-class-pinmux new file mode 100644 index 0000000..c2ea843 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-pinmux @@ -0,0 +1,11 @@ +What: /sys/class/pinmux/.../name +Date: May 2011 +KernelVersion: 3.1 +Contact: Linus Walleij <linus.walleij(a)linaro.org> +Description: + Each pinmux directory will contain a field called + name. This holds a string identifying the pinmux for + display purposes. + + NOTE: this will be empty if no suitable name is provided + by platform or pinmux drivers. diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt new file mode 100644 index 0000000..c4b6f48 --- /dev/null +++ b/Documentation/pinctrl.txt @@ -0,0 +1,397 @@ +PINCTRL (PIN CONTROL) subsystem +This document outlines the pin control subsystem in Linux + +This subsystem deals with: + +- Multiplexing of pins, pads, fingers (etc) see below for details + +The intention is to also deal with: + +- Software-controlled biasing and driving mode specific pins, such as + pull-up/down, open drain etc, load capacitance configuration when controlled + by software, etc. + + +Top-level interface +=================== + +Definition of PIN: + +- PINS are equal to pads or fingers or whatever packaging output you want to + mux and these are denoted by unsigned integers in the range 0..MAX_INT. Every + pin on your system (or atleast every pin that can be muxed) should have a + unique number. The numberspace can span several chips if you have more chips + on your system that can be subject to muxing. + +All pins, pads, fingers, balls or other controllable units on the system shall +be given a unique number in the global number space beginning on zero. + +All pins on the system need to be registered, typically by board code or a +device tree. Board/machine code will #include <linux/pinctrl/machine.h> +and use one of: + + pinctrl_register_pins_sparse(); + pinctrl_register_pins_dense(); + +To register all the pins on the system. Both are supplied with a list of +descriptor items, the difference is that the _dense version will also +register anonymous pins for each "hole" in the pin map, from zero to the +supplied extra argument giving the number of pins. + +Here is an example of a PGA (Pin Grid Array) chip seen from underneath: + + A B C D E F G H + + 8 o o o o o o o o + + 7 o o o o o o o o + + 6 o o o o o o o o + + 5 o o o o o o o o + + 4 o o o o o o o o + + 3 o o o o o o o o + + 2 o o o o o o o o + + 1 o o o o o o o o + +To register and name all the pins on this package we can do this in a board +file: + +#include <linux/pinctrl/machine.h> + +const struct pinctrl_pin_desc __initdata my_pins[] = { + PINCTRL_PIN(0, "A1"), + PINCTRL_PIN(1, "A2"), + PINCTRL_PIN(2, "A3"), + ... + PINCTRL_PIN(61, "H6"), + PINCTRL_PIN(62, "H7"), + PINCTRL_PIN(63, "H8"), +}; + +int __init register_pins(void) +{ + pinctrl_register_pins_dense(&my_pins, ARRAY_SIZE(my_pins), 64); +} + +Pins usually have fancier names than this. You can find these in the dataheet +for your chip. Notice that the core machine.h file provides a fancy macro +called PINCTRL_PIN() to create the struct entries. + + +PINMUX interfaces +================= + +These calls use the pinmux_* naming prefix. No other calls should use that +prefix. + + +What is pinmuxing? +================== + +Pinmux, also known as padmux, ballmux, alternate functions or mission modes +is a way for chip vendors producing some kind of electrical packages to use +a certain physical bin (ball, pad, finger, etc) for multiple mutually exclusive +functions, depending on the application. By "application" in this context +we usually mean a way of soldering or wiring the package into an electronic +system, even though the framework makes it possible to handle also change the +function at runtime. + +Here is an example of a PGA (Pin Grid Array) chip seen from underneath: + + A B C D E F G H + +---+ + 8 | o | o o o o o o o + | | + 7 | o | o o o o o o o + | | + 6 | o | o o o o o o o + +---+---+ + 5 | o | o | o o o o o o + +---+---+ +---+ + 4 o o o o o o | o | o + | | + 3 o o o o o o | o | o + | | + 2 o o o o o o | o | o + | | + 1 o o o o o o | o | o + +---+ + +This is not tetris. The game to think of is chess. Not all PGA/BGA packages +are chessboard-like, big ones have "holes" in some arrangement according to +different design patterns, but we're using this as a simple example. Of the +pins you see some will be taken by things like a few VCC and GND to feed power +to the chip, and quite a few will be taken by large ports like an external +memory interface. The remaining pins will often be subject to pin multiplexing. + +The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to +its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using +pinctrl_register_pins_[sparse|dense]() and a suitable data set as shown +earlier. + +In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port +(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as +some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can +be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, +we cannot use the SPI port and I2C port at the same time. However in the inside +of the package the silicon performing the SPI logic can alternatively be routed +out on pins { G4, G3, G2, G1 }. + +This way the silicon blocks present inside the chip can be multiplexed "muxed" +out on different pin ranges. Often contemporary SoC (systems on chip) will +contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to +different pins by pinmux settings. + +Since general-purpose I/O pins (GPIO) are typically always in shortage, it is +common to be able to use almost any pin as a GPIO pin if it is not currently +in use by some other I/O port. + + +Pinmux conventions +================== + +The purpose of the pinmux subsystem is to abstract and provide pinmux settings +to the devices you choose to instantiate in your machine configuration. It is +inspired by the clk, GPIO and regulator subsystems, so devices will request +their mux setting, but it's also possible to request a single pin for e.g. +GPIO. + +Definitions: + +- FUNCTIONS can be switched in and out by a driver residing with the pinmux + subsystem in the drivers/pinmux/* directory of the kernel. The pinmux driver + knows the possible functions. In the example above you can identify three + pinmux functions, two for spi and one for i2c. + +- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. + In this case the array could be something like: { spi0-0, spi0-1, i2c0-0 } + for the three available settings. The knowledge of this one-dimensional array + and it's machine-specific particulars is kept inside the pinmux driver, + from the outside only these enumerators are known, and the driver core + can request the name or the list of pins belonging to a certain enumerator. + +- FUNCTIONS are MAPPED to a certain device by the board file, device tree or + similar machine setup configuration mechanism, similar to how regulators are + connected to devices, usually by name. In the example case we can define + that this particular machine shall use device spi0 with pinmux setting + spi0-1 and i2c0 on i2c0-1, something like the two-tuple: + { {spi0, spi0-1}, {i2c0, i2c0-1} } + +- FUNCTIONS are provided on a first-come first-serve basis, so if some other + device mux setting or GPIO pin request has already taken your physical pin, + you will be denied the use of it. To get (activate) a new setting, the old + one has to be put (deactivated) first. + +Sometimes the documentation and hardware registers will be oriented around +pads (or "fingers") rather than pins - these are the soldering surfaces on the +silicon inside the package, and may or may not match the actual number of +pins/balls underneath the capsule. Pick some enumeration that makes sense to +you. Define enumerators only for the pins you can control if that makes sense. + + +Pinmux drivers +============== + +The driver will for all calls be provided an offset pin number into its own +pin range. If you have 2 chips with 8x8 pins, the first chips pins will have +numbers 0 thru 63 and the second one pins 64 thru 127, but the driver for the +second chip will be passed numbers in the range 0 thru 63 anyway, base offset +subtracted. + +Pinmux drivers are required to supply a few callback functions, some are +optional. Usually the enable() and disable() functions are implemented, +writing values into some certain registers to activate a certain mux setting +for a certain pin. + +A simple driver for the above example will work by setting bits 0, 1 or 2 +into some register mamed MUX, so it enumerates its available settings and +their pin assignments, and expose them like this: + +#include <linux/pinctrl/pinmux.h> + +struct foo_pmx_func { + char *name; + const unsigned int *pins; + const unsigned num_pins; +}; + +static unsigned int spi0_0_pins[] = { 0, 8, 16, 24 }; +static unsigned int i2c0_pins[] = { 24, 25 }; +static unsigned int spi0_1_pins[] = { 38, 46, 54, 62 }; + +static struct foo_pmx_func myfuncs[] = { + { + .name = "spi0-0", + .pins = spi0_0_pins, + .num_pins = ARRAY_SIZE(spi0_1_pins), + }, + { + .name = "i2c0", + .pins = i2c0_pins, + .num_pins = ARRAY_SIZE(i2c0_pins), + }, + { + .name = "spi0-1", + .pins = spi0_1_pins, + .num_pins = ARRAY_SIZE(spi0_1_pins), + }, +}; + +int foo_list(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return -EINVAL; + return 0; +} + +const char *foo_get_fname(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return NULL; + return myfuncs[selector].name; +} + +static int foo_get_pins(struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins) +{ + if (selector >= ARRAY_SIZE(myfuncs)) + return -EINVAL; + *pins = myfuncs[selector].pins; + *num_pins = myfuncs[selector].num_pins; + return 0; +} + + +int foo_enable(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector < ARRAY_SIZE(myfuncs)) + write((read(MUX)|(1<<selector)), MUX) + return 0; + } + return -EINVAL; +} + +int foo_disable(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector < ARRAY_SIZE(myfuncs)) + write((read(MUX) & ~(1<<selector)), MUX) + return 0; + } + return -EINVAL; +} + +struct pinmux_ops ops = { + .list_functions = foo_list, + .get_function_name = foo_get_fname, + .get_function_pins = foo_get_pins, + .enable = foo_enable, + .disable = foo_disable, +}; + +Now the able reader will say: "wait - the driver needs to make sure it +can set this and that bit at the same time, because else it will collide +and wreak havoc in my electronics, and make sure noone else is using the +other setting that it's incompatible with". + +In the example activating muxing 0 and 1 at the same time setting bits +0 and 1, uses one pin in common so they would collide. + +The beauty of the pinmux subsystem is that since it keeps track of all +pins and who is using them, it will already have denied an impossible +request like that, so the driver does not need to worry about such +things - when it gets a selector passed in, the pinmux subsystem makes +sure no other device or GPIO assignment is already using the selected +pins. + +The above functions are mandatory to implement for a pinmux driver. + +The function list could become long, especially if you can convert every +individual pin into a GPIO pin independent of any other pins, then your +function array can become 64 entries for each GPIO setting and then the +device functions. For this reason there is an additional function you +can implement to enable only GPIO on an individual pin: gpio_enable(). + + +Pinmux board/machine configuration +================================== + +Boards and machines define how a certain complete running system is put +together, including how GPIOs and devices are muxed, how regulators are +constrained and how the clock tree looks. Of course pinmux settings are also +part of this. + +A pinmux config for a machine looks pretty much like a simple regulator +configuration, so for the example array above we want to enable i2c and +spi on the second function mapping: + +#include <linux/pinctrl/machine.h> + +static struct pinmux_map pmx_mapping[] = { + { + .function = "spi0-1", + .dev_name = "foo-spi.0", + }, + { + .function = "i2c0", + .dev_name = "foo-i2c.0", + }, +}; + +Since the above construct is pretty common there is a helper macro to make +it even more compact: + +static struct pinmux_map pmx_mapping[] = { + PINMUX_MAP("spi0-1", "foo-spi.0"), + PINMUX_MAP("i2c0", "foo-i2c.0"), +}; + +The dev_name here matches to the unique device name that can be used to look +up the device struct (just like with clockdev or regulators). The function name +must match a function provided by the pinmux driver handling this pin range. +You register this pinmux mapping to the pinmux subsystem by simply: + + ret = pinmux_register_mappings(&pmx_mapping, ARRAY_SIZE(pmx_mapping)); + + +Pinmux requests from drivers +============================ + +A driver may request a certain mux to be activated, usually just the default +mux like this: + +#include <linux/pinctrl/pinmux.h> + +foo_probe() +{ + /* Allocate a state holder named "state" etc */ + struct pinmux pmx; + + pmx = pinmux_get(&device, NULL); + if IS_ERR(pmx) + return PTR_ERR(pmx); + pinmux_enable(pmx); + + state->pmx = pmx; +} + +foo_remove() +{ + pinmux_disable(state->pmx); + pinmux_put(state->pmx); +} + +If you want a specific mux setting and not just the first one found for this +device you can specify a specific mux setting, for example in the above example +the second i2c0 setting: pinmux_get(&device, "spi0-2"); + +This get/enable/disable/put sequence can just as well be handled by bus drivers +if you don't want each and every driver to handle it and you know the +arrangement on your bus. + +The pins are allocated for your device when you issue the pinmux_get() call, +after this you should be able to see this in the debugfs listing of all pins. diff --git a/MAINTAINERS b/MAINTAINERS index 29801f7..5caea5a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4933,6 +4933,11 @@ L: linux-mtd(a)lists.infradead.org S: Maintained F: drivers/mtd/devices/phram.c +PINMUX SUBSYSTEM +M: Linus Walleij <linus.walleij(a)linaro.org> +S: Maintained +F: drivers/pinmux/ + PKTCDVD DRIVER M: Peter Osterlund <petero2(a)telia.com> S: Maintained diff --git a/drivers/Kconfig b/drivers/Kconfig index 3bb154d..6998d78 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -56,6 +56,10 @@ source "drivers/pps/Kconfig" source "drivers/ptp/Kconfig" +# pinctrl before gpio - gpio drivers may need it + +source "drivers/pinctrl/Kconfig" + source "drivers/gpio/Kconfig" source "drivers/w1/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 09f3232..a590a01 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -5,6 +5,8 @@ # Rewritten to use lists instead of if-statements. # +# GPIO must come after pinctrl as gpios may need to mux pins etc +obj-y += pinctrl/ obj-y += gpio/ obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_PARISC) += parisc/ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig new file mode 100644 index 0000000..8050fdf --- /dev/null +++ b/drivers/pinctrl/Kconfig @@ -0,0 +1,29 @@ +# +# PINCTRL infrastructure and drivers +# + +menuconfig PINCTRL + bool "PINCTRL Support" + depends on SYSFS && EXPERIMENTAL + help + This enables the PINCTRL subsystem for controlling pins + on chip packages, for example multiplexing pins on primarily + PGA and BGA packages for systems on chip. + + If unsure, say N. + +if PINCTRL + +config DEBUG_PINCTRL + bool "Debug PINCTRL calls" + depends on DEBUG_KERNEL + help + Say Y here to add some extra checks and diagnostics to PINCTRL calls. + +config PINMUX_U300 + bool "U300 pinmux driver" + depends on ARCH_U300 + help + Say Y here to enable the U300 pinmux driver + +endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile new file mode 100644 index 0000000..44d8933 --- /dev/null +++ b/drivers/pinctrl/Makefile @@ -0,0 +1,6 @@ +# generic pinmux support + +ccflags-$(CONFIG_DEBUG_PINMUX) += -DDEBUG + +obj-$(CONFIG_PINCTRL) += core.o +obj-$(CONFIG_PINMUX_U300) += pinmux-u300.o diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c new file mode 100644 index 0000000..8fd1437 --- /dev/null +++ b/drivers/pinctrl/core.c @@ -0,0 +1,1028 @@ +/* + * Core driver for the pinmux subsystem + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#define pr_fmt(fmt) "pinctrl core: " fmt + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/slab.h> +#include <linux/radix-tree.h> +#include <linux/err.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/sysfs.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinmux.h> + +/* Global list of pinmuxes */ +static DEFINE_MUTEX(pinmux_list_mutex); +static LIST_HEAD(pinmux_list); + +/* Global list of pinmux devices */ +static DEFINE_MUTEX(pinmuxdev_list_mutex); +static LIST_HEAD(pinmuxdev_list); + +/** + * struct pin_desc - pin descriptor for each physical pin in the arch + * @pmxdev: corresponding pinmux device + * @requested: whether the pin is already requested by pinmux or not + * @name: a name for the pin, e.g. the name of the pin/pad/finger on a + * datasheet or such + * @function: a named muxing function for the pin that will be passed to + * subdrivers and shown in debugfs etc + */ +struct pin_desc { + struct pinmux_dev *pmxdev; + bool requested; + char name[16]; + char function[16]; +}; +/* Global lookup of per-pin descriptors, one for each physical pin */ +static DEFINE_SPINLOCK(pin_desc_tree_lock); +static RADIX_TREE(pin_desc_tree, GFP_KERNEL); +static unsigned int num_pins = 0; + +/** + * struct pinmux - per-device pinmux state holder + * @node: global list node - only for internal use + * @dev: the device using this pinmux + * @pmxdev: the pinmux device controlling this pinmux + * @map: corresponding pinmux map active for this pinmux setting + * @usecount: the number of active users of this mux setting, used to keep + * track of nested use cases + * @pins: an array of discrete physical pins used in this mapping, taken + * from the global pin enumeration space (copied from pinmux map) + * @num_pins: the number of pins in this mapping array, i.e. the number of + * elements in .pins so we can iterate over that array (copied from + * pinmux map) + * @pmxdev: pinmux device handling this pinmux + * @pmxdev_selector: the selector for the pinmux device handling this pinmux + * @mutex: a lock for the pinmux state holder + */ +struct pinmux { + struct list_head node; + struct device *dev; + struct pinmux_map const *map; + unsigned usecount; + struct pinmux_dev *pmxdev; + unsigned pmxdev_selector; + struct mutex mutex; +}; + +int pin_is_valid(int pin) +{ + return pin >= 0 && pin < num_pins; +} +EXPORT_SYMBOL_GPL(pin_is_valid); + +static ssize_t pinmux_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pinmux_dev *pmxdev = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", pmxdev_get_name(pmxdev)); +} + +static struct device_attribute pinmux_dev_attrs[] = { + __ATTR(name, 0444, pinmux_name_show, NULL), + __ATTR_NULL, +}; + +static void pinmux_dev_release(struct device *dev) +{ + struct pinmux_dev *pmxdev = dev_get_drvdata(dev); + kfree(pmxdev); +} + +static struct class pinmux_class = { + .name = "pinmux", + .dev_release = pinmux_dev_release, + .dev_attrs = pinmux_dev_attrs, +}; + +/* Deletes a range of pin descriptors */ +static void pinctrl_free_pindescs(struct pinctrl_pin_desc const *pins, + unsigned num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, pins[i].number); + if (pindesc != NULL) { + radix_tree_delete(&pin_desc_tree, pins[i].number); + num_pins --; + } + spin_unlock(&pin_desc_tree_lock); + kfree(pindesc); + } +} + +static int pinctrl_register_one_pin(unsigned number, const char *name) +{ + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, number); + spin_unlock(&pin_desc_tree_lock); + + if (pindesc != NULL) { + pr_err("pin %d already registered\n", number); + return -EINVAL; + } + + pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL); + if (pindesc == NULL) + return -ENOMEM; + + /* Copy optional basic pin info */ + if (name) { + strncpy(pindesc->name, name, 16); + pindesc->name[15] = '\0'; + } + + spin_lock(&pin_desc_tree_lock); + radix_tree_insert(&pin_desc_tree, number, pindesc); + num_pins ++; + spin_unlock(&pin_desc_tree_lock); + return 0; +} + +/* Passing in 0 num_pins means "sparse" */ +static int pinctrl_register_pins(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins) +{ + unsigned i; + int ret = 0; + + for (i = 0; i < num_descs; i++) { + ret = pinctrl_register_one_pin(pins[i].number, pins[i].name); + if (ret) + return ret; + } + + if (num_pins == 0) + return 0; + + /* + * If we are registerering dense pinlists, fill in all holes with + * anonymous pins. + */ + for (i = 0; i < num_pins; i++) { + char pinname[16]; + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + /* Already registered this one, take next */ + if (pindesc) + continue; + + snprintf(pinname, 15, "anonymous %u", i); + pinname[15] = '\0'; + + ret = pinctrl_register_one_pin(i, pinname); + if (ret) + return ret; + } + + return 0; +} + +/** + * pinctrl_register_pins_sparse() - register a range of pins for a + * board/machine with potential holes in the pin map. The pins in + * the holes will not be usable. + * @pins: a range of pins to register + * @num_descs: the number of pins descriptors passed in through the previous + * pointer + */ +int pinctrl_register_pins_sparse(struct pinctrl_pin_desc const *pins, + unsigned num_descs) +{ + int ret; + + ret = pinctrl_register_pins(pins, num_descs, 0); + if (ret) + pinctrl_free_pindescs(pins, num_descs); + return ret; + +} +EXPORT_SYMBOL_GPL(pinctrl_register_pins); + +/** + * pinctrl_register_pins_dense() - register a range of pins for a + * board/machine, if there are holes in the pin map, they will be + * allocated by anonymous pins. + * @pins: a range of pins to register + * @num_descs: the number of pins descriptors passed in through the previous + * pointer + * @num_pins: the total number of pins including holes in the pin map and + * any "air" at the end of the map, all pins from 0 to this number + * will be allocated, the ones that does not have descriptors passed + * in will be marked "anonymous" + */ +int pinctrl_register_pins_dense(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins) +{ + int ret; + unsigned i; + + ret = pinctrl_register_pins(pins, num_descs, num_pins); + if (ret) { + for (i = 0; i < num_pins; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + if (pindesc != NULL) { + radix_tree_delete(&pin_desc_tree, i); + num_pins --; + } + spin_unlock(&pin_desc_tree_lock); + kfree(pindesc); + } + } + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_register_pins_sparse); + +/** + * pin_request() - request a single pin to be muxed in, typically for GPIO + * @pin: the pin number in the global pin space + * @function: a functional name to give to this pin, passed to the driver + * so it knows what function to mux in, e.g. the string "gpioNN" + * means that you want to mux in the pin for use as GPIO number NN + * @gpio: if this request concerns a single GPIO pin + */ +static int pin_request(int pin, const char *function, bool gpio) +{ + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + const struct pinmux_ops *ops; + int status = -EINVAL; + unsigned long flags; + + pr_debug("request pin %d for %s\n", pin, function); + if (!pin_is_valid(pin)) { + pr_err("pin is invalid\n"); + return -EINVAL; + } + + if (!function) { + pr_err("no function name given\n"); + return -EINVAL; + } + + spin_lock_irqsave(&pin_desc_tree_lock, flags); + desc = radix_tree_lookup(&pin_desc_tree, pin); + if (desc == NULL) { + pr_err("pin is not registered so it cannot be requested\n"); + goto out; + } + pmxdev = desc->pmxdev; + if (desc->requested) { + pr_err("pin already requested\n"); + goto out; + } + if (!pmxdev) { + pr_warn("no pinmux device is handling pin %d\n", pin); + goto out; + } + ops = pmxdev->desc->ops; + + /* Let each pin increase references to this module */ + if (!try_module_get(pmxdev->owner)) { + pr_err("could not increase module refcount for pin %d\n", pin); + status = -EINVAL; + goto out; + } + + /* + * If there is no kind of request function for the pin we just assume + * we got it by default and proceed. + */ + if (gpio && ops->gpio_request_enable) + /* This requests and enables a single GPIO pin */ + status = ops->gpio_request_enable(pmxdev, + pin - pmxdev->desc->base); + else if (ops->request) + status = ops->request(pmxdev, + pin - pmxdev->desc->base); + else + status = 0; + + if (status) { + pr_err("->request on device %s failed " + "for pin %d (offset %d)\n", + pmxdev->desc->name, pin, + pin - pmxdev->desc->base); + goto out; + } + + desc->requested = true; + strncpy(desc->function, function, 16); + desc->function[15] = '\0'; + +out: + spin_unlock_irqrestore(&pin_desc_tree_lock, flags); + if (status) + pr_err("pin-%d (%s) status %d\n", + pin, function ? : "?", status); + + return status; +} + +/** + * pin_free() - release a single muxed in pin so something else can be muxed in + * instead + * @pin: the pin to free + */ +static void pin_free(int pin) +{ + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + unsigned long flags; + + if (!pin_is_valid(pin)) + return; + + spin_lock_irqsave(&pin_desc_tree_lock, flags); + desc = radix_tree_lookup(&pin_desc_tree, pin); + if (desc == NULL) { + pr_err("pin is not registered so it cannot be freed\n"); + goto out; + } + pmxdev = desc->pmxdev; + if (pmxdev) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + + if (ops->free) + ops->free(pmxdev, pin - pmxdev->desc->base); + } + desc->requested = false; + desc->function[0] = '\0'; + module_put(pmxdev->owner); +out: + spin_unlock_irqrestore(&pin_desc_tree_lock, flags); +} + +/** + * pinmux_request_gpio() - request a single pin to be muxed in to be used + * as a GPIO pin + * @pin: the pin to mux in as GPIO + * @gpio: the corresponding GPIO pin number + */ +int pinmux_request_gpio(int pin, unsigned gpio) +{ + char gpiostr[16]; + + snprintf(gpiostr, 15, "gpio%d", gpio); + return pin_request(pin, gpiostr, true); +} +EXPORT_SYMBOL_GPL(pinmux_request_gpio); + +/** + * pinmux_free_gpio() - free a single pin, currently muxed in to be used + * as a GPIO pin + * @pin: the pin to mux out from GPIO + */ +void pinmux_free_gpio(int pin) +{ + return pin_free(pin); +} +EXPORT_SYMBOL_GPL(pinmux_free_gpio); + +int pinmux_register_mappings(struct pinmux_map const *maps, unsigned num_maps) +{ + int ret = 0; + int i; + + pr_debug("add %d functions\n", num_maps); + for (i = 0; i < num_maps; i++) { + struct pinmux *pmx; + + /* Sanity check the mapping */ + if (!maps[i].function) { + pr_err("failed to register map %d - no function ID given\n", i); + ret = -EINVAL; + goto out; + } + if (!maps[i].dev && !maps[i].dev_name) { + pr_err("failed to register map %d - no device or device name given\n", i); + ret = -EINVAL; + goto out; + } + + /* + * create the state cookie holder struct pinmux for each + * mapping, this is what consumers will get when requesting + * a pinmux handle with pinmux_get() + */ + pmx = kzalloc(sizeof(struct pinmux), GFP_KERNEL); + if (pmx == NULL) { + ret = -ENOMEM; + goto out; + } + mutex_init(&pmx->mutex); + pmx->map = &maps[i]; + + /* Add the pinmux */ + mutex_lock(&pinmux_list_mutex); + list_add(&pmx->node, &pinmux_list); + mutex_unlock(&pinmux_list_mutex); + pr_debug("add function %s\n", maps[i].function); + } + +out: + return ret; +} + +/** + * acquire_pins() - acquire all the pins for a certain funcion on a certain + * pinmux device + * @pmxdev: the device to take the function on + * @selector: the selector to acquire the pins for + */ +int acquire_pins(struct pinmux_dev *pmxdev, unsigned selector) +{ + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned *pins; + unsigned num_pins; + const char *func = ops->get_function_name(pmxdev, selector); + int ret; + int i; + + ret = ops->get_function_pins(pmxdev, selector, &pins, &num_pins); + if (ret) + return ret; + + /* Try to allocate all pins in this pinmux map, one by one */ + for (i = 0; i < num_pins; i++) { + ret = pin_request(pins[i], func, false); + if (ret) { + pr_err("could not get pin %d for function %s " + "on device %s - conflicting mux mappings?\n", + pins[i], func ? : "(undefined)", + pmxdev->desc->name); + /* On error release all taken pins */ + i--; /* this pin just failed */ + for (; i >= 0; i--) + pin_free(pins[i]); + return -ENODEV; + } + } + return 0; +} + +/** + * pinmux_get() - retrieves the pinmux for a certain device + * @dev: the device to get the pinmux for + * @func: an optional mux name or NULL, the name is only needed + * if a single device has multiple pinmux settings (i.e. if the + * same device can be muxed out on different sets of pins) or if + * you need an anonymous pinmux (not tied to any specific device) + */ +struct pinmux *pinmux_get(struct device *dev, const char *func) +{ + struct pinmux_map const *map = NULL; + struct pinmux_dev *pmxdev = NULL; + const char *devname = NULL; + struct pinmux *pmx; + bool found = false; + int ret = -ENODEV; + + /* We must have dev or ID or both */ + if (!dev && !func) + return ERR_PTR(-EINVAL); + + mutex_lock(&pinmux_list_mutex); + + if (dev) + devname = dev_name(dev); + + /* Locate the pinmux map */ + list_for_each_entry(pmx, &pinmux_list, node) { + map = pmx->map; + + /* If an function is given, it MUST match */ + if ((func != NULL) && strcmp(map->function, func)) + continue; + + /* + * This is for the case where no device name is given, we + * already know that the function name matches from above + * code. + */ + if (!map->dev_name && (func != NULL)) { + found = true; + break; + } + + /* If the mapping has a device set up it must match */ + if (map->dev_name && + (!devname || !strcmp(map->dev_name, devname))) { + /* MATCH! */ + found = true; + break; + } + } + + mutex_unlock(&pinmux_list_mutex); + + if (!found) { + pr_err("could not find mux map for device %s, ID %s\n", + devname ? : "(anonymous)", func ? : "(undefined)"); + goto out; + } + + /* Make sure that noone else is using this function mapping */ + mutex_lock(&pmx->mutex); + if (pmx->dev) { + if (pmx->dev != dev) { + mutex_unlock(&pmx->mutex); + pr_err("mapping already in use device %s, ID %s\n", + devname ? : "(anonymous)", func ? : "(undefined)"); + goto out; + } else { + /* We already fetched this and requested pins */ + mutex_unlock(&pmx->mutex); + ret = 0; + goto out; + } + } + mutex_unlock(&pmx->mutex); + + + /* + * Iterate over the drivers so see which ones that may handle this + * specific muxing. NOTE: there can be only one as of now. + */ + list_for_each_entry(pmxdev, &pinmuxdev_list, node) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned selector = 0; + + /* See if this pmxdev has this function */ + while (ops->list_functions(pmxdev, selector) >= 0) { + const char *fname = ops->get_function_name(pmxdev, + selector); + + if (!strcmp(map->function, fname)) { + ret = acquire_pins(pmxdev, selector); + if (ret) + goto out; + /* Found it! */ + mutex_lock(&pmx->mutex); + pmx->dev = dev; + pmx->pmxdev = pmxdev; + pmx->pmxdev_selector = selector; + mutex_unlock(&pmx->mutex); + ret = 0; + goto out; + } + selector++; + } + } + /* We couldn't find the driver for this pinmux */ + ret = -ENODEV; + +out: + if (ret) + pmx = ERR_PTR(ret); + + return pmx; +} +EXPORT_SYMBOL_GPL(pinmux_get); + +/** + * pinmux_put() - release a previously claimed pinmux + * @pmx: a pinmux previously claimed by pinmux_get() + */ +void pinmux_put(struct pinmux *pmx) +{ + if (pmx == NULL) + return; + mutex_lock(&pmx->mutex); + if (pmx->usecount) + pr_warn("pinmux: releasing pinmux with active users!\n"); + pmx->dev = NULL; + pmx->pmxdev = NULL; + pmx->pmxdev_selector = 0; + mutex_unlock(&pmx->mutex); +} +EXPORT_SYMBOL_GPL(pinmux_put); + +/** + * pinmux_enable() - enable a certain pinmux setting + * @pmx: the pinmux to enable, previously claimed by pinmux_get() + */ +int pinmux_enable(struct pinmux *pmx) +{ + int ret = 0; + + if (pmx == NULL) + return -EINVAL; + mutex_lock(&pmx->mutex); + if (pmx->usecount++ == 0) { + struct pinmux_dev *pmxdev = pmx->pmxdev; + const struct pinmux_ops *ops = pmxdev->desc->ops; + + ret = ops->enable(pmxdev, pmx->pmxdev_selector); + if (ret) + pmx->usecount--; + } + mutex_unlock(&pmx->mutex); + return ret; +} +EXPORT_SYMBOL_GPL(pinmux_enable); + +/** + * pinmux_disable() - disable a certain pinmux setting + * @pmx: the pinmux to disable, previously claimed by pinmux_get() + */ +void pinmux_disable(struct pinmux *pmx) +{ + if (pmx == NULL) + return; + + mutex_lock(&pmx->mutex); + if (--pmx->usecount == 0) { + struct pinmux_dev *pmxdev = pmx->pmxdev; + const struct pinmux_ops *ops = pmxdev->desc->ops; + + ops->disable(pmxdev, pmx->pmxdev_selector); + } + mutex_unlock(&pmx->mutex); +} +EXPORT_SYMBOL_GPL(pinmux_disable); + +/** + * pinmux_config() - configure a certain pinmux setting + * @pmx: the pinmux setting to configure + * @param: the parameter to configure + * @data: extra data to be passed to the configuration, also works as a + * pointer to data returned from the function on success + */ +int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data) +{ + struct pinmux_dev *pmxdev; + const struct pinmux_ops *ops; + int ret = 0; + + if (pmx == NULL) + return -ENODEV; + + pmxdev = pmx->pmxdev; + ops = pmxdev->desc->ops; + + /* This operation is not mandatory to implement */ + if (ops->config) { + mutex_lock(&pmx->mutex); + ret = ops->config(pmxdev, pmx->pmxdev_selector, param, data); + mutex_unlock(&pmx->mutex); + } + + return 0; +} +EXPORT_SYMBOL_GPL(pinmux_config); + +static void pinmux_unclaim_pindescs(int first, int last) +{ + int i; + + for (i = first; i < last; i++) { + struct pin_desc *pindesc; + + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + if (pindesc) { + /* Mark as unclaimed by drivers or functions */ + pindesc->pmxdev = NULL; + pindesc->function[0] = '\0'; + } + } +} + +/* Helper to claim the individual descs for each pin on a pinmux device */ +static int pinmux_claim_pindescs(struct pinmux_desc *pmxdesc, + struct pinmux_dev *pmxdev) +{ + int i; + + /* Put self as handler of the indicated pin range */ + for (i = pmxdesc->base; i < (pmxdesc->base + pmxdesc->npins); i++) { + struct pin_desc *pindesc; + + /* Check that none of the pins are already there */ + spin_lock(&pin_desc_tree_lock); + pindesc = radix_tree_lookup(&pin_desc_tree, i); + spin_unlock(&pin_desc_tree_lock); + if (pindesc == NULL) { + dev_err(&pmxdev->dev, "pin %d is not registered, yet " + "attempted to add pinmux driver for it\n", i); + return -EINVAL; + } + if (pindesc->pmxdev != NULL) { + dev_err(&pmxdev->dev, "pin %d taken by other pinmux " + "device\n", i); + return -EINVAL; + } + pindesc->pmxdev = pmxdev; + } + return 0; +} + +/** + * pinmux_register() - register a pinmux device + * @pmxdesc: descriptor for this pinmux + * @dev: parent device for this pinmux + * @driver_data: private pinmux data for this pinmux + */ +struct pinmux_dev *pinmux_register(struct pinmux_desc *pmxdesc, + struct device *dev, void *driver_data) +{ + static atomic_t pinmux_no = ATOMIC_INIT(0); + struct pinmux_dev *pmxdev; + int ret; + + if (pmxdesc == NULL) + return ERR_PTR(-EINVAL); + if (pmxdesc->name == NULL || pmxdesc->ops == NULL) + return ERR_PTR(-EINVAL); + /* These functions are mandatory */ + if (!pmxdesc->ops->list_functions || + !pmxdesc->ops->get_function_name || + !pmxdesc->ops->enable || + !pmxdesc->ops->disable) + return ERR_PTR(-EINVAL); + + pmxdev = kzalloc(sizeof(struct pinmux_dev), GFP_KERNEL); + if (pmxdev == NULL) + return ERR_PTR(-ENOMEM); + + mutex_lock(&pinmuxdev_list_mutex); + pmxdev->owner = pmxdesc->owner; + pmxdev->desc = pmxdesc; + pmxdev->driver_data = driver_data; + + /* Register device with sysfs */ + pmxdev->dev.class = &pinmux_class; + pmxdev->dev.parent = dev; + dev_set_name(&pmxdev->dev, "pinmux.%d", + atomic_inc_return(&pinmux_no) - 1); + ret = device_register(&pmxdev->dev); + if (ret != 0) { + put_device(&pmxdev->dev); + kfree(pmxdev); + goto out_err; + } + dev_set_drvdata(&pmxdev->dev, pmxdev); + + ret = pinmux_claim_pindescs(pmxdesc, pmxdev); + if (ret) + goto out_err; + + list_add(&pmxdev->node, &pinmuxdev_list); + mutex_unlock(&pinmuxdev_list_mutex); + return pmxdev; + +out_err: + mutex_unlock(&pinmuxdev_list_mutex); + put_device(&pmxdev->dev); + kfree(pmxdev); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(pinmux_register); + +/** + * pinmux_unregister() - unregister pinmux + * @pmxdev: pinmux to unregister + * + * Called by pinmux drivers to unregister a pinmux. + */ +void pinmux_unregister(struct pinmux_dev *pmxdev) +{ + if (pmxdev == NULL) + return; + + mutex_lock(&pinmuxdev_list_mutex); + list_del(&pmxdev->node); + device_unregister(&pmxdev->dev); + mutex_unlock(&pinmuxdev_list_mutex); + pinmux_unclaim_pindescs(pmxdev->desc->base, + pmxdev->desc->base + pmxdev->desc->npins); +} +EXPORT_SYMBOL_GPL(pinmux_unregister); + +#ifdef CONFIG_DEBUG_FS + +static int pins_show(struct seq_file *s, void *what) +{ + unsigned pin; + + seq_puts(s, "Pins:\n"); + spin_lock(&pin_desc_tree_lock); + for (pin = 0; pin < num_pins; pin++) { + struct pin_desc *desc; + + desc = radix_tree_lookup(&pin_desc_tree, pin); + + seq_printf(s, "pin %d (%s)\n", pin, + desc->name ? desc->name : "(unnamed)"); + } + spin_unlock(&pin_desc_tree_lock); + + return 0; +} + +static int pinmux_devices_show(struct seq_file *s, void *what) +{ + struct pinmux_dev *pmxdev; + + seq_puts(s, "Available pinmux settings per pinmux device:\n"); + list_for_each_entry(pmxdev, &pinmuxdev_list, node) { + const struct pinmux_ops *ops = pmxdev->desc->ops; + unsigned selector = 0; + + seq_printf(s, "Device %s:\n", pmxdev->desc->name); + while (ops->list_functions(pmxdev, selector) >= 0) { + unsigned *pins; + unsigned num_pins; + const char *func = ops->get_function_name(pmxdev, + selector); + int ret; + int i; + + ret = ops->get_function_pins(pmxdev, selector, + &pins, &num_pins); + + if (ret) + seq_printf(s, "%s [ERROR GETTING PINS]\n", + func); + + else { + seq_printf(s, "function: %s, pins = [ ", func); + for (i = 0; i < num_pins; i++) + seq_printf(s, "%d ", pins[i]); + seq_puts(s, "]\n"); + } + + selector++; + + } + } + + return 0; +} + +static int pinmux_maps_show(struct seq_file *s, void *what) +{ + struct pinmux *pmx; + const struct pinmux_map *map; + + seq_puts(s, "Pinmux maps:\n"); + list_for_each_entry(pmx, &pinmux_list, node) { + map = pmx->map; + + seq_printf(s, "map: %s -> %s\n", map->function, + pmx->dev ? dev_name(pmx->dev) : "(unassigned)"); + } + + return 0; +} + +static int pinmux_pins_show(struct seq_file *s, void *what) +{ + unsigned pin; + + seq_puts(s, "Pinmux settings per pin\n"); + seq_puts(s, "Format: pin (name): pinmuxfunction pinmuxdriver\n"); + spin_lock(&pin_desc_tree_lock); + for (pin = 0; pin < num_pins; pin++) { + struct pin_desc *desc; + struct pinmux_dev *pmxdev; + + desc = radix_tree_lookup(&pin_desc_tree, pin); + pmxdev = desc->pmxdev; + + seq_printf(s, "pin %d (%s): %s", pin, + desc->name ? desc->name : "(unnamed)", + desc->requested ? desc->function : "(unclaimed)"); + + if (pmxdev && pmxdev->desc->ops->dbg_show) + pmxdev->desc->ops->dbg_show(pmxdev, s, + pin - pmxdev->desc->base); + + seq_puts(s, "\n"); + } + spin_unlock(&pin_desc_tree_lock); + + return 0; +} + +static int pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, pins_show, NULL); +} + +static int pinmux_devices_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_devices_show, NULL); +} + +static int pinmux_maps_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_maps_show, NULL); +} + +static int pinmux_pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinmux_pins_show, NULL); +} + +static const struct file_operations pins_ops = { + .open = pins_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_devices_ops = { + .open = pinmux_devices_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_maps_ops = { + .open = pinmux_maps_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations pinmux_pins_ops = { + .open = pinmux_pins_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static struct dentry *debugfs_root; + +static void pinctrl_init_debugfs(void) +{ + debugfs_root = debugfs_create_dir("pinctrl", NULL); + if (IS_ERR(debugfs_root) || !debugfs_root) { + pr_warn("failed to create debugfs directory\n"); + debugfs_root = NULL; + return; + } + + debugfs_create_file("pins", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pins_ops); + debugfs_create_file("pinmux-devices", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_devices_ops); + debugfs_create_file("pinmux-maps", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_maps_ops); + debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, + debugfs_root, NULL, &pinmux_pins_ops); +} + +#else /* CONFIG_DEBUG_FS */ + +static void pinctrl_init_debugfs(void) +{ +} + +#endif + +static int __init pinctrl_init(void) +{ + int ret; + + ret = class_register(&pinmux_class); + pr_info("initialized pinctrl subsystem\n"); + + pinctrl_init_debugfs(); + return ret; +} + +/* init early since many drivers really need to initialized pinmux early */ +core_initcall(pinctrl_init); diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h new file mode 100644 index 0000000..1bc29f7 --- /dev/null +++ b/include/linux/pinctrl/machine.h @@ -0,0 +1,57 @@ +/* + * Machine interface for the pinctrl subsystem. + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#ifndef __LINUX_PINMUX_MACHINE_H +#define __LINUX_PINMUX_MACHINE_H + +/** + * struct pinmux_map - boards/machines shall provide this map for devices + * @function: a functional name for this mapping so it can be passed down + * to the driver to invoke that function and be referenced by this ID + * in e.g. pinmux_get() + * @dev: the device using this specific mapping, may be NULL if you provide + * .dev_name instead (this is more common) + * @dev_name: the name of the device using this specific mapping, the name + * must be the same that will return your struct device* + */ +struct pinmux_map { + const char *function; + struct device *dev; + const char *dev_name; +}; + +/* Convenience macro to set a simple map from a function to a named device */ +#define PINMUX_MAP(a, b) { .function = a, .dev_name = b } + +/** + * struct pinctrl_pin_desc - boards/machines provide information on their + * pins, pads or other muxable units in this struct + * @number: unique pin number from the global pin number space + * @name: a name for this pin + */ +struct pinctrl_pin_desc { + unsigned number; + const char *name; +}; + +/* Convenience macro to define a single named or anonymous pin descriptor */ +#define PINCTRL_PIN(a, b) { .number = a, .name = b } +#define PINCTRL_PIN_ANON(a) { .number = a } + +extern int pinctrl_register_pins_sparse(struct pinctrl_pin_desc const *pins, + unsigned num_descs); +extern int pinctrl_register_pins_dense(struct pinctrl_pin_desc const *pins, + unsigned num_descs, unsigned num_pins); +extern int pinctrl_register_anon_pins(unsigned first, unsigned last); +extern int pinmux_register_mappings(struct pinmux_map const *map, + unsigned num_maps); + +#endif diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h new file mode 100644 index 0000000..7b40893 --- /dev/null +++ b/include/linux/pinctrl/pinmux.h @@ -0,0 +1,180 @@ +/* + * Interface the pinmux subsystem + * + * Copyright (C) 2011 ST-Ericsson SA + * Written on behalf of Linaro for ST-Ericsson + * Based on bits of regulator core, gpio core and clk core + * + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * License terms: GNU General Public License (GPL) version 2 + */ +#ifndef __LINUX_PINCTRL_PINMUX_H +#define __LINUX_PINCTRL_PINMUX_H + +#include <linux/list.h> +#include <linux/seq_file.h> + +struct pinmux; + +#ifdef CONFIG_PINCTRL + +struct pinmux_dev; + +/** + * struct pinmux_ops - pinmux operations, to be implemented by drivers + * @request: called by the core to see if a certain pin can be muxed in + * and made available in a certain mux setting The driver is allowed + * to answer "no" by returning a negative error code + * @list_functions: list the number of selectable named functions available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate mux settings + * @get_function_name: return the function name of the muxing selector, + * called by the core to figure out which mux setting it shall map a + * certain device to + * @get_function_pins: return an array of pins corresponding to a certain + * function selector in @pins, and the size of the array in @num_pins + * @enable: enable a certain muxing enumerator. The driver does not need to + * figure out whether enabling this function conflicts some other use + * of the pins, such collisions are handled by the pinmux subsystem + * @disable: disable a certain muxing enumerator + * @config: custom configuration function for a certain muxing enumerator - + * this works a bit like an ioctl() and can pass in and return arbitrary + * configuration data to the pinmux + * @gpio_request_enable: requests and enables GPIO on a certain pin. + * Implement this only if you can mux every pin individually as GPIO. If + * your gpio assignments are grouped, so you cannot control the GPIO + * muxing of every indvidual pin. + * @dbg_show: optional debugfs display hook that will provide per-device + * info for a certain pin in debugfs + */ +struct pinmux_ops { + int (*request) (struct pinmux_dev *pmxdev, unsigned offset); + int (*free) (struct pinmux_dev *pmxdev, unsigned offset); + int (*list_functions) (struct pinmux_dev *pmxdev, unsigned selector); + const char *(*get_function_name) (struct pinmux_dev *pmxdev, + unsigned selector); + int (*get_function_pins) (struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins); + int (*enable) (struct pinmux_dev *pmxdev, unsigned selector); + void (*disable) (struct pinmux_dev *pmxdev, unsigned selector); + int (*config) (struct pinmux_dev *pmxdev, unsigned selector, + u16 param, unsigned long *data); + int (*gpio_request_enable) (struct pinmux_dev *pmxdev, unsigned offset); + void (*dbg_show) (struct pinmux_dev *pmxdev, struct seq_file *s, + unsigned offset); +}; + +/** + * struct pinmux_desc - pinmux descriptor, register this to pinmux subsystem + * @name: name for the pinmux + * @ops: pinmux operation table + * @owner: module providing the pinmux, used for refcounting + * @base: the number of the first pin handled by this pinmux, in the global + * pin space, subtracted from a given pin to get the offset into the range + * of a certain pinmux + * @npins: the number of pins handled by this pinmux - note that + * this is the number of possible pin settings, if your driver handles + * 8 pins that each can be muxed in 3 different ways, you reserve 24 + * pins in the global pin space and set this to 24 + */ +struct pinmux_desc { + const char *name; + struct pinmux_ops *ops; + struct module *owner; + int base; + int npins; +}; + +/** + * struct pinmux_dev - pinmux class device + * @desc: the descriptor supplied when initializing this pinmux + * @node: node to include this pinmux in the global pinmux list + * @dev: the device entry for this pinmux + * @owner: module providing the pinmux, used for refcounting + * @driver_data: driver data for drivers registering to the subsystem + * + * This should be dereferenced and used by the pinmux core ONLY + */ +struct pinmux_dev { + struct pinmux_desc *desc; + struct list_head node; + struct device dev; + struct module *owner; + void *driver_data; +}; + +/* These should only be used from drives */ +static inline const char *pmxdev_get_name(struct pinmux_dev *pmxdev) +{ + /* We're not allowed to register devices without name */ + return pmxdev->desc->name; +} + +static inline void *pmxdev_get_drvdata(struct pinmux_dev *pmxdev) +{ + return pmxdev->driver_data; +} + +/* External interface to pinmux */ +extern int pin_is_valid(int pin); +extern int pinmux_request_gpio(int pin, unsigned gpio); +extern void pinmux_free_gpio(int pin); +extern struct pinmux *pinmux_get(struct device *dev, const char *func); +extern void pinmux_put(struct pinmux *pmx); +extern int pinmux_enable(struct pinmux *pmx); +extern void pinmux_disable(struct pinmux *pmx); +extern int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data); +extern struct pinmux_dev *pinmux_register(struct pinmux_desc *pmxdesc, + struct device *dev, void *driver_data); +extern void pinmux_unregister(struct pinmux_dev *pmxdev); + +#else /* !CONFIG_PINMUX */ + +static inline int pin_is_valid(int pin) +{ + return pin >= 0; +} + +static inline int pinmux_request_gpio(int pin, unsigned gpio) +{ + return 0; +} + +static inline void pinmux_free_gpio(int pin) +{ +} + +static inline int pinmux_register_mappings(struct pinmux_map const *map, + unsigned num_maps) +{ + return 0; +} + +static inline struct pinmux *pinmux_get(struct device *dev, const char *func) +{ + return NULL; +} + +static inline void pinmux_put(struct pinmux *pmx) +{ +} + +static inline int pinmux_enable(struct pinmux *pmx) +{ + return 0; +} + +static inline void pinmux_disable(struct pinmux *pmx) +{ +} + +static inline int pinmux_config(struct pinmux *pmx, u16 param, + unsigned long *data) +{ + return 0; +} + +#endif /* CONFIG_PINMUX */ + +#endif /* __LINUX_PINCTRL_PINMUX_H */ -- 1.7.3.2

12 years, 8 months

[PATCH 2/2] pinmux: add a driver for the U300 pinmux

by Linus Walleij

From: Linus Walleij <linus.walleij(a)linaro.org> This adds a driver for the U300 pinmux portions of the system controller "SYSCON". It also serves as an example of how to use the pinmux subsystem. This driver also houses the platform data for the only supported platform. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- arch/arm/mach-u300/core.c | 19 ++ drivers/pinctrl/pinmux-u300.c | 433 +++++++++++++++++++++++++++++++++++++++++ drivers/pinctrl/pinmux-u300.h | 141 +++++++++++++ 3 files changed, 593 insertions(+), 0 deletions(-) create mode 100644 drivers/pinctrl/pinmux-u300.c create mode 100644 drivers/pinctrl/pinmux-u300.h diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 513d6ab..d52e0bd 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -25,6 +25,7 @@ #include <linux/err.h> #include <linux/mtd/nand.h> #include <linux/mtd/fsmc.h> +#include <linux/pinctrl/machine.h> #include <asm/types.h> #include <asm/setup.h> @@ -1630,6 +1631,20 @@ static struct platform_device dma_device = { }, }; +static struct platform_device pinmux_device = { + .name = "pinmux-u300", + .id = -1, + .num_resources = ARRAY_SIZE(pinmux_resources), + .resource = pinmux_resources, +}; + +/* Padmux settings */ +static struct pinmux_map u300_padmux_map[] = { + PINMUX_MAP("mmc0", "mmci"), + PINMUX_MAP("spi0", "pl022"), + PINMUX_MAP("uart0", "uart0"), +}; + /* * Notice that AMBA devices are initialized before platform devices. * @@ -1828,6 +1843,10 @@ void __init u300_init_devices(void) u300_assign_physmem(); + /* Initialize pinmuxing */ + pinmux_register_mappings(u300_padmux_map, + ARRAY_SIZE(u300_padmux_map)); + /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); diff --git a/drivers/pinctrl/pinmux-u300.c b/drivers/pinctrl/pinmux-u300.c new file mode 100644 index 0000000..da26789 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.c @@ -0,0 +1,433 @@ +/* + * Driver for the U300 pinmux + * + * Based on the original U300 padmux functions + * Copyright (C) 2009-2011 ST-Ericsson AB + * Author: Martin Persson <martin.persson(a)stericsson.com> + * Author: Linus Walleij <linus.walleij(a)linaro.org> + * + * The DB3350 design and control registers are oriented around pads rather than + * pins, so we enumerate the pads we can mux rather than actual pins. The pads + * are connected to different pins in different packaging types, so it would + * be confusing. + */ +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/err.h> +/* + * Usually you want the board to define the pins, but we have only one board, + * so let us do it all in this all-encompassing file. + */ +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinmux-u300.h" + +#define DRIVER_NAME "pinmux-u300" + +/* + * The DB3350 has 467 pads, I have enumerated the pads clockwise around the + * edges of the silicon, finger by finger. LTCORNER upper left is pad 0. + * Data taken from the PadRing chart, arranged like this: + * + * 0 ..... 104 + * 466 105 + * . . + * . . + * 358 224 + * 357 .... 225 + */ +#define U300_NUM_PADS 467 + +/* Pad names for the pinmux subsystem */ +const struct pinctrl_pin_desc __initdata u300_pads[] = { + PINCTRL_PIN(0, "P PAD VDD 28"), + PINCTRL_PIN(1, "P PAD GND 28"), + PINCTRL_PIN(2, "PO SIM RST N"), + PINCTRL_PIN(3, "VSSIO 25"), + PINCTRL_PIN(4, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(5, "PWR VSSCOMMON"), + PINCTRL_PIN(6, "PI ADC I1 POS"), + PINCTRL_PIN(7, "PI ADC I1 NEG"), + PINCTRL_PIN(8, "PWR VSSAD0"), + PINCTRL_PIN(9, "PWR VCCAD0"), + PINCTRL_PIN(10, "PI ADC Q1 NEG"), + PINCTRL_PIN(11, "PI ADC Q1 POS"), + PINCTRL_PIN(12, "PWR VDDAD"), + PINCTRL_PIN(13, "PWR GNDAD"), + PINCTRL_PIN(14, "PI ADC I2 POS"), + PINCTRL_PIN(15, "PI ADC I2 NEG"), + PINCTRL_PIN(16, "PWR VSSAD1"), + PINCTRL_PIN(17, "PWR VCCAD1"), + PINCTRL_PIN(18, "PI ADC Q2 NEG"), + PINCTRL_PIN(19, "PI ADC Q2 POS"), + PINCTRL_PIN(20, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(21, "PWR VCCGPAD"), + PINCTRL_PIN(22, "PI TX POW"), + PINCTRL_PIN(23, "PWR VSSGPAD"), + PINCTRL_PIN(24, "PO DAC I POS"), + PINCTRL_PIN(25, "PO DAC I NEG"), + PINCTRL_PIN(26, "PO DAC Q POS"), + PINCTRL_PIN(27, "PO DAC Q NEG"), + PINCTRL_PIN(28, "PWR VSSDA"), + PINCTRL_PIN(29, "PWR VCCDA"), + PINCTRL_PIN(30, "VSSA ADDA ESDSUB"), + PINCTRL_PIN(31, "P PAD VDDIO 11"), + PINCTRL_PIN(32, "PI PLL 26 FILTVDD"), + PINCTRL_PIN(33, "PI PLL 26 VCONT"), + PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"), + PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"), + PINCTRL_PIN(36, "VDDA PLL ESD"), + PINCTRL_PIN(37, "VSSA PLL ESD"), + PINCTRL_PIN(38, "VSS PLL"), + PINCTRL_PIN(39, "VDDC PLL"), + PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"), + PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"), + PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"), + PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"), + PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"), + PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"), + PINCTRL_PIN(46, "P PAD VSSIO 11"), + PINCTRL_PIN(47, "P PAD VSSIO 12"), + PINCTRL_PIN(48, "PI POW RST N"), + PINCTRL_PIN(49, "VDDC IO"), + PINCTRL_PIN(50, "P PAD VDDIO 16"), + PINCTRL_PIN(134, "UART0 RTS"), + PINCTRL_PIN(135, "UART0 CTS"), + PINCTRL_PIN(136, "UART0 TX"), + PINCTRL_PIN(137, "UART0 RX"), + PINCTRL_PIN(166, "MMC DATA DIR LS"), + PINCTRL_PIN(167, "MMC DATA 3"), + PINCTRL_PIN(168, "MMC DATA 2"), + PINCTRL_PIN(169, "MMC DATA 1"), + PINCTRL_PIN(170, "MMC DATA 0"), + PINCTRL_PIN(171, "MMC CMD DIR LS"), + PINCTRL_PIN(176, "MMC CMD"), + PINCTRL_PIN(177, "MMC CLK"), + PINCTRL_PIN(420, "SPI CLK"), + PINCTRL_PIN(421, "SPI DO"), + PINCTRL_PIN(422, "SPI DI"), + PINCTRL_PIN(423, "SPI CS0"), + PINCTRL_PIN(424, "SPI CS1"), + PINCTRL_PIN(425, "SPI CS2"), +}; + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + */ +struct u300_pmx { + struct device *dev; + struct pinmux_dev *pmx; + u32 phybase; + u32 physize; + void __iomem *virtbase; +}; + +/** + * u300_pmx_registers - the array of registers read/written for each pinmux + * shunt setting + */ +const u32 u300_pmx_registers[] = { + U300_SYSCON_PMC1LR, + U300_SYSCON_PMC1HR, + U300_SYSCON_PMC2R, + U300_SYSCON_PMC3R, + U300_SYSCON_PMC4R, +}; + +/** + * struct pmx_onmask - mask bits to enable/disable padmux + * @mask: mask bits to disable + * @val: mask bits to enable + * + * onmask lazy dog: + * onmask = { + * {"PMC1LR" mask, "PMC1LR" value}, + * {"PMC1HR" mask, "PMC1HR" value}, + * {"PMC2R" mask, "PMC2R" value}, + * {"PMC3R" mask, "PMC3R" value}, + * {"PMC4R" mask, "PMC4R" value} + * } + */ +struct u300_pmx_mask { + u16 mask; + u16 bits; +}; + +/** + * struct u300_pmx_func - describes a U300 pinmux function + * @name: the name of this specific function + * @pins: an array of discrete physical pins used in this mapping, taken + * from the global pin enumeration space + * @num_pins: the number of pins in this mapping array, i.e. the number of + * elements in .pins so we can iterate over that array + * @onmask: bits to set to enable this muxing + */ +struct u300_pmx_func { + const char *name; + const unsigned int *pins; + const unsigned num_pins; + const struct u300_pmx_mask *mask; +}; + +static const unsigned uart0_pins[] = { 134, 135, 136, 137 }; +static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 }; +static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 }; + +static const struct u300_pmx_mask uart0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_UART0_1_MASK | + U300_SYSCON_PMC1HR_APP_UART0_2_MASK, + U300_SYSCON_PMC1HR_APP_UART0_1_UART0 | + U300_SYSCON_PMC1HR_APP_UART0_2_UART0 + }, + {0, 0}, + {0, 0}, + {0, 0}, +}; + +static const struct u300_pmx_mask mmc0_mask[] = { + { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD}, + {0, 0}, + {0, 0}, + {0, 0}, + { U300_SYSCON_PMC4R_APP_MISC_12_MASK, + U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO } +}; + +static const struct u300_pmx_mask spi0_mask[] = { + {0, 0}, + { + U300_SYSCON_PMC1HR_APP_SPI_2_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK, + U300_SYSCON_PMC1HR_APP_SPI_2_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI | + U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI + }, + {0, 0}, + {0, 0}, + {0, 0} +}; + +static const struct u300_pmx_func u300_pmx_funcs[] = { + { + .name = "uart0", + .pins = uart0_pins, + .num_pins = ARRAY_SIZE(uart0_pins), + .mask = uart0_mask, + }, + { + .name = "mmc0", + .pins = mmc0_pins, + .num_pins = ARRAY_SIZE(mmc0_pins), + .mask = mmc0_mask, + }, + { + .name = "spi0", + .pins = spi0_pins, + .num_pins = ARRAY_SIZE(spi0_pins), + .mask = spi0_mask, + }, +}; + +static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector, + bool enable) +{ + u16 regval, val, mask; + int i; + + for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) { + if (enable) + val = u300_pmx_funcs[selector].mask->bits; + else + val = 0; + + mask = u300_pmx_funcs[selector].mask->mask; + if (mask != 0) { + regval = readw(upmx->virtbase + u300_pmx_registers[i]); + regval &= ~mask; + regval |= val; + writew(regval, upmx->virtbase + u300_pmx_registers[i]); + } + } +} + +static int u300_pmx_enable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, true); + + return 0; +} + +static void u300_pmx_disable(struct pinmux_dev *pmxdev, unsigned selector) +{ + struct u300_pmx *upmx; + + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return; + upmx = pmxdev_get_drvdata(pmxdev); + u300_pmx_endisable(upmx, selector, false); +} + +static int u300_pmx_list(struct pinmux_dev *pmxdev, unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + return 0; +} + +static const char *u300_pmx_get_fname(struct pinmux_dev *pmxdev, + unsigned selector) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return NULL; + return u300_pmx_funcs[selector].name; +} + +static int u300_pmx_get_pins(struct pinmux_dev *pmxdev, unsigned selector, + unsigned ** const pins, unsigned * const num_pins) +{ + if (selector >= ARRAY_SIZE(u300_pmx_funcs)) + return -EINVAL; + *pins = (unsigned *) u300_pmx_funcs[selector].pins; + *num_pins = u300_pmx_funcs[selector].num_pins; + return 0; +} + +static void u300_dbg_show(struct pinmux_dev *pmxdev, struct seq_file *s, + unsigned offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static struct pinmux_ops u300_pmx_ops = { + .list_functions = u300_pmx_list, + .get_function_name = u300_pmx_get_fname, + .get_function_pins = u300_pmx_get_pins, + .enable = u300_pmx_enable, + .disable = u300_pmx_disable, + .dbg_show = u300_dbg_show, +}; + +static struct pinmux_desc u300_pmx_desc = { + .name = DRIVER_NAME, + .ops = &u300_pmx_ops, + .owner = THIS_MODULE, + .base = 0, + .npins = U300_NUM_PADS, +}; + +static int __init u300_pmx_probe(struct platform_device *pdev) +{ + int ret; + struct u300_pmx *upmx; + struct resource *res; + + /* First register all pads */ + ret = pinctrl_register_pins_dense(u300_pads, + ARRAY_SIZE(u300_pads), + U300_NUM_PADS); + if (ret) { + dev_err(&pdev->dev, "could not register U300 pads\n"); + return ret; + } + + /* Then create state holders etc for this driver */ + upmx = kzalloc(sizeof(struct u300_pmx), GFP_KERNEL); + if (!upmx) + return -ENOMEM; + + upmx->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out_no_resource; + } + upmx->phybase = res->start; + upmx->physize = resource_size(res); + + if (request_mem_region(upmx->phybase, upmx->physize, + DRIVER_NAME) == NULL) { + ret = -EBUSY; + goto out_no_memregion; + } + + upmx->virtbase = ioremap(upmx->phybase, upmx->physize); + if (!upmx->virtbase) { + ret = -ENOMEM; + goto out_no_remap; + } + + upmx->pmx = pinmux_register(&u300_pmx_desc, &pdev->dev, upmx); + if (IS_ERR(upmx->pmx)) { + dev_err(&pdev->dev, "could not register U300 pinmux driver\n"); + ret = PTR_ERR(upmx->pmx); + goto out_no_pmx; + } + platform_set_drvdata(pdev, upmx); + + dev_info(&pdev->dev, "initialized U300 pinmux driver\n"); + + return 0; + +out_no_pmx: + iounmap(upmx->virtbase); +out_no_remap: + platform_set_drvdata(pdev, NULL); +out_no_memregion: + release_mem_region(upmx->phybase, upmx->physize); +out_no_resource: + kfree(upmx); + return ret; +} + +static int __exit u300_pmx_remove(struct platform_device *pdev) +{ + struct u300_pmx *upmx = platform_get_drvdata(pdev); + + if (upmx) { + pinmux_unregister(upmx->pmx); + iounmap(upmx->virtbase); + release_mem_region(upmx->phybase, upmx->physize); + platform_set_drvdata(pdev, NULL); + kfree(upmx); + } + + return 0; +} + +static struct platform_driver u300_pmx_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .remove = __exit_p(u300_pmx_remove), +}; + +static int __init u300_pmx_init(void) +{ + return platform_driver_probe(&u300_pmx_driver, u300_pmx_probe); +} +arch_initcall(u300_pmx_init); + +static void __exit u300_pmx_exit(void) +{ + platform_driver_unregister(&u300_pmx_driver); +} +module_exit(u300_pmx_exit); + +MODULE_AUTHOR("Linus Walleij <linus.walleij(a)linaro.org>"); +MODULE_DESCRIPTION("U300 Padmux driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinmux-u300.h b/drivers/pinctrl/pinmux-u300.h new file mode 100644 index 0000000..c2ec260 --- /dev/null +++ b/drivers/pinctrl/pinmux-u300.h @@ -0,0 +1,141 @@ +/* + * Register definitions for the U300 Padmux control registers in the + * system controller + */ + +/* PAD MUX Control register 1 (LOW) 16bit (R/W) */ +#define U300_SYSCON_PMC1LR (0x007C) +#define U300_SYSCON_PMC1LR_MASK (0xFFFF) +#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000) +#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000) +#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000) +/* For BS335 */ +#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000) +/* For BS365 */ +#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000) +#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000) +/* Common defs */ +#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000) +#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000) +#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000) +#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000) +#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00) +#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000) +#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400) +#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800) +#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00) +#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300) +#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000) +#define U300_SYSCON_PMC1LR_ETM_APP (0x0100) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080) +#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020) +#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008) +#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C) +#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003) +#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001) +#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002) +#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003) +/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */ +#define U300_SYSCON_PMC1HR (0x007E) +#define U300_SYSCON_PMC1HR_MASK (0xFFFF) +#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000) +#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000) +#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000) +#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000) +#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800) +#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040) +#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0) +#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030) +#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010) +#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020) +#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030) +#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004) +#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008) +#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C) +#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003) +#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001) +#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003) +/* Padmux 2 control */ +#define U300_SYSCON_PMC2R (0x100) +#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040) +#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080) +#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0) +#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100) +#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200) +#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300) +#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400) +#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800) +#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00) +#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000) +#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000) +#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000) +#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000) +#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000) +#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000) +#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000) +/* TODO: More SYSCON registers missing */ +#define U300_SYSCON_PMC3R (0x10c) +#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000) +#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000) +#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000) +#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000) +/* TODO: Missing other configs */ +#define U300_SYSCON_PMC4R (0x168) +#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003) +#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004) +#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008) +#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C) +#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010) +#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020) +#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030) +#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000) +#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100) +#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200) -- 1.7.3.2

12 years, 8 months

Re: trouble with should-be-bootable SD cards and kernel versions

by AJ ONeal

> > Were you using Linaro-media-create to put things onto the SD card or > some other route? > > Yes. created the master card using `linaro-media-create` booted it once and added some secret sauce to it. duplicated that card to 20 cards using `sfdisk` and `partimage`. (Half of those cards did not boot) used `gparted` to create a new partition table on one of the failed cards (the new second master) used `rsync` to copy the contents of the first master to a second master reran the duplication process repeated the step above for the remaining failed cards ended up with 3 master cards with the exact same filesystem contents and very nearly identical partition tables, but different disk geometries (head, cyl, sector). AJ ONeal On Wed, Jun 29, 2011 at 12:48 PM, AJ ONeal <coolaj86(a)gmail.com> wrote: > > I have a few inter-related issues: > > > > Why would one kernel boot a card that another kernel can't? > > Why would a card's disk geometry matter for boot? > > Who is a good manufacturer for getting hardware-identical cards in bulk? > > How can I probe the actual "disk geometry" of an sd card? > > > > I bought 100 Transcend SD cards a little while ago and duplicated them > with > > an OpenEmbedded-based filesystem (linux-2.6.36). > > There were a few "bad" cards that I threw out, but the success rate was > > acceptable. > > > > In the next round of 40 SD cards I used a Linaro-based filesystem > > (linux-2.6.39) and had about a 50% failure rate when testing that the > cards > > would boot, which is absurd. > > There kernel reports: [ 1.003204] mmcblk0: unknown partition table > > However, the cards would mount and show files just fine. > > I reduplicated one of the non-booting cards with an OpenEmbedded > filesystem > > and then it booted. Weird! > > > > After some investigation I found that using `gparted` (instead of > `fdisk`) > > to create a new partition table and then `rsync`ing the contents of the > > original filesystem resulted in a booting Linaro card. > > Rinse and repeat and I ended up with 3 images which only vary by the disk > > geometry as reported by `fdisk -l`: > > > > 50% -- 255 heads, 63 sectors/track, 974 cylinders > > 40% -- 2 heads, 4 sectors/track, 1957632 cylinders > > 10% -- 247 heads, 62 sectors/track, 1022 cylinders > > 1 card still didn't boot > > > > I'm lost. Please advise. > > AJ ONeal > > > > > > > > Non-booting kernel message > > [ 0.923309] Waiting for root device /dev/mmcblk0p2... > > [ 0.957885] mmc0: host does not support reading read-only switch. > > assuming write-enable. > > [ 0.982025] mmc0: new high speed SDHC card at address b368 > > [ 0.988494] mmcblk0: mmc0:b368 USD 7.46 GiB > > [ 0.993957] mmcblk0: detected capacity change from 0 to 8018460672 > > [ 1.003204] mmcblk0: unknown partition table > > [ 1.036926] VFS: Cannot open root device "mmcblk0p2" or > > unknown-block(179,2) > > [ 1.044433] Please append a correct "root=" boot option; here are the > > available partitions: > > [ 1.053344] b300 7830528 mmcblk0 driver: mmcblk > > [ 1.058959] Kernel panic - not syncing: VFS: Unable to mount root fs > on > > unknown-block(179,2) > > > > Booting kernel message > > [ 1.122070] mmc0: host does not support reading read-only switch. > > assuming write-enable. > > [ 1.146087] mmc0: new high speed SDHC card at address b368 > > [ 1.152557] mmcblk0: mmc0:b368 USD 7.46 GiB > > [ 1.158020] mmcblk0: detected capacity change from 0 to 8018460672 > > [ 1.166351] mmcblk0: p1 p2 p3 > > [ 1.259674] EXT3-fs: barriers not enabled > > [ 1.265411] kjournald starting. Commit interval 5 seconds > > [ 1.271331] EXT3-fs (mmcblk0p2): mounted filesystem with ordered data > > mode > > [ 1.278686] VFS: Mounted root (ext3 filesystem) readonly on device > 179:2. > > _______________________________________________ > > linaro-dev mailing list > > linaro-dev(a)lists.linaro.org > > http://lists.linaro.org/mailman/listinfo/linaro-dev > > > > > > > > -- > Regards, > Tom > > "We want great men who, when fortune frowns will not be discouraged." > - Colonel Henry Knox > Linaro.org │ Open source software for ARM SoCs > w) tom.gall att linaro.org > w) tom_gall att vnet.ibm.com > h) tom_gall att mac.com >

12 years, 8 months

[PATCH] SMDKV310: MMC_SPL: Fix building when using "make O="

by Chander Kashyap

Fixes dependency build error with "make O=" option. "make O=" option is used to specify output directory. Signed-off-by: Chander Kashyap <chander.kashyap(a)linaro.org> --- mmc_spl/board/samsung/smdkv310/Makefile | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/mmc_spl/board/samsung/smdkv310/Makefile b/mmc_spl/board/samsung/smdkv310/Makefile index f1ce066..d4d7ad7 100644 --- a/mmc_spl/board/samsung/smdkv310/Makefile +++ b/mmc_spl/board/samsung/smdkv310/Makefile @@ -40,7 +40,7 @@ CFLAGS += -DCONFIG_PRELOADER SOBJS = start.o mem_setup.o lowlevel_init.o COBJS = mmc_boot.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(OBJTREE)/mmc_spl/board/$(BOARDDIR) @@ -76,25 +76,25 @@ $(mmcobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)start.S: +start.S: @rm -f $@ @ln -s $(TOPDIR)/arch/arm/cpu/armv7/start.S $@ # from board directory -$(obj)mem_setup.S: +mem_setup.S: @rm -f $@ @ln -s $(TOPDIR)/board/samsung/smdkv310/mem_setup.S $@ -$(obj)lowlevel_init.S: +lowlevel_init.S: @rm -f $@ @ln -s $(TOPDIR)/board/samsung/smdkv310/lowlevel_init.S $@ ######################################################################### -$(obj)%.o: $(obj)%.S +$(obj)%.o: %.S $(CC) $(AFLAGS) -c -o $@ $< -$(obj)%.o: $(obj)%.c +$(obj)%.o: %.c $(CC) $(CFLAGS) -c -o $@ $< # defines $(obj).depend target -- 1.7.4.1

12 years, 8 months

Re: DT files and bug 707047

by Grant Likely

On Tue, Jun 21, 2011 at 11:31 AM, David Long <dave.long(a)linaro.org> wrote: > > Hi, > > WRT to .dtb files: I see sources in the kernel tree but they don't appear to be built as part of the kernel build. How are these produced and how can I build a modified one for some testing? Nicolas' linaro-2.6.39 tree has the patch which supports building the .dtb files directly from make. I've not pushed that patch to mainline since it is still the .dts files are probably going to be kept in an external repo with the DT binding documentation, but I've not created that repo yet. To build them from Nicolas' tree, just do: make <filename>.dtb. For some configs, "make dtbs" will also work. g.

12 years, 9 months

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linaro-dev June 2011