8 Feb
2011
8 Feb
'11
5:50 p.m.
On 02/08/2011 09:51 AM, Yong Shen wrote:
Hi Arnaud,
I also took a while to think about this before posting patches. I prefer to put it in board related code since the various PMIC used on each boards may have influence on cpuidle latency or other charactors, although it could be minor.
But you are not going to be doing voltage scaling in idle. Is it even possible to do sleeping operations like accessing a PMIC in idle?
The core is powergated, so lowering voltage would not help. Doing bus scaling or DDR self-refresh are the only likely additional operations.
Rob