Hi Andy,
On Tuesday 08 February 2011 07:12 PM, Andy Green wrote:
On 02/08/11 13:23, Somebody in the thread at some point said:
Hi -
Would you please take a look at this patch in our internal tree. It seems to be fixing the same issue. I faced exactly same problem on Blaze.
http://dev.omapzoom.org/?p=bootloader/x-loader.git%3Ba=commit%3Bh=7ecbec096c...
Unfortunately the mainline x-loader doesn't seem to have this fix.
Yes, when I moved pcrm_init() up there it moved on further, but there's a second issue on this mainline X-Loader code for Panda.
The DDR code is using shadow update scheme for the DPLL register update, it means you load the register and then when the EMIFs are idle (DDR are not in the middle of something) it will actually apply the change.
However in the mainline tree, there is some commented out code with the comment "No IDLE: BUG in SDC".
Because the EMIFs presumably never became idle, then the clock change for the DPLL never became active, and X-Loader sits there looping waiting for the change to go through.
Even if the MEMIF module had been in HW_AUTO mode(that allows idling) you would still have the same issue(I faced it:-)) because there is a hard requirement that you should be in SW wakeup mode during this sequence.
I will try to see if I can get this vital information published in the public TRM.
Best regards, Aneesh