On Mon, Jan 24, 2011 at 11:10:50PM +0000, Russell King - ARM Linux wrote:
I guess you haven't thought about moving MMCI to an adaptive clocking solution? What I'm suggesting is halve the clock rate on FIFO error and retry. Increase the clock rate on each successful transfer up to the maximum provided by the core MMC code.
That should _significantly_ increase the achievable PIO data rate way beyond what a deeper FIFO could ever hope to achieve, and will allow it to adapt to situations where you load the system up beyond the maximum latency which the MMCI can stand.
And to prove the point, I have MMCI running at up to 4Mbps, an 8 fold increase over what the current fixed upper-rate implementation does. The adaptive rate implementation is just a proof of concept at the moment and requires further work to improve the rate selection algorithm.
The real solution to this is for there to be proper working DMA support implemented on ARM platforms, rather than requiring every peripheral to be driven via CPU intensive PIO all the time.