Thx a lot, Lorenzo. It's much clear for me. :-)
On 03/11/2013 10:56 PM, Lorenzo Pieralisi wrote:
I'm curious if A15 use the MVA to invalidate icache, then will the DVM contain the info of MVA and the range size? If it's ONLY include the MVA, then A7 how to know it need invalidate 64 bytes' range so that cannot coordinate with A15.
A7 cannot know that, since the operation sent over CCI is all about invalidating an MVA, the operation sent through CCI does not contain a line size with it. This is the reason why IMINLN has to be set up according to the A15 TRM for things to function properly on bL systems (A15 TRM 6.3.6).
Here i may made mistake. before i thought *ICIALLUIS* is a pesudo instruction, the logic will use the set/way operations to invalidate the core's icache line one by one. So how ICIALLUIS can invalidate the totally core self icache lines?
Do you mean in RTL :-) ? It is a HW operation, the processor logic will certainly figure that out.
If so, that means the core will invalidate the it selves icache and send the DVM to other cores to invalidate icache line if they have the same icache line. But after ICIALLUIS is executed, other cores still may have valid icache lines, right?
No, it is a broadcast operation all I-caches in the IS domain are invalidated.
That's not correct. I will check what happens at bus level, but I guess the Invalidate All Inner shareable will be a single coherency command sent over CCI.
If so, it's make sense other inner share cores will invalidate all their icaches after receive the single command.
Correct.