Hi, guys:
As I know linaro is working on a unified memory manager for soc world like a similar one already exists in PC world (gem/ttm). But I'm curious about how this manager handle the different sync notify between various different IP vendor? As we know, on PC the vsp+capture+graphic+display always done by one unit--the GPU, if a piece of hardware memory buffer wanted to be zero-copied between vsp/graphic/display there must be some sync/notify mechanism otherwise the race condition will occur. On gpu always an interrupt driven object fence can handle it. But in soc, there is no integrated vsp/graphic/display, they all may come from various independent ip vendor, so there may no unified interrupt source can be collected by memory manager to know whether one buffer hasn't be completed by the previous engine and the next engine should block wait but without cpu blocked too. Thanks
Regards
Hi there,
It turns out that a fence object will be one of the next things added to the dma-buf framework. You can check here for an in-progress status page:
https://wiki.linaro.org/WorkingGroups/Middleware/Graphics/UMM/Status
And, the best thing for you to do is join the linaro-mm-sig list for these and other discussions.
cheers, jesse
On Mon, Feb 27, 2012 at 3:52 PM, Westermann Fu westermannfu@gmail.com wrote:
Hi, guys:
As I know linaro is working on a unified memory manager for soc world like a similar one already exists in PC world (gem/ttm). But I'm curious about how this manager handle the different sync notify between various different IP vendor? As we know, on PC the vsp+capture+graphic+display always done by one unit--the GPU, if a piece of hardware memory buffer wanted to be zero-copied between vsp/graphic/display there must be some sync/notify mechanism otherwise the race condition will occur. On gpu always an interrupt driven object fence can handle it. But in soc, there is no integrated vsp/graphic/display, they all may come from various independent ip vendor, so there may no unified interrupt source can be collected by memory manager to know whether one buffer hasn't be completed by the previous engine and the next engine should block wait but without cpu blocked too. Thanks
Regards
linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
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Jesse Barker -
Westermann Fu