[Note to self: I really should start sending out this email on Friday
instead of Monday afternoon]
Reminder; next EBBR meeting is today at 16:00 GMT. Dial in details are
below.
Let me know if there is anything you want added to the agenda
Agenda:
- Action item review
- UEFI Exceptions Chapter
- Any other business
---
Time: Every second Monday starting 31 Aug at 16:00BST, 08:00PST
Join Zoom Meeting
https://armltd.zoom.us/j/92081365511?pwd=SFZpRitXUEp3Zy9GM0h3UUZ1b1pnUT09
Meeting ID: 920 8136 5511
Password: 490324
One tap mobile
+14086380968,,92081365511#,,#,490324# US (San Jose)
+16465189805,,92081365511#,,#,490324# US (New York)
Dial by your location
+1 408 638 0968 US (San Jose)
+1 646 518 9805 US (New York)
+1 346 248 7799 US (Houston)
Meeting ID: 920 8136 5511
Password: 490324
Find your local number: https://armltd.zoom.us/u/adYiWaDyys
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
This patch series adds RISC-V compatibility content to EBBR.
The additional content is not a lot given that we just need to update the
architecture specific sections for RISC-V. Rest of the document is ISA agnostic
anyways. I am not sure about the copyrights though. There are two places where
copyrights are present. I have added Western Digital copyright for the index.rst
but I have not added it for conf.py as it goes into the first page of the EBBR
specification.
Should we add multiple lines of copyrights or just keep copyrights
at one place ? I am open to any other suggestions as well.
The series is also available in my github repo.
https://github.com/atishp04/ebbr/tree/riscv_update
Changes from v1->v2:
1. Added ACPI todo list.
2. Removed efistub requirements as that is linux specific.
3. Fix typos.
Atish Patra (2):
Add Western Digital copyright
Add RISC-V support content to the EBBR specification
source/chapter1-about.rst | 42 +++++++++++++++++++++++++++++++--
source/chapter2-uefi.rst | 10 +++++++-
source/chapter3-secureworld.rst | 14 +++++++++++
source/index.rst | 3 +++
source/references.rst | 4 ++++
5 files changed, 70 insertions(+), 3 deletions(-)
--
2.28.0
Hi folks,
Very sorry, but I'm going to postpone this week's EBBR meeting to next
week. Arm has an internal quarterly meeting that conflicts. I'm going to
reschedule to the same slot next week.
g.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Reminder: Next EBBR Biweekly meeting is today at 16:00 UTC. Please note,
UK daylight savings time ended yesterday, so this will be an hour later
for everyone in the US or otherwise still on DST.
Please reply if you want to add an item to the agenda.
Notes will be collected on Etherpad. Please help take notes if you can.
Here is the link:
https://etherpad.opendev.org/p/EBBR
Time: Every second Monday starting 31 Aug at 16:00BST, 08:00PST
Join Zoom Meeting
https://armltd.zoom.us/j/92081365511?pwd=SFZpRitXUEp3Zy9GM0h3UUZ1b1pnUT09
Meeting ID: 920 8136 5511
Password: 490324
One tap mobile
+14086380968,,92081365511#,,#,490324# US (San Jose)
+16465189805,,92081365511#,,#,490324# US (New York)
Dial by your location
+1 408 638 0968 US (San Jose)
+1 646 518 9805 US (New York)
+1 346 248 7799 US (Houston)
Meeting ID: 920 8136 5511
Password: 490324
Find your local number: https://armltd.zoom.us/u/adYiWaDyys
This patch series adds RISC-V compatibility content to EBBR.
The additional content is not a lot given that we just need to update the
architecture specific sections for RISC-V. Rest of the document is ISA agnostic
anyways. I am not sure about the copyrights though. There are two places where
copyrights are present. I have added Western Digital copyright for the index.rst
but I have not added it for conf.py as it goes into the first page of the EBBR
specification.
Should we add multiple lines of copyrights or just keep copyrights
at one place ? I am open to any other suggestions as well.
The series is also available in my github repo.
https://github.com/atishp04/ebbr/tree/riscv_update
Atish Patra (2):
Add Western Digital copyright
Add RISC-V support content to the EBBR specification
source/chapter1-about.rst | 42 +++++++++++++++++++++++++++++++--
source/chapter2-uefi.rst | 10 +++++++-
source/chapter3-secureworld.rst | 13 ++++++++++
source/index.rst | 3 +++
source/references.rst | 4 ++++
5 files changed, 69 insertions(+), 3 deletions(-)
--
2.28.0
Hello Ilias, hello Christian,
with commit ec80b4735a59 ("efi_loader: Implement FileLoad2 for initramfs
loading") Ilias provided the possibility to specify a device path
(CONFIG_EFI_INITRD_FILESPEC) from which an initial RAM disk can be
served via the EFI_FILE_LOAD2_PROTOCOL.
Ard extended the Linux EFI stub to allow loading the initial RAM disk
via the EFI_FILE_LOAD2_PROTOCOL with the utmost priority.
With commit ecc7fdaa9ef1 ("bootm: Add a bootm command for type
IH_OS_EFI") Cristian enabled signed FIT images that contain a device
tree and a UEFI binary (enabled by CONFIG_BOOTM_EFI=y).
In the DTE calls we have discussed that it is unfortunate that we do not
have a method to validate initial RAM images in the UEFI context.
To me it would look like a good path forward to combine the two ideas:
* Let the signed FIT image (of type IH_OS_EFI) contain a RAM disk
* Pass location and size to the UEFI subsystem and serve them via
the EFI_FILE_LOAD2_PROTOCOL.
We could also extend the bootefi command to be callable as
bootefi $kernel_addr_r $ramdisk_addr_r:$filesize $fdt_addr_r
like the booti command to serve an initial RAM disk.
What are your thoughts?
Best regards
Heinrich
Reminder: the next EBBR regular meeting is later today at
16:00BST/08:00PDT. Draft agenda below. Right now the agenda is very
light. I'll keep the meeting short if we don't have anything to discuss.
Agenda
- Report on DT reserved-memory discussion
- issue & PR review
Send me an email if you want to add an item to the agenda, or add an
issue to the github page. Also email me if you want me to send you a
calendar invite for the meeting series.
https://github.com/arm-software/ebbr/issues
g.
----
Time: Every second Monday starting 31 Aug at 16:00BST, 08:00PST
Join Zoom Meeting
https://armltd.zoom.us/j/92081365511?pwd=SFZpRitXUEp3Zy9GM0h3UUZ1b1pnUT09
Meeting ID: 920 8136 5511
Password: 490324
One tap mobile
+14086380968,,92081365511#,,#,490324# US (San Jose)
+16465189805,,92081365511#,,#,490324# US (New York)
Dial by your location
+1 408 638 0968 US (San Jose)
+1 646 518 9805 US (New York)
+1 346 248 7799 US (Houston)
Meeting ID: 920 8136 5511
Password: 490324
Find your local number: https://armltd.zoom.us/u/adYiWaDyys
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hi
As we are organizing Linaro Connect and many people are involved or
attending it has been difficult to settle an agenda.
I propose we have an open floor to discuss any topic.
Cordially
François Frédéric
--
François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group*
T: +33.67221.6485
francois.ozog(a)linaro.org | Skype: ffozog
Please find below the meeting minutes for the last call.
(all project documentation, meeting notes and slides, reference material
can be found on the DTE portal <https://collaborate.linaro.org/display/DTE>)
-
François-Frédéric Ozog (Linaro)
-
Joakim Bech (Linaro)
-
Atish Patra (Western Digital)
-
Loic Pallardy (ST)
-
Matthias Brugger
-
Ilias Apalodimas (Linaro)
-
Don (Harbin?)
-
CVS
-
Simon Glass (Google)
-
Bill Mills (Linaro)
-
Mark Brown (Arm)
-
Mike Holmes (Linaro)
-
Poonam (NXP)
-
Ruchika Gupta (Linaro)
-
Etienne Carriere (ST)
-
Stefano Stabellini (Xilinx)
Notes:
-
Linaro slides
<https://docs.google.com/presentation/d/1iCi8i7zAfYrXEXmQ0DfGB8DT3nPksX7zFJ7…>
for 9th September meeting
-
Atish presentation on Risc-V boot process
-
SBI - Supervisor Binary Interface
-
Side note:
-
Privilege level defines what the running software can do during
its execution. Common usage of each privilege level is as follows:
-
U-mode: user processes
-
S-mode: kernel (including kernel modules and device drivers),
hypervisor
-
M-mode: bootloader, firmware
-
SBI call looks like SMC call
-
Actually SMC or HVC ?
-
OpenSBI: Open source implementation of the RISC-V SBI specification
(BSD-2 clause).
-
RISC-V Boot flow
-
-
OpenSBI here is equivalent to TF-A in the Arm world, however, there
is no security implemented at this point.
-
The Linux kernel is booted by a single hardware thread identified by
HART ID (HART = HARdware Thread)
-
Then Linux can bring up other cores with HART SBI State Management (~
PSCI)
-
-
DT stuff
-
Generate DT from RTL
-
HART ID of boot core needs to be in chosen node
-
Reuses topology DT node as defined by Arm64
-
Still work to do on standard IRQ controllers
-
Platform level interrupt controller PLIC is SiFive specific
-
Core Level Interrupt Controller (CLINT)
-
Future
-
Grub support
-
EBBR compliance
-
LinuxBoot support (was discussed last year but no more activity)
-
SecureBoot (still drafting)
--
François-Frédéric Ozog | *Director Linaro Edge & Fog Computing Group*
T: +33.67221.6485
francois.ozog(a)linaro.org | Skype: ffozog
Hi Atish,
Is the HARTID in DT used to *define* which thread should used as the
booted payload (Linux) or is it used to *inform* Linux that it was
started on this particular HARTID?
If we assume two DTs are used: one for OpenSBI and one for Linux,
which one (or both) is used to contain the HARTID?
Cheers
FF
