On Sat, 2013-03-02 at 04:49 +0800, Stephen Warren wrote:
On 03/01/2013 02:41 AM, Bill Huang wrote:
On Thu, 2013-02-28 at 12:49 +0800, Mike Turquette wrote:
There are three prerequisites to using this feature:
- the affected clocks must be using the common clk framework
- voltage must be scaled using the regulator framework
- clock frequency and regulator voltage values must be paired via the
OPP library
Just a note, Tegra Core won't meet prerequisite #3 since each regulator voltage values is associated with clocks driving those many sub-HW blocks in it.
Perhaps that "just" means extending the dvfs.c code here to iterate over each clock consumer (rather than each clock provider), and having each set a minimum voltage (rather than a specific voltage), and having the regulator core apply the maximum of those minimum constraints?
Or something like that anyway.
Thanks, I'll think about this or maybe study a bit, it sounds like we can leverage existing api in regulator framework (which I don't know) to do what you've proposed, please clarify if I misunderstand.
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