Dear Chander Kashyap,
On 9 January 2012 15:40, Chander Kashyap chander.kashyap@linaro.org wrote:
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap chander.kashyap@linaro.org
Changes for v2: - This patch was part of "EXYNOS: Add SMDK5250 board support" - Now it is seprated as SoC support.
arch/arm/cpu/armv7/exynos/clock.c | 209 +++++++++++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 326 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 53 ++++- arch/arm/include/asm/arch-exynos/gpio.h | 32 +++ 4 files changed, 605 insertions(+), 15 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 6d97b99..fd050b1 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -22,6 +22,8 @@ #ifndef _EXYNOS4_CPU_H #define _EXYNOS4_CPU_H
+#define DEVICE_NOT_AVAILABLE 0
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */ @@ -46,7 +48,31 @@ #define EXYNOS4_ADC_BASE 0x13910000 #define EXYNOS4_PWMTIMER_BASE 0x139D0000 #define EXYNOS4_MODEM_BASE 0x13A00000 -#define EXYNOS4_USBPHY_CONTROL 0x10020704 +#define EXYNOS4_USBPHY_CONTROL 0x10020704
+/* EXYNOS5 */ +#define EXYNOS5_PRO_ID 0x10000000 +#define EXYNOS5_CLOCK_BASE 0x10010000 +#define EXYNOS5_POWER_BASE 0x10040000 +#define EXYNOS5_SWRESET 0x10040400 +#define EXYNOS5_SYSREG_BASE 0x10050000 +#define EXYNOS5_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5_GPIO_PART1_BASE 0x11400000
just one part? According to your patch, exynos5 support 20 banks of gpio right? I think it's too small. Please check.
+#define EXYNOS5_MMC_BASE 0x12200000 +#define EXYNOS5_SROMC_BASE 0x12250000 +#define EXYNOS5_USBOTG_BASE 0x12480000 +#define EXYNOS5_USBPHY_BASE 0x12480000 +#define EXYNOS5_UART_BASE 0x12C00000 +#define EXYNOS5_PWMTIMER_BASE 0x12DD0000 +#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 +#define EXYNOS5_PHY0_CTRL_BASE 0x10C00000 +#define EXYNOS5_PHY1_CTRL_BASE 0x10C10000
What are PHY0 and PHY1?
+#define EXYNOS5_FIMD_BASE 0x14400000
And please sort this list.
+#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_GPIO_PART2_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_GPIO_PART3_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__ #include <asm/io.h> @@ -59,9 +85,22 @@ static inline int s5p_get_cpu_rev(void) return s5p_cpu_rev; }
+#define IS_SAMSUNG_TYPE(type, id) \ +static inline int cpu_is_##type(void) \ +{ \
- return s5p_cpu_id == id ? 1 : 0; \
+}
+IS_SAMSUNG_TYPE(exynos4, 0xc210) +IS_SAMSUNG_TYPE(exynos5, 0xc520)
static inline void s5p_set_cpu_id(void) {
- s5p_cpu_id = readl(EXYNOS4_PRO_ID);
- if (cpu_is_exynos5())
- s5p_cpu_id = readl(EXYNOS5_PRO_ID);
- else
- s5p_cpu_id = readl(EXYNOS4_PRO_ID);
Hm.. this is right but, Since base addresses are same, just do "s5p_cpu_id = readl(EXYNOS4_PRO_ID);"
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
/* @@ -76,19 +115,13 @@ static inline void s5p_set_cpu_id(void) } }
-#define IS_SAMSUNG_TYPE(type, id) \ -static inline int cpu_is_##type(void) \ -{ \
- return s5p_cpu_id == id ? 1 : 0; \
-}
-IS_SAMSUNG_TYPE(exynos4, 0xc210)
So.. no need to move.
#define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ { \ if (cpu_is_exynos4()) \ return EXYNOS4_##base; \
- else if (cpu_is_exynos5()) \
- return EXYNOS5_##base; \
else \ return 0; \ } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 9863a12..a5a09ec 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -75,6 +75,29 @@ struct exynos4_gpio_part2 { struct s5p_gpio_bank x3; };
+struct exynos5_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank a2;
- struct s5p_gpio_bank b0;
- struct s5p_gpio_bank b1;
- struct s5p_gpio_bank b2;
- struct s5p_gpio_bank b3;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank c2;
- struct s5p_gpio_bank c3;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
+};
Please move it to under the exynos4_gpio_part3.
struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; @@ -107,8 +130,17 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
+#define exynos5_gpio_part1_get_nr(bank, pin) \
If it support just one part then remove part1. (exynos5_gpio_get_nr)
- ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
- EXYNOS5_GPIO_PART1_BASE)->bank)) \
- - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
static inline unsigned int s5p_gpio_base(int nr) {
- if (cpu_is_exynos5())
- return EXYNOS5_GPIO_PART1_BASE;
if (nr < GPIO_PART1_MAX) return EXYNOS4_GPIO_PART1_BASE; else -- 1.7.5.4
Thanks. Minkyu Kang.