On Sun, Aug 21, 2011 at 4:42 PM, Barry Song 21cnbao@gmail.com wrote:

it seems there is not an actual example that gpio requests pin from pinctrl yet. i might give one on SiRFprimaII.

No good example yet, no.

The reason is that for the U300 that I use as guinea pig, the GPIO driver is tangled up in discussions about how to handle the special control mechanics like requesting muxing and biasing pins. Right now it seems easier to rewrite all that to use the new pinctrl subsystem rather than actually trying to work it into the GPIO subsystem first and refactor from there, and that needs quite a bit of upfront work...

Linus Walleij

On Fri, Aug 26, 2011 at 3:58 AM, Barry Song 21cnbao@gmail.com wrote:

Do you want the pinmux_request_gpio called by the gpiolib driver or by every device driver who uses this gpio?

I always thought about the gpiolib driver.

I think Grant told me he wanted drivers with combined GPIO and pinmuxing to reside in drivers/pinctrl and expose an additional gpiolib interface.

Do you think the following make sense in gpiolib driver? static int xxx_gpio_request(struct gpio_chip *chip, unsigned offset) {        int ret = 0;

ret = pinmux_request_gpio(chip->base + offset);        if (ret)                goto out;        ..... out:        return ret; }

Looks sane to me. It's a bit unfortunate to have to subtract the base and then add it again before passing to pinmux but the idea is to drop the global GPIO pinspace down the road and then it makes more sense.

Yours, Linus Walleij

On Fri, Aug 26, 2011 at 7:12 PM, Stephen Warren swarren@nvidia.com wrote:

[Barry]

...

static int xxx_gpio_request(struct gpio_chip *chip, unsigned offset) {         int ret = 0;

ret = pinmux_request_gpio(chip->base + offset);         if (ret)                 goto out;         ..... out:         return ret; }

I would have expected this to work the other way around; "gpio" is just another function that can be assigned to a pin.

That's basically how it work internally, what I noticed is that GPIO requests seem to come in single pins (not groups) so there is a special function to request a pin by passing in the number from the GPIO pinspace and this optionally propagates all the way to the driver if there is a quick way to request this pin to be muxed in as GPIO.

1. Pin is SF or a particular GPIO.

2. Pin is SF or a particular GPIO from GPIO controller A, or a particular

GPIO from controller B

3. Pin is SF, or one of a number of user-selectable GPIOs.

Case (1) is covered by the code quoted above from earlier in the thread. Cases (2) and (3) can't be covered by that code, and according to comments in earlier replies, both actually exist in real HW.

I think we can handle this quite well conceptually, but I don't know if we have the proper interaction with the drivers yet, so let's rinse and repeat a bit here.

I'll post v5 today with your proposed changes (if you recognize them...)

1. Have a single function "gpio" that can be applied to any pin that

supports it. The actual GPIO number that gets mux'd onto the pin differs per pin, and is determine by HW design. But logically, we're connecting that pin to function "gpio", so we only need one function name for that.

Actually I think the new code can do this, one function "gpio" with multiple what I call "positions", so "gpio" can be on pin {1, 5, 95, ..}

2. Have a function for each GPIO controller that can be attached to a

pin; "gpioa" or "gpiob". Based on the pin being configured, and which of those two GPIO functions is selected, the HW determines the specific GPIO number that's assigned to the pin.

Should also work now with functions and positions per function I hope.

3. Where the GPIO ID assigned to pins is user-selectable, have a function

per GPIO ID; "gpio1", "gpio2", "gpio3", ... "gpio31". This sounds like it'd cause a huge explosion in the number of functions; one to represent each GPIO ID. However, I suspect this won't be too bad in practice, since there's presumably some practical limit to the amount of muxing logic that can be applied to each pin in HW, so the set of options won't be too large.

What happens right now is that the pinmux core system names the pin as taken by "gpioN" where N is the number from the GPIOlib number space.

However that is just a name, not a function, and we have this special callback to the driver to mux in a single pin for GPIO.

So what I need to do to support this is to support machine mappings for the GPIOs as function with positions which currently not available.

Lemme see what I can do about that in v6.

If the set of GPIO IDs that can be assigned to any particular pin is a subset of the whole GPIO number space, e.g.:

pina: gpio1, gpio2, gpio3, gpio4 pinb: gpio2, gpio3, gpio4, gpio5 pinc: gpio3, gpio4, gpio5, gpio6

... then I imagine HW has already defined an enumerator gpioa, gpiob, gpioc, gpiod and a mapping from those to the specific GPIO ID that each means when assigned to a given pin, so those gpioa/b/c/d values could be used as the function exposed by the pinmux driver.

Yep should be possible to make it work that way. Just need a way to map that for the machine.

Yours, Linus Walleij