From: Amit Daniel Kachhap amit.kachhap@linaro.org
This Patch series adds support for AFTR mode cpuidle state based on patch (http://www.spinics.net/lists/arm-kernel/msg132243.html) earlier submitted by Jaecheol Lee jc.lee@samsung.com.
This patch uses CPU PM notifiers , common l2 save/restore and new cpu_suspend/resume interfaces and is based on the tip of linus tree(git://github.com/torvalds/linux.git).
Amit Daniel Kachhap (3): ARM: exynos4: Add support for AFTR mode cpuidle state ARM: exynos4: add L2 early resume code ARM: exynos4: remove useless code to save/restore L2 and GIC state
Lorenzo Pieralisi (1): ARM: exynos4: remove useless churn in sleep.S
arch/arm/mach-exynos4/cpu.c | 43 ++++++-- arch/arm/mach-exynos4/cpuidle.c | 152 +++++++++++++++++++++++++++++- arch/arm/mach-exynos4/include/mach/pmu.h | 2 + arch/arm/mach-exynos4/pm.c | 86 ----------------- arch/arm/mach-exynos4/sleep.S | 29 +++++- 5 files changed, 210 insertions(+), 102 deletions(-)
From: Amit Daniel Kachhap amit.kachhap@linaro.org
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume.
Signed-off-by: Jaecheol Lee jc.lee@samsung.com Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org --- arch/arm/mach-exynos4/cpuidle.c | 152 +++++++++++++++++++++++++++++- arch/arm/mach-exynos4/include/mach/pmu.h | 2 + 2 files changed, 151 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpuidle.c b/arch/arm/mach-exynos4/cpuidle.c index bf7e96f..111ccc3 100644 --- a/arch/arm/mach-exynos4/cpuidle.c +++ b/arch/arm/mach-exynos4/cpuidle.c @@ -11,22 +11,48 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/cpuidle.h> +#include <linux/cpu_pm.h> #include <linux/io.h> - +#include <linux/suspend.h> +#include <linux/err.h> #include <asm/proc-fns.h> +#include <asm/smp_scu.h> +#include <asm/suspend.h> +#include <asm/unified.h> +#include <mach/regs-pmu.h> +#include <mach/pmu.h> + +#include <plat/exynos4.h> +#include <plat/cpu.h> + +#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM7 : (S5P_VA_SYSRAM + 0x24)) +#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM6 : (S5P_VA_SYSRAM + 0x20))
static int exynos4_enter_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
+static int exynos4_enter_lowpower(struct cpuidle_device *dev, + struct cpuidle_state *state); + static struct cpuidle_state exynos4_cpuidle_set[] = { [0] = { .enter = exynos4_enter_idle, .exit_latency = 1, .target_residency = 100000, .flags = CPUIDLE_FLAG_TIME_VALID, - .name = "IDLE", + .name = "C0", .desc = "ARM clock gating(WFI)", }, + [1] = { + .enter = exynos4_enter_lowpower, + .exit_latency = 300, + .target_residency = 100000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "C1", + .desc = "ARM power down", + }, };
static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); @@ -36,6 +62,96 @@ static struct cpuidle_driver exynos4_idle_driver = { .owner = THIS_MODULE, };
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ +static void exynos4_set_wakeupmask(void) +{ + __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); +} + +static unsigned int g_pwr_ctrl, g_diag_reg; + +static void save_cpu_arch_register(void) +{ + /*read power control register*/ + asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); + /*read diagnostic register*/ + asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); + return; +} + +static void restore_cpu_arch_register(void) +{ + /*write power control register*/ + asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); + /*write diagnostic register*/ + asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); + return; +} + +static int idle_finisher(unsigned long flags) +{ + cpu_do_idle(); + return 1; +} + +static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct timeval before, after; + int idle_time; + unsigned long tmp; + + local_irq_disable(); + do_gettimeofday(&before); + + exynos4_set_wakeupmask(); + + /* Set value of power down register for aftr mode */ + exynos4_sys_powerdown_conf(SYS_AFTR); + + save_cpu_arch_register(); + + /* Setting Central Sequence Register for power down mode */ + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + tmp &= ~S5P_CENTRAL_LOWPWR_CFG; + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + cpu_suspend(0, idle_finisher); + + scu_enable(S5P_VA_SCU); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + + restore_cpu_arch_register(); + + /* + * If PMU failed while entering sleep mode, WFI will be + * ignored by PMU and then exiting cpu_do_idle(). + * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically + * in this situation. + */ + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { + tmp |= S5P_CENTRAL_LOWPWR_CFG; + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + } + + /* Clear wakeup state register */ + __raw_writel(0x0, S5P_WAKEUP_STAT); + + do_gettimeofday(&after); + + local_irq_enable(); + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + + (after.tv_usec - before.tv_usec); + + return idle_time; +} + static int exynos4_enter_idle(struct cpuidle_device *dev, struct cpuidle_state *state) { @@ -55,6 +171,26 @@ static int exynos4_enter_idle(struct cpuidle_device *dev, return idle_time; }
+static int exynos4_enter_lowpower(struct cpuidle_device *dev, + struct cpuidle_state *state) +{ + struct cpuidle_state *new_state = state; + + /* This mode only can be entered when Core1 is offline */ + if (num_online_cpus() > 1) { + BUG_ON(!dev->safe_state); + new_state = dev->safe_state; + } + dev->last_state = new_state; + + if (new_state == &dev->states[0]) + return exynos4_enter_idle(dev, new_state); + else + return exynos4_enter_core0_aftr(dev, new_state); + + return exynos4_enter_idle(dev, new_state); +} + static int __init exynos4_init_cpuidle(void) { int i, max_cpuidle_state, cpu_id; @@ -66,8 +202,11 @@ static int __init exynos4_init_cpuidle(void) device = &per_cpu(exynos4_cpuidle_device, cpu_id); device->cpu = cpu_id;
- device->state_count = (sizeof(exynos4_cpuidle_set) / + if (cpu_id == 0) + device->state_count = (sizeof(exynos4_cpuidle_set) / sizeof(struct cpuidle_state)); + else + device->state_count = 1; /* Support IDLE only */
max_cpuidle_state = device->state_count;
@@ -76,11 +215,18 @@ static int __init exynos4_init_cpuidle(void) sizeof(struct cpuidle_state)); }
+ device->safe_state = &device->states[0]; + if (cpuidle_register_device(device)) { printk(KERN_ERR "CPUidle register device failed\n,"); return -EIO; } } + + __raw_writel(BSYM(virt_to_phys(s3c_cpu_resume)), + REG_DIRECTGO_ADDR); + __raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG); + return 0; } device_initcall(exynos4_init_cpuidle); diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h index a952904..31d1ed8 100644 --- a/arch/arm/mach-exynos4/include/mach/pmu.h +++ b/arch/arm/mach-exynos4/include/mach/pmu.h @@ -20,6 +20,8 @@ enum sys_powerdown { NUM_SYS_POWERDOWN, };
+extern unsigned long l2x0_regs_phys; extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); +extern void s3c_cpu_resume(void);
#endif /* __ASM_ARCH_PMU_H */
On Sat, Nov 5, 2011 at 2:03 AM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhap amit.kachhap@linaro.org
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume.
Signed-off-by: Jaecheol Lee jc.lee@samsung.com Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org
[]
+#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (S5P_VA_SYSRAM + 0x24))+#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM6 : (S5P_VA_SYSRAM + 0x20))
[]
__raw_writel(BSYM(virt_to_phys(s3c_cpu_resume)),REG_DIRECTGO_ADDR);__raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);return 0;
Hello,
Why are you using INFORM6 and 7 registers in order to save resume address and power-mode flags?
INFORM0 and 1 have been used in pm.c for the exactly same purpose. Please use the same registers in cpuidle.c as well.
The same part in bootloader (IPL) can handle whether it's suspend-to-RAM or AFTR and the both modes are mutually exclusive and you only need one value for resume PC.
Therefore, you can keep the value at the same location, which is the method we have been using.
Besides, the Exynos4210 chipmaker (S.LSI) has told that INFORM6 and 7 registers are used by in-chip code (iROM or iRAM).
Cheers! MyungJoo
On 11 November 2011 13:03, MyungJoo Ham myungjoo.ham@gmail.com wrote:
On Sat, Nov 5, 2011 at 2:03 AM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhap amit.kachhap@linaro.org
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume.
Signed-off-by: Jaecheol Lee jc.lee@samsung.com Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org
[]
+#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM7 : (S5P_VA_SYSRAM + 0x24))
+#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM6 : (S5P_VA_SYSRAM + 0x20))
[]
- __raw_writel(BSYM(virt_to_phys(s3c_cpu_resume)),
- REG_DIRECTGO_ADDR);
- __raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
return 0;
Hello,
Why are you using INFORM6 and 7 registers in order to save resume address and power-mode flags?
INFORM0 and 1 have been used in pm.c for the exactly same purpose. Please use the same registers in cpuidle.c as well.
The same part in bootloader (IPL) can handle whether it's suspend-to-RAM or AFTR and the both modes are mutually exclusive and you only need one value for resume PC.
Therefore, you can keep the value at the same location, which is the method we have been using.
Hi,
I tried using INFORM0 and INFORM1 in cpuidle and make it same as pm.c. But this doesnt work. Looks like my irom fused code checks for the wakeup source and needs INFORM7 and INFORM6 for non sleep wakeups. My cpu version is S5PV310AH--0AH1113(Origen board). I suggest adding support for both type of wakeups(directly from irom and through bootloader).
Thanks, Amit D
Besides, the Exynos4210 chipmaker (S.LSI) has told that INFORM6 and 7 registers are used by in-chip code (iROM or iRAM).
Cheers! MyungJoo
-- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics
On Thu, Nov 17, 2011 at 8:22 PM, Amit Kachhap amit.kachhap@linaro.org wrote:
On 11 November 2011 13:03, MyungJoo Ham myungjoo.ham@gmail.com wrote:
On Sat, Nov 5, 2011 at 2:03 AM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhap amit.kachhap@linaro.org
This patch adds support for AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver for EXYNOS4210. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume.
Signed-off-by: Jaecheol Lee jc.lee@samsung.com Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org
[]
+#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM7 : (S5P_VA_SYSRAM + 0x24))
+#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
- S5P_INFORM6 : (S5P_VA_SYSRAM + 0x20))
[]
- __raw_writel(BSYM(virt_to_phys(s3c_cpu_resume)),
- REG_DIRECTGO_ADDR);
- __raw_writel(0xfcba0d10, REG_DIRECTGO_FLAG);
return 0;
Hello,
Why are you using INFORM6 and 7 registers in order to save resume address and power-mode flags?
INFORM0 and 1 have been used in pm.c for the exactly same purpose. Please use the same registers in cpuidle.c as well.
The same part in bootloader (IPL) can handle whether it's suspend-to-RAM or AFTR and the both modes are mutually exclusive and you only need one value for resume PC.
Therefore, you can keep the value at the same location, which is the method we have been using.
Hi,
I tried using INFORM0 and INFORM1 in cpuidle and make it same as pm.c. But this doesnt work. Looks like my irom fused code checks for the wakeup source and needs INFORM7 and INFORM6 for non sleep wakeups. My cpu version is S5PV310AH--0AH1113(Origen board). I suggest adding support for both type of wakeups(directly from irom and through bootloader).
Hello Amit,
Have you checked the part that checks flags for AFTR mode and Suspend-to-RAM in IPL?
If your code is checking AFTR flags with INFORM6/7 and PM flags with INFORM0/1, that is terribly wrong as those two modes are mutually exclusive and are very similar in terms of IPL codes.
Also, the IPL-bootloader code runs in IRAM where CPU determines whether to continue to boot or jump to resume address of suspend-to-RAM or deepidle (AFTR/LPA/...).
If yours works with INFORM0/1 for PM, it should work with INFORM0/1 in AFTR as well if your (S/W loadable) IPL code is correct and INFORM6/7 is not touched regardless of how your IROM code is written. Please check your IPL code and try to let AFTR use the same address with PM. There is no reason to use another INFORM registers for AFTR only. Please note that pm-related IPL code is not in ROM, but loaded by ROM part of IPL to RAM from a storage.
To jc.lee,
Could you please check whether your IPL code checks for INFORM0/1 for both PM and AFTR or INFORM0/1 for PM and INFORM6/7 for AFTR? If the latter is what your IPL does, then, how does it react when both INFORM0/1 and INFORM6/7 are set for both PM and AFTR? The IPL code we have uses INFORM0/1 for both PM and AFTR/LPA.
Cheers! MyungJoo
Thanks, Amit D
Besides, the Exynos4210 chipmaker (S.LSI) has told that INFORM6 and 7 registers are used by in-chip code (iROM or iRAM).
Cheers! MyungJoo
-- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics
From: Lorenzo Pieralisi lorenzo.pieralisi@arm.com
This patch cleans up sleep code in preparation for L2 resume code and hotplug functions
Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com --- arch/arm/mach-exynos4/sleep.S | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index 0984078..c19527b 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -27,8 +27,6 @@ */
#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/memory.h>
.text
@@ -52,3 +50,4 @@
ENTRY(s3c_cpu_resume) b cpu_resume +ENDPROC(s3c_cpu_resume)
From: Amit Daniel Kachhap amit.kachhap@linaro.org
This patch adds code to save L2 register configuration at boot, and to resume L2 before MMU is enabled in suspend and cpuidle resume paths.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org --- arch/arm/mach-exynos4/cpu.c | 43 ++++++++++++++++++++++++++++++---------- arch/arm/mach-exynos4/sleep.S | 26 ++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index a348434..53c6cd3 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -11,6 +11,7 @@ #include <linux/sched.h> #include <linux/sysdev.h>
+#include <asm/cacheflush.h> #include <asm/mach/map.h> #include <asm/mach/irq.h>
@@ -31,6 +32,7 @@
#include <mach/regs-irq.h> #include <mach/regs-pmu.h> +#include <mach/pmu.h>
unsigned int gic_bank_offset __read_mostly;
@@ -254,20 +256,39 @@ core_initcall(exynos4_core_init); #ifdef CONFIG_CACHE_L2X0 static int __init exynos4_l2x0_cache_init(void) { - /* TAG, Data Latency Control: 2cycle */ - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
- if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212() || soc_is_exynos4412()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; + /* TAG, Data Latency Control: 2 cycles */ + l2x0_saved_regs.tag_latency = 0x110; + + if (soc_is_exynos4212() || soc_is_exynos4412()) + l2x0_saved_regs.data_latency = 0x120; + else + l2x0_saved_regs.data_latency = 0x110; + + l2x0_saved_regs.prefetch_ctrl = 0x30000007; + l2x0_saved_regs.pwr_ctrl = + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
- /* L2X0 Prefetch Control */ - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
- /* L2X0 Power Control */ - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, - S5P_VA_L2CC + L2X0_POWER_CTRL); + __raw_writel(l2x0_saved_regs.tag_latency, + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(l2x0_saved_regs.data_latency, + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + + /* L2X0 Prefetch Control */ + __raw_writel(l2x0_saved_regs.prefetch_ctrl, + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(l2x0_saved_regs.pwr_ctrl, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); + }
l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index c19527b..3284213 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -27,6 +27,8 @@ */
#include <linux/linkage.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h>
.text
@@ -47,7 +49,31 @@ * other way of restoring the stack pointer after sleep, and we * must not write to the code segment (code is read-only) */ + .align + .data
ENTRY(s3c_cpu_resume) + adr r0, l2x0_regs_phys + ldr r0, [r0] + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne resume_l2on + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +resume_l2on: b cpu_resume ENDPROC(s3c_cpu_resume) + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0
From: Amit Daniel Kachhap amit.kachhap@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org --- arch/arm/mach-exynos4/pm.c | 86 -------------------------------------------- 1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 62e4f43..7499f14 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = { };
static struct sleep_save exynos4_core_save[] = { - /* GIC side */ - SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x008), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x014), - SAVE_ITEM(S5P_VA_GIC_CPU + 0x018), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x000), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x004), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x100), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x104), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x108), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x300), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x304), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x308), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x400), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x404), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x408), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x410), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x414), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x418), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x420), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x424), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x428), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x430), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x434), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x438), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x440), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x444), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x448), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x450), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x454), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x458), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C), - - SAVE_ITEM(S5P_VA_GIC_DIST + 0x800), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x804), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x808), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x810), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x814), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x818), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x820), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x824), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x828), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x830), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x834), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x838), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x840), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x844), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x848), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x850), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x854), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x858), - SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C), - - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10), - SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000), SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010), @@ -154,13 +83,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), };
-static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -};
/* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -181,7 +103,6 @@ static void exynos4_pm_prepare(void) u32 tmp;
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
@@ -397,13 +318,6 @@ static void exynos4_pm_resume(void)
exynos4_scu_enable(S5P_VA_SCU);
-#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }
On 11/04/2011 06:03 PM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhap amit.kachhap@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org
arch/arm/mach-exynos4/pm.c | 86 -------------------------------------------- 1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 62e4f43..7499f14 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = { }; static struct sleep_save exynos4_core_save[] = {
- /* GIC side */
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
This list is not complete anyway, some peripheral devices interrupts do not work after resume from system suspend to RAM. Is there any code already handling GIC state during system suspend/resume cycles? Or you refer to some upcoming patches ?
-- Thanks, Sylwester
On 4 November 2011 23:03, Sylwester Nawrocki s.nawrocki@samsung.com wrote:
On 11/04/2011 06:03 PM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhap amit.kachhap@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on.
Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhap amit.kachhap@linaro.org
arch/arm/mach-exynos4/pm.c | 86 -------------------------------------------- 1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 62e4f43..7499f14 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = { };
static struct sleep_save exynos4_core_save[] = {
- /* GIC side */
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
- SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
- SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
This list is not complete anyway, some peripheral devices interrupts do not work after resume from system suspend to RAM. Is there any code already handling GIC state during system suspend/resume cycles? Or you refer to some upcoming patches ?
In my next patch series I have left the GIC save/restore from platform code.
-- Thanks, Sylwester
On 11/11/2011 07:28 AM, Amit Kachhap wrote:
On 4 November 2011 23:03, Sylwester Nawrockis.nawrocki@samsung.com wrote:
On 11/04/2011 06:03 PM, amit.kachhap@linaro.org wrote:
From: Amit Daniel Kachhapamit.kachhap@linaro.org
Following the merge of CPU PM notifiers and L2 resume code, this patch removes useless code to save and restore L2 and GIC registers.
This is now automatically covered by suspend calls which integrated CPU PM notifiers and new sleep code that allows to resume L2 before MMU is turned on.
Signed-off-by: Lorenzo Pieralisilorenzo.pieralisi@arm.com Signed-off-by: Amit Daniel Kachhapamit.kachhap@linaro.org
arch/arm/mach-exynos4/pm.c | 86 -------------------------------------------- 1 files changed, 0 insertions(+), 86 deletions(-)
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 62e4f43..7499f14 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -63,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = { };
static struct sleep_save exynos4_core_save[] = {
/* GIC side */SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),This list is not complete anyway, some peripheral devices interrupts do not work after resume from system suspend to RAM. Is there any code already handling GIC state during system suspend/resume cycles? Or you refer to some upcoming patches ?
In my next patch series I have left the GIC save/restore from platform code.
OK, although I thought someone is just going to fix the regression introduced with commit:
commit aab74d3e753649defa52ea43cbec1e91ebb4cc8e Author: Changhwan Youn chaos.youn@samsung.com Date: Sat Jul 16 10:49:51 2011 +0900
ARM: EXYNOS4: Add support external GIC
For full support of power modes, this patch adds implementation external GIC on EXYNOS4.
External GIC of Exynos4 cannot support register banking so several interrupt related code for CPU1 should be different from that of CPU0.
Signed-off-by: Changhwan Youn chaos.youn@samsung.com Signed-off-by: Kukjin Kim kgene.kim@samsung.com
The external GIC has more registers and now not all of them are properly handled during system sleep/resume. I didn't get around yet to submit a proper solution for that. I suspect per CPU distributor and CPU interface register files need to be saved/restored. I'm not an expert in the GIC internals though, I'm just wondering why can't GIC be left active during system sleep.
-- Regards, Sylwester
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Amit Kachhap -
amit.kachhap＠linaro.org
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MyungJoo Ham -
Sylwester Nawrocki -
Sylwester Nawrocki