On Fri, Dec 06, 2013 at 12:39:56PM +0000, sandeep tripathy wrote:

Is there any rational why flush_cache_louis is necessary in cpu_suspend() funciton ?

Legacy.

After saving the context it does DCCIMVA ie writes to POC the affected lines. So why we should clean the entire L1 here ?

Legacy :). Remember that that code is shared by all ARM 32-bit implementations, most of them UP. cpu_suspend consolidated existing suspend finishers and moved the common L1 flush routine there (remember that LoUIS is a v7 thing, on pre-v7 cores that function flushes the entire d-cache).

It rather should be left to the platform dependent function called after __cpu_suspend ?

That's what the cpu_suspend common code implementation wanted to prevent, scattering flush calls that can be consolidated in one place.

On v7, we then added the LoUIS API to prevent suspend code to flush the entire d-cache hierarchy on power down, but left the flush in cpu_suspend, because otherwise we would have to patch ALL suspend finishers in the kernel, basically reverting the consolidation effort.

flush_cache_louis does not disable the d cache. This is not the recommended sequence for core power down.

All v7 SMP implementations must clear C bit in SCTLR and then clean/invalidate the cache again, and that's how it is done in platform backends. If the platform code does not do it, it is buggy.

The second flush will be _mostly_ a nop.

We are aware of the duplicated code, and I think it is best to keep it as it is instead of re-scattering all the flush calls in platform specific finishers. On v8, cpu_suspend just cleans few lines to DRAM, complete cache flush is delegated to FW/platform backends.

HTH, Lorenzo