Hi All,
In arch/arm64/include/asm/barrier.h, there is the definition of smp_mb()/smp_rmb()/smp_wmb() for arm64. I noticed that all the 3 macors are using "dmb ishxx", which is only affect the cluster of the CPU executing the instruction. But in the big.LITTLE system, there will be 2 cluster. So the smp_mb()/smp_rmb()/smp_wmb() cannot affect all the CPU in the system.
Is there other considerations so that smp_mb()/smp_rmb()/smp_wmb() are implemented to "only affecting inner sharable cores"?
Best Regards,
Kelvin K. Li
--------------------------------------------------------------- Software Team, VIA Technologies, Inc. 5F, VIA Tower, 1 Zhongguancun East Road, Haidian District, Beijing, 100084 Tel: 86-10-59852288 ext.3620 mailto: kelvinkli@via-alliance.com
Hi Kelvin.
On 30 April 2014 10:52, KelvinKLi@via-alliance.com wrote:
In arch/arm64/include/asm/barrier.h, there is the definition of smp_mb()/smp_rmb()/smp_wmb() for arm64. I noticed that all the 3 macors are using “dmb ishxx”, which is only affect the cluster of the CPU executing the instruction.
This is incorrect.
But in the big.LITTLE system, there will be 2 cluster. So the smp_mb()/smp_rmb()/smp_wmb() cannot affect all the CPU in the system.
Yes, they do.
In a big.LITTLE HMP system, all participating CPUs are part of the inner-shareable domain.
Regards,
Leif
Hi Leif，
Why do the smp_mb()/smp_rmb()/smp_wmb() for arm (arm-32) not change to the "dmb ishxx" too?
Is there some consideration？
-----Original Message----- From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: 2014-5-1 (星期四) 0:39 To: Kelvin K. Li Cc: linaro-dev Subject: Re: why is the the smp_mb() in arm64's barrier.h "dmb ish"?
Hi Kelvin.
On 30 April 2014 10:52, KelvinKLi@via-alliance.com wrote:
In arch/arm64/include/asm/barrier.h, there is the definition of smp_mb()/smp_rmb()/smp_wmb() for arm64. I noticed that all the 3 macors are using “dmb ishxx”, which is only affect the cluster of the CPU executing the instruction.
This is incorrect.
But in the big.LITTLE system, there will be 2 cluster. So the smp_mb()/smp_rmb()/smp_wmb() cannot affect all the CPU in the system.
Yes, they do.
In a big.LITTLE HMP system, all participating CPUs are part of the inner-shareable domain.
Regards,
Leif
Hi Kelvin,
On Thu, May 01, 2014 at 06:08:14PM +0800, KelvinKLi@via-alliance.com wrote:
Why do the smp_mb()/smp_rmb()/smp_wmb() for arm (arm-32) not change to the "dmb ishxx" too?
But they do. For ARMv7, smb_mb(), smp_rmb() and smp_wmb() become dmb ish, dmb ish and dmb ishst respectively.
This was introduced in: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/...
/ Leif
Hi Leif，
Another questions:
In Arm V8 Architecture Reference Manual，there is an example (see beblow) to explain the shareability attribute of clusters. It is easy to know: each cluster is corresponding to a Inner shareable domain; the two cluster comprise a Outer shareable domain.
So, how does the big.LITTLE HMP system treat two clusters as a Inner shareable domain？
From Page B2-91, DDI0487A_b_armv8_arm.pdf:
Example B2-1 Use of shareability attributes In an implementation, a particular subsystem with two clusters of PEs has the requirement that: * In each cluster, the data caches or unified caches of the PEs in the cluster are transparent for all data accesses to memory locations with the Inner Shareable attribute. * However, between the two clusters, the caches: ― Are not required to be coherentfor data accesses that have only the Inner Shareable attribute. ― Are coherent for data accesses that have the Outer Shareable attribute. In this system, each cluster is in a different shareability domain for the Inner Shareable attribute,but all components of the subsystem are in the same shareability domain for the Outer Shareable attribute. A system might implement two such subsystems. If the data caches or unified caches of onesubsystem are not transparent to the accesses from the other subsystem, this system has two Outer Shareable shareability domains.
-----Original Message----- From: Kelvin K. Li Sent: 2014-5-1 (星期四) 18:08 To: Leif Lindholm Cc: linaro-dev Subject: 答复: why is the the smp_mb() in arm64's barrier.h "dmb ish"?
Hi Leif，
Why do the smp_mb()/smp_rmb()/smp_wmb() for arm (arm-32) not change to the "dmb ishxx" too?
Is there some consideration？
-----Original Message----- From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: 2014-5-1 (星期四) 0:39 To: Kelvin K. Li Cc: linaro-dev Subject: Re: why is the the smp_mb() in arm64's barrier.h "dmb ish"?
Hi Kelvin.
On 30 April 2014 10:52, KelvinKLi@via-alliance.com wrote:
In arch/arm64/include/asm/barrier.h, there is the definition of smp_mb()/smp_rmb()/smp_wmb() for arm64. I noticed that all the 3 macors are using “dmb ishxx”, which is only affect the cluster of the CPU executing the instruction.
This is incorrect.
But in the big.LITTLE system, there will be 2 cluster. So the smp_mb()/smp_rmb()/smp_wmb() cannot affect all the CPU in the system.
Yes, they do.
In a big.LITTLE HMP system, all participating CPUs are part of the inner-shareable domain.
Regards,
Leif
On Thu, May 01, 2014 at 06:49:44PM +0800, KelvinKLi@via-alliance.com wrote:
Another questions:
In Arm V8 Architecture Reference Manual，there is an example (see beblow) to explain the shareability attribute of clusters. It is easy to know: each cluster is corresponding to a Inner shareable domain; the two cluster comprise a Outer shareable domain.
The ARM ARM describes the architectural requirements for a system to be able to work correctly. Specific implementations can add further abilities within the scope of this. And Linux can then have additional requirements for how to enable SMP/HMP..
So, how does the big.LITTLE HMP system treat two clusters as a Inner shareable domain？
Example for Cortex-A53: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500d/ch07s02...
Regards,
Leif
Hi Leif,
I think I got it. Thank you very much.
-----Original Message----- From: Leif Lindholm [mailto:leif.lindholm@linaro.org] Sent: 2014-5-1 (星期四) 19:32 To: Kelvin K. Li Cc: linaro-dev@lists.linaro.org Subject: Re: 答复: why is the the smp_mb() in arm64's barrier.h "dmb ish"?
On Thu, May 01, 2014 at 06:49:44PM +0800, KelvinKLi@via-alliance.com wrote:
Another questions:
In Arm V8 Architecture Reference Manual，there is an example (see beblow) to explain the shareability attribute of clusters. It is easy to know: each cluster is corresponding to a Inner shareable domain; the two cluster comprise a Outer shareable domain.
The ARM ARM describes the architectural requirements for a system to be able to work correctly. Specific implementations can add further abilities within the scope of this. And Linux can then have additional requirements for how to enable SMP/HMP..
So, how does the big.LITTLE HMP system treat two clusters as a Inner shareable domain？
Example for Cortex-A53: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500d/ch07s02...
Regards,
Leif
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KelvinKLi＠via-alliance.com -
Leif Lindholm