flag@omap:~$ dmesg | grep -A 1 L310 [ 0.219024] L310 cache controller enabled [ 0.219055] l2x0: 16 ways, CACHE_ID 0x410000c4, AUX_CTRL 0x7e470000, Cache size: 1048576 B ^^^^^^^^^^^^^^ according to [1], that means Panda has a r3p0 L310 L2 controller.

[flag@newluxor linux-linaro-2.6.38]$ git show 885028e

commit 885028e4ba4caf49d565c96481e1a05220ecb517 Author: Srinidhi Kasagar srinidhi.kasagar@stericsson.com Date: Thu Feb 17 07:03:51 2011 +0100

ARM: 6741/1: errata: pl310 cache sync operation may be faulty

The effect of cache sync operation is to drain the store buffer and wait for all internal buffers to be empty. In normal conditions, store buffer is able to merge the normal memory writes within its 32-byte data buffers. Due to this erratum present in r3p0, the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes.

This can severely affect performance on the write traffic esp. on Normal memory NC one.

The proposed workaround is to replace the normal offset of cache sync operation(0x730) by another offset targeting an unmapped PL310 register 0x740.

Signed-off-by: srinidhi kasagar srinidhi.kasagar@stericsson.com Acked-by: Linus Walleij linus.walleij@stericsson.com Acked-by: Catalin Marinas catalin.marinas@arm.com Signed-off-by: Russell King rmk+kernel@arm.linux.org.uk

[1]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246d/Beibhhe...