Hi. I have a question about a detail in the OMAP3 TRM, which I was hoping some omap-savvy person on this list might be able to answer.
This is about the GPMC prefetch engine register GPMC_PREFETCH_STATUS and specifically its FIFOTHRESHOLDSTATUS bit. I've been using the OMAP35xx TRM (document SPRUF98L, rev L) as reference.
The register summary on page 1176 says "set when FIFOPointer exceeds FIFOThreshold value" and is clear that it is 1 if Pointer
Threshold. However the description on page 1141 says "The
FIFOPOINTER indicates the current number of available data to be read; FIFOTHRESHOLDSTATUS set to 1 indicates that at least FIFOTHRESHOLD bytes are available from the FIFO", ie the bit is set if Pointer >= Threshold. The text on p1143 is similar.
So is the bit set for Pointer > Threshold or Pointer >= Threshold? (Greater-than-or-equal makes more conceptual sense to me and would match the condition in which GPMC_IRQSTATUS's FIFOEVENTSTATUS bit is set.)
(I'm looking at this because I'm implementing the prefetch engine in qemu.)
thanks in advance -- PMM
The underlying functional spec which TRM started from gives this description:
"In MPU filling mode, the FIFO status can be monitored through the FIFOPointer or through the FIFOThresholdStatus bits in the GPMC_PREFETCH_STATUS register. FIFOPointer indicates the current number of available free byte places in the FIFO, and FIFOThresholdStatus, when set, indicates that at least FIFOThreshold free byte places are available in the FIFO."
There is an NDA application note about on prefetch engine which also might be useful (SWPA146 - NAND Flash usage with GPMC).
Regards, Richard W.
-----Original Message----- From: linaro-dev-bounces@lists.linaro.org [mailto:linaro-dev- bounces@lists.linaro.org] On Behalf Of Peter Maydell Sent: Friday, December 10, 2010 11:06 AM To: linaro-dev@lists.linaro.org Subject: OMAP query about GPMC FIFOTHRESHOLDSTATUS bit
Hi. I have a question about a detail in the OMAP3 TRM, which I was hoping some omap-savvy person on this list might be able to answer.
This is about the GPMC prefetch engine register GPMC_PREFETCH_STATUS and specifically its FIFOTHRESHOLDSTATUS bit. I've been using the OMAP35xx TRM (document SPRUF98L, rev L) as reference.
The register summary on page 1176 says "set when FIFOPointer exceeds FIFOThreshold value" and is clear that it is 1 if Pointer
Threshold. However the description on page 1141 says "The
FIFOPOINTER indicates the current number of available data to be read; FIFOTHRESHOLDSTATUS set to 1 indicates that at least FIFOTHRESHOLD bytes are available from the FIFO", ie the bit is set if Pointer >= Threshold. The text on p1143 is similar.
So is the bit set for Pointer > Threshold or Pointer >= Threshold? (Greater-than-or-equal makes more conceptual sense to me and would match the condition in which GPMC_IRQSTATUS's FIFOEVENTSTATUS bit is set.)
(I'm looking at this because I'm implementing the prefetch engine in qemu.)
thanks in advance -- PMM
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On 10 December 2010 19:25, Woodruff, Richard r-woodruff2@ti.com wrote:
The underlying functional spec which TRM started from gives this description:
"In MPU filling mode, the FIFO status can be monitored through the FIFOPointer or through the FIFOThresholdStatus bits in the GPMC_PREFETCH_STATUS register. FIFOPointer indicates the current number of available free byte places in the FIFO, and FIFOThresholdStatus, when set, indicates that at least FIFOThreshold free byte places are available in the FIFO."
Thanks for the clarification.
In case you're collecting things to clean up for the next issue, here's another :-) The Rev M OMAP35x TRM says on page 1139:
"In both prefetch and write-posting modes, the engine respectivelly uses byte or Word16 access requests for an 8- or 16-bit wide NAND device attached to the linked chip-select. The FIFOTHRESHOLD and TRANSFERCOUNT fields must be programmed accordingly as a number of bytes or a number of Word16."
However the register descriptions just say that FIFOTHRESHOLD and TRANSFERCOUNT are byte counts.
In this case I'm going to trust the register descriptions because that's how Linux programs them (and it doesn't boot if you model them as Word16 counts...)
-- PMM
From: Peter Maydell [mailto:peter.maydell@linaro.org] Sent: Sunday, December 12, 2010 3:02 PM
In case you're collecting things to clean up for the next issue, here's another :-) The Rev M OMAP35x TRM says on page 1139:
"In both prefetch and write-posting modes, the engine respectivelly uses byte or Word16 access requests for an 8- or 16-bit wide NAND device attached to the linked chip-select. The FIFOTHRESHOLD and TRANSFERCOUNT fields must be programmed accordingly as a number of bytes or a number of Word16."
Yes that appears wrong in all TRM and underlying specs.
However the register descriptions just say that FIFOTHRESHOLD and TRANSFERCOUNT are byte counts.
In this case I'm going to trust the register descriptions because that's how Linux programs them (and it doesn't boot if you model them as Word16 counts...)
A search on TRANSFERCOUNT does show 3 spots where it explicitly says bytes.
I'll forward to TRM owners. I know the right folks for 34xx,36xx,44xx, I think that should propagate to 35xx and other variants.
Regards, Richard W.
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Peter Maydell -
Woodruff, Richard