On 10 December 2010 19:25, Woodruff, Richard r-woodruff2@ti.com wrote:
The underlying functional spec which TRM started from gives this description:
"In MPU filling mode, the FIFO status can be monitored through the FIFOPointer or through the FIFOThresholdStatus bits in the GPMC_PREFETCH_STATUS register. FIFOPointer indicates the current number of available free byte places in the FIFO, and FIFOThresholdStatus, when set, indicates that at least FIFOThreshold free byte places are available in the FIFO."
Thanks for the clarification.
In case you're collecting things to clean up for the next issue, here's another :-) The Rev M OMAP35x TRM says on page 1139:
"In both prefetch and write-posting modes, the engine respectivelly uses byte or Word16 access requests for an 8- or 16-bit wide NAND device attached to the linked chip-select. The FIFOTHRESHOLD and TRANSFERCOUNT fields must be programmed accordingly as a number of bytes or a number of Word16."
However the register descriptions just say that FIFOTHRESHOLD and TRANSFERCOUNT are byte counts.
In this case I'm going to trust the register descriptions because that's how Linux programs them (and it doesn't boot if you model them as Word16 counts...)
-- PMM