linaro-dev

linaro-dev@lists.linaro.org

4332 discussions

by Amit Kucheria

Can we merge the SD/MMC patches for i.MX MMC support into the linaro kernel? They have been reviewed extensively and look very likely to go into the next merge window. Merging them and enabling SD support for i.MX51 will allow us to make a more functional hwpack for the babbage boards. Please search for "SD/MMC driver for MX25/35/51" from Wolfram Sang on lakml for the patchset. Regards, Amit

14 years, 2 months

[PATCHv3] cpufreq for freescale mx51

by yong.shen＠linaro.org

From: Yong Shen <yong.shen(a)linaro.org> the operating points are tested on babbage 3.0 Signed-off-by: Yong Shen <yong.shen(a)linaro.org> --- arch/arm/Kconfig | 6 + arch/arm/mach-mx5/Kconfig | 1 + arch/arm/mach-mx5/Makefile | 1 + arch/arm/mach-mx5/board-mx51_babbage.c | 12 ++- arch/arm/mach-mx5/clock-mx51.c | 22 +++- arch/arm/mach-mx5/cpu.c | 2 + arch/arm/mach-mx5/cpu_op-mx51.c | 29 +++++ arch/arm/mach-mx5/cpu_op-mx51.h | 14 +++ arch/arm/plat-mxc/Makefile | 1 + arch/arm/plat-mxc/cpufreq.c | 202 ++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mxc.h | 20 +++- 11 files changed, 306 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-mx5/cpu_op-mx51.c create mode 100644 arch/arm/mach-mx5/cpu_op-mx51.h create mode 100644 arch/arm/plat-mxc/cpufreq.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e4ea9cb..d9ad605 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1692,6 +1692,12 @@ if ARCH_HAS_CPUFREQ source "drivers/cpufreq/Kconfig" +config CPU_FREQ_IMX + tristate "CPUfreq driver for i.MX CPUs" + depends on ARCH_MXC && CPU_FREQ + help + This enables the CPUfreq driver for i.MX CPUs. + config CPU_FREQ_SA1100 bool diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 0848db5..7a621b4 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -5,6 +5,7 @@ config ARCH_MX51 default y select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select ARCH_HAS_CPUFREQ comment "MX5 platforms:" diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 86c66e7..2fadac5 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -5,6 +5,7 @@ # Object file lists. obj-y := cpu.o mm.o clock-mx51.o devices.o +obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 6e384d9..74c796f 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria(a)canonical.com> * * The code contained herein is licensed under the GNU General Public @@ -32,6 +32,7 @@ #include <asm/mach/time.h> #include "devices.h" +#include "cpu_op-mx51.h" #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ @@ -279,8 +280,17 @@ static struct sys_timer mxc_timer = { .init = mx51_babbage_timer_init, }; +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +#if defined(CONFIG_CPU_FREQ_IMX) + get_cpu_op = mx51_get_cpu_op; +#endif +} + MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Amit Kucheria <amit.kucheria(a)canonical.com> */ + .fixup = fixup_mxc_board, .phys_io = MX51_AIPS1_BASE_ADDR, .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 6af69de..f89d8a0 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -330,7 +330,7 @@ static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) return 0; } -static unsigned long clk_arm_get_rate(struct clk *clk) +static unsigned long clk_cpu_get_rate(struct clk *clk) { u32 cacrr, div; unsigned long parent_rate; @@ -342,6 +342,22 @@ static unsigned long clk_arm_get_rate(struct clk *clk) return parent_rate / div; } +static int clk_cpu_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, cpu_podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + cpu_podf = parent_rate / rate - 1; + /* use post divider to change freq */ + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; + reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -693,7 +709,8 @@ static struct clk periph_apm_clk = { static struct clk cpu_clk = { .parent = &pll1_sw_clk, - .get_rate = clk_arm_get_rate, + .get_rate = clk_cpu_get_rate, + .set_rate = clk_cpu_set_rate, }; static struct clk ahb_clk = { @@ -837,6 +854,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) }; static void clk_tree_init(void) diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 2d37785..f3fe51a 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -22,6 +22,8 @@ static int cpu_silicon_rev = -1; #define SI_REV 0x48 +struct cpu_op *(*get_cpu_op)(int *op); + static void query_silicon_parameter(void) { void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c new file mode 100644 index 0000000..9d34c3d --- /dev/null +++ b/arch/arm/mach-mx5/cpu_op-mx51.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/types.h> +#include <mach/hardware.h> +#include <linux/kernel.h> + +static struct cpu_op mx51_cpu_op[] = { + { + .cpu_rate = 160000000,}, + { + .cpu_rate = 800000000,}, +}; + +struct cpu_op *mx51_get_cpu_op(int *op) +{ + *op = ARRAY_SIZE(mx51_cpu_op); + return mx51_cpu_op; +} diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h new file mode 100644 index 0000000..97477fe --- /dev/null +++ b/arch/arm/mach-mx5/cpu_op-mx51.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +extern struct cpu_op *mx51_get_cpu_op(int *op); diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 78d405e..a833d38 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o +obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o ifdef CONFIG_SND_IMX_SOC obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c new file mode 100644 index 0000000..9cabeb9 --- /dev/null +++ b/arch/arm/plat-mxc/cpufreq.c @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * A driver for the Freescale Semiconductor i.MXC CPUfreq module. + * The CPUFREQ driver is for controling CPU frequency. It allows you to change + * the CPU clock speed on the fly. + */ + +#include <linux/cpufreq.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <mach/hardware.h> +#include <mach/clock.h> + +#define CLK32_FREQ 32768 +#define NANOSECOND (1000 * 1000 * 1000) + +static int cpu_freq_khz_min; +static int cpu_freq_khz_max; +static int arm_normal_clk; + +static struct clk *cpu_clk; +static struct cpufreq_frequency_table *imx_freq_table; + +static int cpu_op_nr; +static struct cpu_op *cpu_op_tbl; + +static int set_cpu_freq(int freq) +{ + int ret = 0; + int org_cpu_rate; + + org_cpu_rate = clk_get_rate(cpu_clk); + if (org_cpu_rate == freq) + return ret; + + ret = clk_set_rate(cpu_clk, freq); + if (ret != 0) { + printk(KERN_DEBUG "cannot set CPU clock rate\n"); + return ret; + } + + return ret; +} + +static int mxc_verify_speed(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -EINVAL; + + return cpufreq_frequency_table_verify(policy, imx_freq_table); +} + +static unsigned int mxc_get_speed(unsigned int cpu) +{ + if (cpu) + return 0; + + return clk_get_rate(cpu_clk) / 1000; +} + +static int mxc_set_target(struct cpufreq_policy *policy, + unsigned int target_freq, unsigned int relation) +{ + struct cpufreq_freqs freqs; + int freq_Hz; + int ret = 0; + unsigned int index; + + cpufreq_frequency_table_target(policy, imx_freq_table, + target_freq, relation, &index); + freq_Hz = imx_freq_table[index].frequency * 1000; + + freqs.old = clk_get_rate(cpu_clk) / 1000; + freqs.new = freq_Hz / 1000; + freqs.cpu = 0; + freqs.flags = 0; + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + + if (freqs.old != freqs.new) + ret = set_cpu_freq(freq_Hz); + + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + + return ret; +} + +static int __init mxc_cpufreq_init(struct cpufreq_policy *policy) +{ + int ret; + int i; + + printk(KERN_INFO "i.MXC CPU frequency driver\n"); + + if (policy->cpu != 0) + return -EINVAL; + + cpu_clk = clk_get(NULL, "cpu_clk"); + if (IS_ERR(cpu_clk)) { + printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); + return PTR_ERR(cpu_clk); + } + + cpu_op_tbl = get_cpu_op(&cpu_op_nr); + + cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000; + cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000; + + imx_freq_table = kmalloc( + sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1), + GFP_KERNEL); + if (!imx_freq_table) { + clk_put(cpu_clk); + return -ENOMEM; + } + + for (i = 0; i < cpu_op_nr; i++) { + imx_freq_table[i].index = i; + imx_freq_table[i].frequency = + cpu_op_tbl[i].cpu_rate / 1000; + + if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min) + cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000; + + if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max) + cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000; + } + + imx_freq_table[i].index = i; + imx_freq_table[i].frequency = CPUFREQ_TABLE_END; + + policy->cur = clk_get_rate(cpu_clk) / 1000; + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; + policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; + + arm_normal_clk = cpu_freq_khz_max * 1000; + + /* Manual states, that PLL stabilizes in two CLK32 periods */ + policy->cpuinfo.transition_latency = 2 / CLK32_FREQ * NANOSECOND; + + ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table); + + if (ret < 0) { + clk_put(cpu_clk); + printk(KERN_ERR "%s: failed to register i.MXC CPUfreq\n", + __func__); + return ret; + } + + cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu); + return 0; +} + +static int mxc_cpufreq_exit(struct cpufreq_policy *policy) +{ + cpufreq_frequency_table_put_attr(policy->cpu); + + set_cpu_freq(arm_normal_clk); + clk_put(cpu_clk); + kfree(imx_freq_table); + return 0; +} + +static struct cpufreq_driver mxc_driver = { + .flags = CPUFREQ_STICKY, + .verify = mxc_verify_speed, + .target = mxc_set_target, + .get = mxc_get_speed, + .init = mxc_cpufreq_init, + .exit = mxc_cpufreq_exit, + .name = "imx", +}; + +static int __devinit mxc_cpufreq_driver_init(void) +{ + return cpufreq_register_driver(&mxc_driver); +} + +static void mxc_cpufreq_driver_exit(void) +{ + cpufreq_unregister_driver(&mxc_driver); +} + +module_init(mxc_cpufreq_driver_init); +module_exit(mxc_cpufreq_driver_exit); + +MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen(a)linaro.org>"); +MODULE_DESCRIPTION("CPUfreq driver for i.MX"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a790bf2..888dddc 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 Juergen Beisert (kernel(a)pengutronix.de) * * This program is free software; you can redistribute it and/or @@ -133,6 +133,24 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mxc91231() (0) #endif +#ifndef __ASSEMBLY__ + +struct cpu_op { + u32 pll_reg; + u32 pll_rate; + u32 cpu_rate; + u32 pdr0_reg; + u32 pdf; + u32 mfi; + u32 mfd; + u32 mfn; + u32 cpu_voltage; + u32 cpu_podf; +}; + +extern struct cpu_op *(*get_cpu_op)(int *op); +#endif + #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) /* These are deprecated, use mx[23][157]_setup_weimcs instead. */ #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) -- 1.6.3.3

14 years, 2 months

cpufreq for freescale mx51

by yong.shen＠linaro.org

Hope this time I can cover all the comments. :)

14 years, 2 months

Linaro gitweb stops working?

by Shawn Guo

I used to access Linaro gitweb below all the time. But from yesterday, I found it stops working for me. Anyone else experienced the same problem, or it's just the problem on my end? http://git.linaro.org/gitweb -- Regards, Shawn

14 years, 2 months

Flavoured toolchains anyone?

by Marcin Juszkiewicz

Some of Linaro developers works with ARM devices older then ARMv7-a architecture. Other people experiments with hard-float ABI. Each of them has to rebuild toolchain for own use and that means playing with components to have them build properly. But it is no more - I made some patches and armel-cross-toolchain-base since 1.53 version + newer source packages for gcc-4.[45]-armel-cross have support for "debian/flavour" file which allows to set some flags related to toolchain build. So far supported things are: - ARM architecture - float ABI - FPU mode - Thumb mode This feature is not merged into regular Ubuntu packages yet as this is work in progress which needs to be cleaned first. http://people.linaro.org/~hrw/armel-cross-toolchain/ has all source packages needed. Regards, -- JID: hrw(a)jabber.org Website: http://marcin.juszkiewicz.com.pl/ LinkedIn: http://www.linkedin.com/in/marcinjuszkiewicz

14 years, 2 months

Notes & Actions: Linaro Graphics Working Group - Oct 18, 2010

by Alexandros Frantzis

Hi, notes and actions from our Monday graphics cross-vendor call are available on the wiki: + https://wiki.linaro.org/WorkingGroups/Middleware/Graphics/Notes/2010-10-18 Details about when and where of this meeting can be found here: + https://wiki.linaro.org/WorkingGroups/Middleware/Graphics#Weekly%20Public%2… Thanks, -- - Alexandros

14 years, 2 months

Re: export kernel clock information to user space

by Amit Kucheria

Adding linaro-dev to cc. Kernel consolidation WG might have comments. On Tue, Oct 12, 2010 at 9:04 AM, Yong Shen <yong.shen(a)linaro.org> wrote: > Hi Amit and Jeremy, > > This is not a patch review. But patch may better present my idea. Basically, > I want to add some code in common clock code to export clock information, so > every platform can benefit. This information is present in a tree-like > pattern. > Currently, each platform uses their own way to show clock info, which is > hard to use a common user space tool to collect information. > For this purpose, I need do the rest: > 1. Add a clock name check in the clkdev_add. We don't accept two clocks with > the same name to clkdev_add, do we? otherwise, it is impossible to create a > tree-like structure under file system, cause no same names under a > directory. > 2. Recursive function creates the clock tree in debugfs, which referred > omap's clock implementation. > 3. Add interface needed to let mach related drivers to report their > information. clk_get_rate is already there. Maybe we need clk_get_flags() > and clk_get_usecount() and more. Agreed, this functionality is necessary for common clk infrastructure to be useful. We've also incorporated this functionality into a tool called powerdebug that'll show runtime state of the clock tree. This is very useful for driver developers. /Amit > Below is the patch, please share your thoughts. > > diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c > index e2b2bb6..2ec09ee 100644 > --- a/arch/arm/common/clkdev.c > +++ b/arch/arm/common/clkdev.c > @@ -19,6 +19,7 @@ > #include <linux/mutex.h> > #include <linux/clk.h> > #include <linux/slab.h> > +#include <linux/debugfs.h> > > #include <asm/clkdev.h> > #include <mach/clkdev.h> > @@ -95,6 +96,21 @@ EXPORT_SYMBOL(clk_put); > > void clkdev_add(struct clk_lookup *cl) > { > + struct clk_lookup *p; > + struct clk *clk = NULL; > + > + list_for_each_entry(p, &clocks, node) { > + if (p->dev_id) { > + if (!cl->dev_id || strcmp(p->dev_id, cl->dev_id)) > + continue; > + } > + if (p->con_id) { > + if (!cl->con_id || strcmp(p->con_id, cl->con_id)) > + continue; > + } > + > + return; > + } > mutex_lock(&clocks_mutex); > list_add_tail(&cl->node, &clocks); > mutex_unlock(&clocks_mutex); > @@ -177,3 +193,131 @@ void clkdev_drop(struct clk_lookup *cl) > kfree(cl); > } > EXPORT_SYMBOL(clkdev_drop); > + > +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) > +/* > + * debugfs support to trace clock tree hierarchy and attributes > + */ > + > +static struct clk_lookup *clk_lookup_get_parent(struct clk *clk) > +{ > + struct clk_lookup *cl; > + > + list_for_each_entry(cl, &clocks, node) { > + if (cl->clk == clk_get_parent(clk)) > + return cl; > + } > + > + return NULL; > +} > +static struct dentry *clk_debugfs_root; > + > +static int clk_debugfs_register_one(struct clk_lookup *cl) > +{ > + int err; > + struct dentry *d, *child, *child_tmp; > + struct clk_lookup *pa = clk_lookup_get_parent(cl->clk); > + char s[255]; > + char *p = s; > + > + if (cl->dev_id && cl->con_id) > + p += sprintf(p, "%s-%s", cl->dev_id, cl->con_id); > + else if (cl->dev_id) > + p += sprintf(p, "%s-NULL", cl->dev_id); > + else if (cl->con_id) > + p += sprintf(p, "NULL-%s", cl->con_id); > + else > + p += sprintf(p, "%s", "unknown"); > + > + printk("create dir %s, %s....\n", s, pa? "nonroot" : "root"); > + d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); > + if (!d) { > + printk("failed to create dir....\n"); > + return -ENOMEM; > + } > + > + cl->dent = d; > + > + if (cl->usecount != NULL) { > + d = debugfs_create_u8("usecount", S_IRUGO, cl->dent, (u8 > *)&cl->usecount); > + if (!d) { > + err = -ENOMEM; > + goto err_out; > + } > + } > + if (cl->rate) { > + d = debugfs_create_u32("rate", S_IRUGO, cl->dent, (u32 > *)&cl->rate); > + if (!d) { > + err = -ENOMEM; > + goto err_out; > + } > + } > + if (cl->flags) { > + d = debugfs_create_x32("flags", S_IRUGO, cl->dent, (u32 > *)&cl->flags); > + if (!d) { > + err = -ENOMEM; > + goto err_out; > + } > + } > + return 0; > + > +err_out: > + printk("err out....\n"); > + return -ENOMEM; > + d = cl->dent; > + list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) > + debugfs_remove(child); > + debugfs_remove(cl->dent); > + return err; > +} > + > +static int clk_debugfs_register(struct clk_lookup *cl) > +{ > + int err; > + struct clk_lookup *pa = clk_lookup_get_parent(cl->clk); > + > + if (pa && !pa->dent) { > + err = clk_debugfs_register(pa); > + if (err) > + return err; > + } > + > + if (!cl->dent) { > + err = clk_debugfs_register_one(cl); > + if (err) > + return err; > + } > + return 0; > +} > + > +static int __init clk_debugfs_init(void) > +{ > + struct clk_lookup *cl; > + struct dentry *d; > + int err; > + > + d = debugfs_create_dir("clock", NULL); > + if (!d) > + return -ENOMEM; > + clk_debugfs_root = d; > + > + list_for_each_entry(cl, &clocks, node) { > + //cl->usercount = clk_get_usercount(cl->clk); > + //cl->flags = clk_get_flags(cl->clk); > + cl->rate = clk_get_rate(cl->clk); > + printk("dev name %s, con name %s\n",\ > + cl->dev_id ? cl->dev_id : NULL,\ > + cl->con_id ? cl->con_id : NULL); > + err = clk_debugfs_register(cl); > + if (err) > + goto err_out; > + } > + return 0; > +err_out: > + printk("on my god ........\n"); > + debugfs_remove_recursive(clk_debugfs_root); > + return err; > +} > +late_initcall(clk_debugfs_init); > + > +#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */ > diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h > index b56c138..51734ef 100644 > --- a/arch/arm/include/asm/clkdev.h > +++ b/arch/arm/include/asm/clkdev.h > @@ -20,6 +20,13 @@ struct clk_lookup { > const char *dev_id; > const char *con_id; > struct clk *clk; > + > +#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) > + short usecount; > + unsigned short flags; > + unsigned long rate; > + struct dentry *dent; > +#endif > }; > > struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id > > > This is the information output from powerdebug after I apply the patch to > mx51 kernel. > / > |-- fec.0-NULL <flags=0x0:rate=66500000:usecount=0> > |-- NULL-gpt <flags=0x0:rate=8000000:usecount=0> > |-- NULL-cko1 <flags=0x0:rate=8000000:usecount=0> > |-- mxc_w1.0-NULL <flags=0x0:rate=8000000:usecount=0> > |-- pata_fsl-NULL <flags=0x0:rate=66500000:usecount=0> > |-- NULL-usb_clk <flags=0x0:rate=60000000:usecount=0> > |-- NULL-usb_utmi_clk <flags=0x0:rate=60000000:usecount=0> > |-- NULL-usb_ahb_clk <flags=0x0:rate=66500000:usecount=0> > |-- NULL-iim_clk <flags=0x0:rate=66500000:usecount=0> > |-- mxc_spi.2-NULL <flags=0x0:rate=66500000:usecount=0> > |-- mxc_spi.1-NULL <flags=0x0:rate=6000000:usecount=0> > |-- mxc_spi.0-NULL <flags=0x0:rate=6000000:usecount=0> > |-- mxc_pwm.1-NULL <flags=0x0:rate=8000000:usecount=0> > |-- mxc_pwm.0-NULL <flags=0x0:rate=8000000:usecount=0> > |-- imx-i2c.1-NULL <flags=0x0:rate=8000000:usecount=0> > |-- imx-i2c.0-NULL <flags=0x0:rate=8000000:usecount=0> > |-- mxcintuart.2-NULL <flags=0x0:rate=66666666:usecount=0> > |-- mxcintuart.1-NULL <flags=0x0:rate=66666666:usecount=0> > |-- mxcintuart.0-NULL <flags=0x0:rate=66666666:usecount=0> > |-- mxc_sdma-sdma_ipg_clk <flags=0x0:rate=66500000:usecount=0> > |-- NULL-gpc_dvfs_clk <flags=0x0:rate=66500000:usecount=0> > |-- NULL-ckil <flags=0x0:rate=32768:usecount=0> > | |-- mxc_rtc.0-NULL <flags=0x0:rate=32768:usecount=0> > | |-- NULL-lpsr_clk <flags=0x0:rate=32768:usecount=0> > |-- NULL-ckih2 <flags=0x0:rate=24576000:usecount=0> > |-- NULL-ckih <flags=0x0:rate=22579200:usecount=0> > |-- NULL-osc <flags=0x0:rate=24000000:usecount=0> > | |-- NULL-spdif_xtal_clk <flags=0x0:rate=24000000:usecount=0> > | | |-- mxc_alsa_spdif.0-NULL <flags=0x0:rate=24000000:usecount=0> > | |-- NULL-usb_phy1_clk <flags=0x0:rate=24000000:usecount=0> > | |-- NULL-lp_apm <flags=0x0:rate=24000000:usecount=0> > | | |-- NULL-ssi_lp_apm_clk <flags=0x0:rate=24000000:usecount=0> > | | | |-- mxc_ssi.1-NULL <flags=0x0:rate=12000000:usecount=0> > | | | | |-- NULL-ssi_ext2_clk <flags=0x0:rate=12000000:usecount=0> > | | | |-- mxc_ssi.0-NULL <flags=0x0:rate=12000000:usecount=0> > | | | | |-- NULL-ssi_ext1_clk <flags=0x0:rate=12000000:usecount=0> > | |-- NULL-pll3 <flags=0x0:rate=216000000:usecount=0> > | | |-- mxc_sim.0-NULL <flags=0x0:rate=54000000:usecount=0> > | | |-- mxc_i2c_hs.3-NULL <flags=0x0:rate=54000000:usecount=0> > | | |-- tve.0-NULL <flags=0x0:rate=216000000:usecount=0> > | | |-- NULL-csi_mclk2 <flags=0x0:rate=54000000:usecount=0> > | | |-- NULL-csi_mclk1 <flags=0x0:rate=54000000:usecount=0> > | | |-- NULL-ipu_di1_clk <flags=0x0:rate=27000000:usecount=0> > | | |-- NULL-ipu_di0_clk <flags=0x0:rate=27000000:usecount=0> > | |-- NULL-pll2 <flags=0x0:rate=665000000:usecount=0> > | | |-- mxsdhci.1-NULL <flags=0x0:rate=166250000:usecount=0> > | | |-- mxsdhci.0-NULL <flags=0x0:rate=166250000:usecount=0> > | | | |-- mxsdhci.3-NULL <flags=0x0:rate=166250000:usecount=0> > | | | |-- mxsdhci.2-NULL <flags=0x0:rate=166250000:usecount=0>/q > | | |-- NULL-usboh3_clk <flags=0x0:rate=66500000:usecount=0> > | | |-- NULL-main_bus_clk <flags=0x0:rate=665000000:usecount=0> > | | | |-- NULL-ahb_clk <flags=0x0:rate=133000000:usecount=0> > | | | | |-- mxc_scc.0-NULL <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-sahara_clk <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-emi_intr_clk.1 > <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-emi_intr_clk.0 > <flags=0x0:rate=133000000:usecount=0> > | | | | |-- mxc_sdma-sdma_ahb_clk > <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-emi_slow_clk <flags=0x0:rate=133000000:usecount=0> > | | | | | |-- NULL-emi_enfc_clk > <flags=0x0:rate=33250000:usecount=0> > | | | | | |-- NULL-nfc_clk <flags=0x0:rate=33250000:usecount=0> > | | | | |-- NULL-ahb_max_clk <flags=0x0:rate=133000000:usecount=0> > | | | |-- NULL-axi_b_clk <flags=0x0:rate=133000000:usecount=0> > | | | | |-- mxc_vpu.0-NULL <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-ipu_clk <flags=0x0:rate=133000000:usecount=0> > | | | | | |-- NULL-mipi_hsp_clk > <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-vpu_core_clk <flags=0x0:rate=133000000:usecount=0> > | | | | |-- NULL-vpu_clk <flags=0x0:rate=133000000:usecount=0> > | | | |-- NULL-axi_a_clk <flags=0x0:rate=166250000:usecount=0> > | | | | |-- NULL-gpu2d_clk <flags=0x0:rate=166250000:usecount=0> > | | | | |-- NULL-garb_clk <flags=0x0:rate=166250000:usecount=0> > | | | | |-- NULL-gpu3d_clk <flags=0x0:rate=166250000:usecount=0> > | |-- NULL-pll1_main_clk <flags=0x0:rate=800000000:usecount=0> > | | |-- NULL-pll1_sw_clk <flags=0x0:rate=800000000:usecount=0> > | | | |-- NULL-ddr_hf_clk <flags=0x0:rate=0:usecount=0> > | | | | |-- NULL-ddr_clk <flags=0x0:rate=200000000:usecount=0> > | | | | | |-- NULL-emi_fast_clk > <flags=0x0:rate=200000000:usecount=0> > | | | |-- NULL-periph_apm_clk <flags=0x0:rate=800000000:usecount=0> > | | | |-- NULL-cpu_clk <flags=0x0:rate=800000000:usecount=0> > > > Yong >

14 years, 2 months

userspace access to cache geometry information

by Peter Maydell

One of the Valgrind subtools is Cachegrind; this is a cache profiler. (It simulates the I1, D1 and L2 caches so it can pinpoint the sources of cache misses in application code.) On x86 Cachegrind automatically queries the host CPU to find out what sort/size of cache it has installed, and by default will simulate that sort of cache. (You can also use command line options to specify a different cache layout to model.) On ARM, the ARMv7 VMSA coprocessor registers which describe the cache geometry are privileged-mode access only. This means cachegrind can't do the same "default cache model is the same as your real CPU" behaviour that it does on x86. Can the kernel folks on this list suggest whether it would be a reasonable idea for the kernel to provide some sort of userspace API so tools like cachegrind can find out the cache geometry? Thanks in advance -- PMM

14 years, 2 months

Flavoured toolchains anyone?

by Marcin Juszkiewicz

14 years, 2 months

Common ARM context save/restore code

by Jon Callan

Vishwa, I have a more-or-less complete set of example code for CPU context save/restore, currently supporting A5/A8/A9 and with planned support for Eagle. It is structured as "firmware" at the moment, but it would be much better if it was integrated into the ARM Linux kernel. The idea is the kernel calls it from CPUidle, and it saves all CPU context and cuts the power. Then when power returns, it restores all CPU context and returns to the kernel as if nothing has happened. It handles just the CPU and cluster context, which on A9mpcore includes MMU, GIC, VFP, SCU, L2cc, Debug, etc. It takes care of cleaning caches and entering/leaving the coherency domain. There is also support for TrustZone, but as you say that's quite platform-specific. So we would need to integrate this with the SoC-specific code somehow. Jon. -- I work Tue/Wed/Fri only Jon Callan, Staff Software Engineer, Processor Division ARM Cambridge / +44 1223 400814 -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

14 years, 2 months

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