Hi All,
This proposal is a call for contribution for a STM driver and its possible usages in kernel tracing infrastructure. I'd like to know if another ARM SoC plan to use or already use STM or some similar hardware enabling the same kind of MIPI trace points. If yes, we can share our works.
What's STM?
Hardware overview: ------------------ This hardware collects and provides simple tracepoints, so a system processor (in our case the main ARM CPU, or some small CPUs and DSPs) can write some data, up to 8 bytes, into a register and out comes a log entry with a time stamp on one of 256 channels. Also hardware tracepoints are supported.
This module external interface is a pad on the chip which complies to the MIPI System Trace Protocol v1.0, and the actual trace output can be read by an electronic probe, not by software so it cannot be intercepted by the CPU and reach Linux userspace.
Bandwidth depends on number of lines & bus frequency (for example on ux500 SoC 4 lines at max 100MHz eg max 400Mbit/s shared between 7 cores). Transmit FIFO size: 256 samples up to 8 bytes.
Software overview: ------------------ - Put this platform driver in drivers/misc kernel tree - API: Configuration functions (trace output clock frequency, trace mode) Enable/disable STM trace functions Alloc/free STM trace channel functions Set of low level atomic trace functions for 1, 2, 4 or 8 bytes with & w/o time stamp Higher level lockless trace function (alloc a channel, output the trace buffer with arbitrary length then free the channel) Expose a debugfs interface for example to read/reset overflow status File IO output console like interface (open, close, write) Implement mmap to expose all STM trace channels memory access to userspace IOCTLs interface for configuration, enable/disable STM, alloc/free STM channels ... - Write atomicity and write order on STM trace channels is ensured by the fact we allocate one channel by execution thread (no concurrent access)
Possible usages: ---------------- - Provide multiple output consoles for traces
- Use it in standard kernel tracing infrastucture, possibilities: - Insert STM trace calls before trace ring buffer write - Substitute time stamping & trace ring buffer by STM - Implement the same functionality than the Ftrace function tracer without lock problem & very low overhead (in 8bytes + auto time stamp on 32bits arch we can have the function entry & its caller like Ftrace do). Remark: Problem is around lock to extract trace in right order when tracepoints buffer size > 8bytes (real time disturbance when tracing), a prototype must be done to find a clever lock system (use multiple channels)
- other ideas...
Many experiments must be done to validate its usage in kernel tracing infrastructure (performance, trace overflow, real time behavior...)
Regards, Philippe
This module external interface is a pad on the chip which complies to the MIPI System Trace Protocol v1.0, and the actual trace output can be read by an electronic probe, not by software so it cannot be intercepted by the CPU and reach Linux userspace.
I'm not an expert here, but my understanding is that the architecture allows to put all the trace data to both trace port and ETB (Embedded Trace Buffer) at the same time. It's just that the STM (along with ETM/PTM and other xTMs ;-) outputs its data via funnel to a trace bus, and the bus can feed both the buffer and the port.
And as it is possible to read the ETB content - see arch/arm/kernel/etm.c
I'd like to know if another ARM SoC plan to use or already use STM or some similar hardware enabling the same kind of MIPI trace points. If yes, we can share our works.
Would you be so kind to talk to Ian Spray Ian.Spray@arm.com? He is doing stuff around CoreSight drivers...
Cheers!
Paweł
On 7 February 2011 13:16, Pawel Moll pawel.moll@arm.com wrote:
This module external interface is a pad on the chip which complies to the MIPI System Trace Protocol v1.0, and the actual trace output can be read by an electronic probe, not by software so it cannot be intercepted by the CPU and reach Linux userspace.
I'm not an expert here, but my understanding is that the architecture allows to put all the trace data to both trace port and ETB (Embedded Trace Buffer) at the same time. It's just that the STM (along with ETM/PTM and other xTMs ;-) outputs its data via funnel to a trace bus, and the bus can feed both the buffer and the port.
And as it is possible to read the ETB content - see arch/arm/kernel/etm.c
Sorry, STM is not in the same family that xTM which trace execution & data
flow of an ARM core (non intrusive). STM is more at applicative trace level like printf (output console only).
I'd like to know if another ARM SoC plan to use or already use STM or some similar hardware enabling the same kind of MIPI trace points. If yes, we can share our works.
Would you be so kind to talk to Ian Spray Ian.Spray@arm.com? He is doing stuff around CoreSight drivers...
Cheers!
Paweł
Regards Philippe
Morning,
y, STM is not in the same family that xTM which trace execution & data flow of an ARM core (non intrusive). STM is more at applicative trace level like printf (output console only).
Well, what I mean is that xTMs - ETM/PTM tracing execution flow, ITM behaving like mentioned printf (STM's older sibling), etc. - are just source of data in the CoreSight architecture, connected to a (shared) trace bus, which then has sinks like trace port and trace buffer. Have a look at this diagram:
http://www.arm.com/images/CoreSight_Diagram.jpg
And as far as I know STM can be configured to do the same, but you should really talk to Ian - he's the resident expert in this subject :-) I'll forward him your questions.
Cheers!
Paweł
Thanks Pawel, now I understand better the Coresight architecture, but STM has its own hardware architecture independent to Coresight not connected to Debug Bus nor Funnel Trace bus. STM exposes a set of registers to our main CPU for its control, it is connected to our ST-BUS through interconnect. ITM appears to have the same functions as our STM, perhaps we can share their usages or more.
Regards Philippe
On 8 February 2011 11:20, Pawel Moll pawel.moll@arm.com wrote:
Morning,
y, STM is not in the same family that xTM which trace execution & data flow of an ARM core (non intrusive). STM is more at applicative trace level like printf (output console only).
Well, what I mean is that xTMs - ETM/PTM tracing execution flow, ITM behaving like mentioned printf (STM's older sibling), etc. - are just source of data in the CoreSight architecture, connected to a (shared) trace bus, which then has sinks like trace port and trace buffer. Have a look at this diagram:
http://www.arm.com/images/CoreSight_Diagram.jpg
And as far as I know STM can be configured to do the same, but you should really talk to Ian - he's the resident expert in this subject :-) I'll forward him your questions.
Cheers!
Paweł
On Tue, Feb 8, 2011 at 11:20 AM, Pawel Moll pawel.moll@arm.com wrote:
And as far as I know STM can be configured to do the same, but you should really talk to Ian - he's the resident expert in this subject :-) I'll forward him your questions.
Ah I think there is a misunderstanding here, damn these TLA:s.
STM in U8500 == ST-Ericsson System Trace Module STM in coresight == ARM System Trace Macrocell
Two completely different hardware blocks, synthesized at completely different locations in the system. We indeed have the "other" STM as well :-P
Yours, Linus Walleij
Ah I think there is a misunderstanding here, damn these TLA:s.
STM in U8500 == ST-Ericsson System Trace Module STM in coresight == ARM System Trace Macrocell
Right... I've just nearly died laughing... ;-)
We could have discussed technical details for a looong time then :-)
Thanks for being vigilant!
Paweł