Chander Kashyap (2): Exynos: PWM: Add TCMPB3 field in pwm structure Exynos: Fix ARM Clock frequency calculation
arch/arm/cpu/armv7/exynos/clock.c | 9 ++++++--- arch/arm/include/asm/arch-exynos/pwm.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-)
Add TCMPB3 field in pwm structure, earliar this was res1.
Signed-off-by: Chander Kashyap chander.kashyap@linaro.org --- arch/arm/include/asm/arch-exynos/pwm.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/pwm.h b/arch/arm/include/asm/arch-exynos/pwm.h index d0cf3cb..3e95160 100644 --- a/arch/arm/include/asm/arch-exynos/pwm.h +++ b/arch/arm/include/asm/arch-exynos/pwm.h @@ -57,7 +57,7 @@ struct s5p_timer { unsigned int tcmpb2; unsigned int tcnto2; unsigned int tcntb3; - unsigned int res1; + unsigned int tcmpb3; unsigned int tcnto3; unsigned int tcntb4; unsigned int tcnto4;
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows: ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
Signed-off-by: Chander Kashyap chander.kashyap@linaro.org --- arch/arm/cpu/armv7/exynos/clock.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 64de262..17ff012 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -103,14 +103,17 @@ static unsigned long exynos4_get_arm_clk(void) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll; - unsigned int apll_ratio; + unsigned int core_ratio; + unsigned int core2_ratio;
div = readl(&clk->div_cpu0);
/* APLL_RATIO: [26:24] */ - apll_ratio = (div >> 24) & 0x7; + core_ratio = (div >> 0) & 0x7; + core2_ratio = (div >> 28) & 0x7;
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + dout_apll = get_pll_clk(APLL) / (core_ratio + 1); + dout_apll /= (core2_ratio + 1);
return dout_apll; }
Dear Chander Kashyap,
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
- dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
- dout_apll /= (core2_ratio + 1);
This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
On 19 December 2011 13:27, Wolfgang Denk wd@denx.de wrote:
Dear Chander Kashyap,
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);dout_apll /= (core2_ratio + 1);This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Below is the scenario of selection. ____________ MOUTAPLL --------------->| MUX_CORE |------------>MOUTCORE MOUTMPLL --------------->|____________|
Here MOUTAPLL is selected as input. So Parent is correct.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Bus error -- driver executed.
Dear Wolfgang Denk,
On 19 December 2011 13:50, Chander Kashyap chander.kashyap@linaro.orgwrote:
Dear Wolfgang Denk,
On 19 December 2011 13:27, Wolfgang Denk wd@denx.de wrote:
Dear Chander Kashyap,
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
Yes comment need to be modified.
...or is this just missing a paren?
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);dout_apll /= (core2_ratio + 1);This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Below is the scenario of selection. ____________ MOUTAPLL --------------->| MUX_CORE |------------>MOUTCORE MOUTMPLL --------------->|____________|
Here MOUTAPLL is selected as input. So Parent is correct.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Bus error -- driver executed.
-- with warm regards, Chander Kashyap
Dear Chander Kashyap,
In message CANuQgHHq_+aZ6z100agOuaumeUyXwH-HL6aNPgrtOWBadEQaHQ@mail.gmail.com you wrote:
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);dout_apll /= (core2_ratio + 1);This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Below is the scenario of selection. ____________ MOUTAPLL --------------->| MUX_CORE |------------>MOUTCORE MOUTMPLL --------------->|____________|
Here MOUTAPLL is selected as input. So Parent is correct.
You miss the point.
Your comment:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
is missing one opening brace. Depending on where you insert it, the code may or may not match.
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
On 19 December 2011 14:29, Wolfgang Denk wd@denx.de wrote:
Dear Chander Kashyap,
In message < CANuQgHHq_+aZ6z100agOuaumeUyXwH-HL6aNPgrtOWBadEQaHQ@mail.gmail.com> you wrote:
In message <
1324275424-29468-3-git-send-email-chander.kashyap@linaro.org>
you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);dout_apll /= (core2_ratio + 1);This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Below is the scenario of selection. ____________ MOUTAPLL --------------->| MUX_CORE |------------>MOUTCORE MOUTMPLL --------------->|____________|
Here MOUTAPLL is selected as input. So Parent is correct.
You miss the point.
Your comment:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)is missing one opening brace. Depending on where you insert it, the code may or may not match.
Thanks, I got it. Resend it again.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de "A little knowledge is a dangerous thing." - Doug Gwyn
On 19 December 2011 16:57, Wolfgang Denk wd@denx.de wrote:
Dear Chander Kashyap,
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
- dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
- dout_apll /= (core2_ratio + 1);
This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Wolfgang, you are right. ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) is right.
Dear Chander Kashyap,
/* APLL_RATIO: [26:24] */
Please fix this comment also.
- apll_ratio = (div >> 24) & 0x7;
- core_ratio = (div >> 0) & 0x7;
- core2_ratio = (div >> 28) & 0x7;
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
This output is not dout_apll. Please fix it.
- dout_apll /= (core2_ratio + 1);
return dout_apll;
Thanks Minkyu Kang
On 19 December 2011 13:56, Minkyu Kang promsoft@gmail.com wrote:
On 19 December 2011 16:57, Wolfgang Denk wd@denx.de wrote:
Dear Chander Kashyap,
In message 1324275424-29468-3-git-send-email-chander.kashyap@linaro.org
you wrote:
Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calcuating it as follows:
Um.... Comment and code disagree:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
...or is this just missing a paren?
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);dout_apll /= (core2_ratio + 1);This gives
ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
Please check if this is correct.
Wolfgang, you are right. ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) is right.
I will fix the comment.
Dear Chander Kashyap,
/* APLL_RATIO: [26:24] */Please fix this comment also.
Yes
apll_ratio = (div >> 24) & 0x7;
core_ratio = (div >> 0) & 0x7;core2_ratio = (div >> 28) & 0x7;
dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
dout_apll = get_pll_clk(APLL) / (core_ratio + 1);This output is not dout_apll. Please fix it.
I will rename the output.
dout_apll /= (core2_ratio + 1); return dout_apll;Thanks Minkyu Kang -- from. prom. www.promsoft.net
-
Chander Kashyap -
Minkyu Kang -
Wolfgang Denk